[llvm-commits] [llvm] r137466 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

[Bruno Cardoso Lopes]

Thanks Nadav!

On Fri, Aug 12, 2011 at 10:15 AM, Nadav Rotem <nadav.rotem at intel.com> wrote:
> Author: nadav
> Date: Fri Aug 12 12:15:04 2011
> New Revision: 137466
>
> URL: http://llvm.org/viewvc/llvm-project?rev=137466&view=rev
> Log:
> Revert r137310 because it does not optimize any code on ToT
>
> Modified:
>    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=137466&r1=137465&r2=137466&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Aug 12 12:15:04 2011
> @@ -213,7 +213,6 @@
>     SDValue visitLOAD(SDNode *N);
>     SDValue visitSTORE(SDNode *N);
>     SDValue visitINSERT_VECTOR_ELT(SDNode *N);
> -    SDValue visitINSERT_SUBVECTOR(SDNode *N);
>     SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
>     SDValue visitBUILD_VECTOR(SDNode *N);
>     SDValue visitCONCAT_VECTORS(SDNode *N);
> @@ -1103,7 +1102,6 @@
>   case ISD::LOAD:               return visitLOAD(N);
>   case ISD::STORE:              return visitSTORE(N);
>   case ISD::INSERT_VECTOR_ELT:  return visitINSERT_VECTOR_ELT(N);
> -  case ISD::INSERT_SUBVECTOR:  return visitINSERT_SUBVECTOR(N);
>   case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
>   case ISD::BUILD_VECTOR:       return visitBUILD_VECTOR(N);
>   case ISD::CONCAT_VECTORS:     return visitCONCAT_VECTORS(N);
> @@ -7138,36 +7136,6 @@
>   }
>  }
>
> -SDValue DAGCombiner::visitINSERT_SUBVECTOR(SDNode* N) {
> -  DebugLoc dl = N->getDebugLoc();
> -  EVT VT = N->getValueType(0);
> -  // When inserting a subvector into a vector, make sure to start
> -  // inserting starting the Zero index. This will allow making the
> -  // first insertion using a subreg insertion, and save a register.
> -  SDValue V = N->getOperand(0);
> -  if (V->getOpcode() == ISD::INSERT_SUBVECTOR && V->hasOneUse()) {
> -    ConstantSDNode *N_Idx = dyn_cast<ConstantSDNode>(N->getOperand(2));
> -    ConstantSDNode *V_Idx = dyn_cast<ConstantSDNode>(V->getOperand(2));
> -    uint64_t Nc = N_Idx->getZExtValue();
> -    uint64_t Vc = V_Idx->getZExtValue();
> -
> -    // Reorder insertion to vector
> -    if (Nc < Vc) {
> -      SDValue NewV = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VT,
> -                                 V->getOperand(0),
> -                                 N->getOperand(1),
> -                                 N->getOperand(2));
> -      return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VT,
> -                         NewV,
> -                         V->getOperand(1),
> -                         V->getOperand(2));
> -    }
> -  }
> -
> -  return SDValue();
> -}
> -
> -
>  /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
>  /// an AND to a vector_shuffle with the destination vector and a zero vector.
>  /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
>
>
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-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc