[llvm-commits] [llvm] r137370 - /llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

[Owen Anderson]

Author: resistor
Date: Thu Aug 11 17:08:38 2011
New Revision: 137370

URL: http://llvm.org/viewvc/llvm-project?rev=137370&view=rev
Log:
Add another accidentally omitted predicate operand.

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=137370&r1=137369&r2=137370&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Thu Aug 11 17:08:38 2011
@@ -2491,6 +2491,7 @@
   unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
   unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
   unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
 
   if (Inst.getOpcode() == ARM::STREXD)
     if (!DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
@@ -2501,6 +2502,7 @@
   if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false;
   if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false;
   if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
 
   return true;
 }