[llvm-commits] [llvm] r137356 - in /llvm/trunk/lib/Target/ARM: ARMInstrInfo.td Disassembler/ARMDisassembler.cpp
Owen Anderson
resistor at mac.com
Thu Aug 11 14:34:59 PDT 2011
Author: resistor
Date: Thu Aug 11 16:34:58 2011
New Revision: 137356
URL: http://llvm.org/viewvc/llvm-project?rev=137356&view=rev
Log:
Fix decoding support for STREXD and LDREXD.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=137356&r1=137355&r2=137356&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Aug 11 16:34:58 2011
@@ -4090,7 +4090,9 @@
NoItinerary, "ldrex", "\t$Rt, $addr", []>;
let hasExtraDefRegAllocReq = 1 in
def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr),
- NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []>;
+ NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []> {
+ let DecoderMethod = "DecodeDoubleRegExclusive";
+}
}
let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
@@ -4105,7 +4107,9 @@
let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
def STREXD : AIstrex<0b01, (outs GPR:$Rd),
(ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
- NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []>;
+ NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> {
+ let DecoderMethod = "DecodeDoubleRegExclusive";
+}
// Clear-Exclusive is for disassembly only.
def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=137356&r1=137355&r2=137356&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Thu Aug 11 16:34:58 2011
@@ -135,6 +135,8 @@
uint64_t Address, const void *Decoder);
static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
+static bool DecodeDoubleRegExclusive(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder);
static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
@@ -2481,3 +2483,24 @@
Inst.addOperand(MCOperand::CreateImm(Val));
return true;
}
+
+static bool DecodeDoubleRegExclusive(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
+ unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
+ unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
+ unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+
+ if (Inst.getOpcode() == ARM::STREXD)
+ if (!DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+
+ if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false;
+ if (Rd == Rn || Rd == Rt || Rd == Rt+1) return false;
+
+ if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false;
+ if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false;
+ if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+
+ return true;
+}
+
+
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