[llvm-commits] [llvm] r137347 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassembler.cpp test/MC/Disassembler/ARM/arm-tests.txt

[Owen Anderson]

Author: resistor
Date: Thu Aug 11 15:47:56 2011
New Revision: 137347

URL: http://llvm.org/viewvc/llvm-project?rev=137347&view=rev
Log:
Fix decoding for indexed STRB and LDRB.  Fixes <rdar://problem/9926161>.

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=137347&r1=137346&r2=137347&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Thu Aug 11 15:47:56 2011
@@ -941,6 +941,8 @@
   switch (Inst.getOpcode()) {
     case ARM::STR_POST_IMM:
     case ARM::STR_POST_REG:
+    case ARM::STRB_POST_IMM:
+    case ARM::STRB_POST_REG:
     case ARM::STRTr:
     case ARM::STRTi:
     case ARM::STRBT_POST_REG:
@@ -957,6 +959,8 @@
   switch (Inst.getOpcode()) {
     case ARM::LDR_POST_IMM:
     case ARM::LDR_POST_REG:
+    case ARM::LDRB_POST_IMM:
+    case ARM::LDRB_POST_REG:
     case ARM::LDR_PRE:
     case ARM::LDRBT_POST_REG:
     case ARM::LDRBT_POST_IMM:

Modified: llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt?rev=137347&r1=137346&r2=137347&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt Thu Aug 11 15:47:56 2011
@@ -305,3 +305,6 @@
 
 # CHECK:        andeq   r0, r0, r0, lsr #32
 0x20 0x00 0x00 0x00
+
+# CHECK: strb	r3, [r2], #1
+0x01 0x30 0xc2 0xe4