[llvm-commits] [llvm] r137337 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/Disassembler/ARMDisassembler.cpp test/MC/ARM/arm-memory-instructions.s
Jim Grosbach
grosbach at apple.com
Thu Aug 11 13:04:56 PDT 2011
Author: grosbach
Date: Thu Aug 11 15:04:56 2011
New Revision: 137337
URL: http://llvm.org/viewvc/llvm-project?rev=137337&view=rev
Log:
ARM STRBT assembly parsing and encoding.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
llvm/trunk/test/MC/ARM/arm-memory-instructions.s
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=137337&r1=137336&r2=137337&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Aug 11 15:04:56 2011
@@ -2350,35 +2350,47 @@
// STRT, STRBT, and STRHT
-def STRTr : AI2stridxT<0, 0, (outs GPR:$Rn_wb),
- (ins GPR:$Rt, ldst_so_reg:$addr),
- IndexModePost, StFrm, IIC_iStore_ru,
- "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
- [/* For disassembly only; pattern left blank */]> {
+def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
+ (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
+ IndexModePost, StFrm, IIC_iStore_bh_ru,
+ "strbt", "\t$Rt, $addr, $offset",
+ "$addr.base = $Rn_wb", []> {
+ // {12} isAdd
+ // {11-0} imm12/Rm
+ bits<14> offset;
+ bits<4> addr;
let Inst{25} = 1;
+ let Inst{23} = offset{12};
let Inst{21} = 1; // overwrite
+ let Inst{19-16} = addr;
+ let Inst{11-5} = offset{11-5};
let Inst{4} = 0;
- let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
+ let Inst{3-0} = offset{3-0};
let DecoderMethod = "DecodeAddrMode2IdxInstruction";
}
-def STRTi : AI2stridxT<0, 0, (outs GPR:$Rn_wb),
- (ins GPR:$Rt, addrmode_imm12:$addr),
- IndexModePost, StFrm, IIC_iStore_ru,
- "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
- [/* For disassembly only; pattern left blank */]> {
+def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
+ (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
+ IndexModePost, StFrm, IIC_iStore_bh_ru,
+ "strbt", "\t$Rt, $addr, $offset",
+ "$addr.base = $Rn_wb", []> {
+ // {12} isAdd
+ // {11-0} imm12/Rm
+ bits<14> offset;
+ bits<4> addr;
let Inst{25} = 0;
+ let Inst{23} = offset{12};
let Inst{21} = 1; // overwrite
- let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
+ let Inst{19-16} = addr;
+ let Inst{11-0} = offset{11-0};
let DecoderMethod = "DecodeAddrMode2IdxInstruction";
}
-
-def STRBTr : AI2stridxT<1, 0, (outs GPR:$Rn_wb),
- (ins GPR:$Rt, ldst_so_reg:$addr),
- IndexModePost, StFrm, IIC_iStore_bh_ru,
- "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
- [/* For disassembly only; pattern left blank */]> {
+def STRTr : AI2stridxT<0, 0, (outs GPR:$Rn_wb),
+ (ins GPR:$Rt, ldst_so_reg:$addr),
+ IndexModePost, StFrm, IIC_iStore_ru,
+ "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
+ [/* For disassembly only; pattern left blank */]> {
let Inst{25} = 1;
let Inst{21} = 1; // overwrite
let Inst{4} = 0;
@@ -2386,11 +2398,11 @@
let DecoderMethod = "DecodeAddrMode2IdxInstruction";
}
-def STRBTi : AI2stridxT<1, 0, (outs GPR:$Rn_wb),
- (ins GPR:$Rt, addrmode_imm12:$addr),
- IndexModePost, StFrm, IIC_iStore_bh_ru,
- "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
- [/* For disassembly only; pattern left blank */]> {
+def STRTi : AI2stridxT<0, 0, (outs GPR:$Rn_wb),
+ (ins GPR:$Rt, addrmode_imm12:$addr),
+ IndexModePost, StFrm, IIC_iStore_ru,
+ "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
+ [/* For disassembly only; pattern left blank */]> {
let Inst{25} = 0;
let Inst{21} = 1; // overwrite
let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=137337&r1=137336&r2=137337&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Thu Aug 11 15:04:56 2011
@@ -939,8 +939,8 @@
case ARM::STR_POST_REG:
case ARM::STRTr:
case ARM::STRTi:
- case ARM::STRBTr:
- case ARM::STRBTi:
+ case ARM::STRBT_POST_REG:
+ case ARM::STRBT_POST_IMM:
if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
break;
default:
Modified: llvm/trunk/test/MC/ARM/arm-memory-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm-memory-instructions.s?rev=137337&r1=137336&r2=137337&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/arm-memory-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/arm-memory-instructions.s Thu Aug 11 15:04:56 2011
@@ -375,3 +375,17 @@
@ CHECK: strb r7, [r12, -r3, lsl #5] @ encoding: [0x83,0x72,0x4c,0xe7]
@ CHECK: strb sp, [r7], r2, asr #12 @ encoding: [0x42,0xd6,0xc7,0xe6]
+
+ at ------------------------------------------------------------------------------
+@ STRBT
+ at ------------------------------------------------------------------------------
+@ FIXME: Optional offset operand.
+ strbt r6, [r2], #12
+ strbt r5, [r6], #-13
+ strbt r4, [r9], r5
+ strbt r3, [r8], -r2, lsl #3
+
+@ CHECK: strbt r6, [r2], #12 @ encoding: [0x0c,0x60,0xe2,0xe4]
+@ CHECK: strbt r5, [r6], #-13 @ encoding: [0x0d,0x50,0x66,0xe4]
+@ CHECK: strbt r4, [r9], r5 @ encoding: [0x05,0x40,0xe9,0xe6]
+@ CHECK: strbt r3, [r8], -r2, lsl #3 @ encoding: [0x82,0x31,0x68,0xe6]
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