[llvm-commits] [llvm] r137325 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassembler.cpp test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt

[Owen Anderson]

Author: resistor
Date: Thu Aug 11 14:00:18 2011
New Revision: 137325

URL: http://llvm.org/viewvc/llvm-project?rev=137325&view=rev
Log:
Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=137325&r1=137324&r2=137325&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Thu Aug 11 14:00:18 2011
@@ -978,6 +978,8 @@
   else if (!P && writeback)
     idx_mode = ARMII::IndexModePost;
 
+  if (writeback && (Rn == 15 || Rn == Rt)) return false; // UNPREDICTABLE
+
   if (reg) {
     if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false;
     ARM_AM::ShiftOpc Opc = ARM_AM::lsl;

Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt?rev=137325&r1=137324&r2=137325&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt Thu Aug 11 14:00:18 2011
@@ -1,11 +1,10 @@
 # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
-# XFAIL: *
 
 # Opcode=140 Name=LDRB_POST Format=ARM_FORMAT_LDFRM(6)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
 # -------------------------------------------------------------------------------------------------
 # | 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 0: 1| 0: 1: 1: 1| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 0: 1|
 # -------------------------------------------------------------------------------------------------
-# 
+#
 # if wback && (n == 15 || n == t) then UNPREDICTABLE
 0x05 0x70 0xd7 0xe6