[llvm-commits] [llvm] r137318 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp test/CodeGen/ARM/str_pre-2.ll test/MC/ARM/basic-arm-instructions.s

[Jim Grosbach]

Author: grosbach
Date: Thu Aug 11 13:07:11 2011
New Revision: 137318

URL: http://llvm.org/viewvc/llvm-project?rev=137318&view=rev
Log:
ARM push of a single register encodes as pre-indexed STR.

Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
    llvm/trunk/test/CodeGen/ARM/str_pre-2.ll
    llvm/trunk/test/MC/ARM/basic-arm-instructions.s

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=137318&r1=137317&r2=137318&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Aug 11 13:07:11 2011
@@ -2879,6 +2879,22 @@
       Inst = TmpInst;
     }
     break;
+  case ARM::STMDB_UPD:
+    // If this is a store of a single register via a 'push', then we should use
+    // a pre-indexed STR instruction instead, per the ARM ARM.
+    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
+        Inst.getNumOperands() == 5) {
+      MCInst TmpInst;
+      TmpInst.setOpcode(ARM::STR_PRE_IMM);
+      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
+      TmpInst.addOperand(Inst.getOperand(4)); // Rt
+      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
+      TmpInst.addOperand(MCOperand::CreateImm(-4));
+      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
+      TmpInst.addOperand(Inst.getOperand(3));
+      Inst = TmpInst;
+    }
+    break;
   }
 }
 

Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=137318&r1=137317&r2=137318&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Thu Aug 11 13:07:11 2011
@@ -88,6 +88,13 @@
     printRegisterList(MI, 4, O);
     return;
   }
+  if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
+      MI->getOperand(3).getImm() == -4) {
+    O << '\t' << "push";
+    printPredicateOperand(MI, 4, O);
+    O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
+    return;
+  }
 
   // A8.6.122 POP
   if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&

Modified: llvm/trunk/test/CodeGen/ARM/str_pre-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/str_pre-2.ll?rev=137318&r1=137317&r2=137318&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/str_pre-2.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/str_pre-2.ll Thu Aug 11 13:07:11 2011
@@ -7,7 +7,7 @@
 
 define i64 @t(i64 %a) nounwind readonly {
 entry:
-; CHECK: str lr, [sp, #-4]!
+; CHECK: push {lr}
 ; CHECK: pop {lr}
 	%0 = load i64** @b, align 4
 	%1 = load i64* %0, align 4

Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=137318&r1=137317&r2=137318&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Thu Aug 11 13:07:11 2011
@@ -1071,8 +1071,7 @@
         push {r7}
         push {r7, r8, r9, r10}
 
-@ FIXME: push of a single register should encode as "str r7, [sp, #-4]!"
-@ CHECK-FIXME: push	{r7}                    @ encoding: [0x04,0x70,0x2d,0xe5]
+@ CHECK: push	{r7}                    @ encoding: [0x04,0x70,0x2d,0xe5]
 @ CHECK: push	{r7, r8, r9, r10}       @ encoding: [0x80,0x07,0x2d,0xe9]