[llvm-commits] [llvm] r137144 - in /llvm/trunk: lib/Target/ARM/ lib/Target/ARM/Disassembler/ test/MC/Disassembler/ARM/ utils/TableGen/
Nick Lewycky
nicholas at mxc.ca
Tue Aug 9 22:06:37 PDT 2011
Owen Anderson wrote:
> Author: resistor
> Date: Tue Aug 9 15:55:18 2011
> New Revision: 137144
>
> URL: http://llvm.org/viewvc/llvm-project?rev=137144&view=rev
> Log:
> Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
> This new disassembler can correctly decode all the testcases that the old one did, though
> some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
> operand checking as the old one was.
>
> Removed:
> llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
> llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.h
> llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
> Modified:
> llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
> llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
> llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
> llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
> llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
> llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.h
> llvm/trunk/lib/Target/ARM/Disassembler/CMakeLists.txt
> llvm/trunk/lib/Target/ARM/Makefile
> llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-BFI-arm.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-DSB-arm.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-LSL-regform.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-MCR-arm.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-RSC-arm.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-SRS-arm.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-SSAT-arm.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-STRBrs-arm.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt
> llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt
> llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=137144&r1=137143&r2=137144&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Aug 9 15:55:18 2011
> @@ -152,6 +152,7 @@
> (ops (i32 14), (i32 zero_reg))> {
> let PrintMethod = "printPredicateOperand";
> let ParserMatchClass = CondCodeOperand;
> + let DecoderMethod = "DecodePredicateOperand";
Tab.
> }
>
> // Conditional code result for instructions whose 's' bit is set, e.g. subs.
> @@ -160,6 +161,7 @@
> let EncoderMethod = "getCCOutOpValue";
> let PrintMethod = "printSBitModifierOperand";
> let ParserMatchClass = CCOutOperand;
> + let DecoderMethod = "DecodeCCOutOperand";
Tab.
> }
>
> // Same as cc_out except it defaults to setting CPSR.
> @@ -167,6 +169,7 @@
> let EncoderMethod = "getCCOutOpValue";
> let PrintMethod = "printSBitModifierOperand";
> let ParserMatchClass = CCOutOperand;
> + let DecoderMethod = "DecodeCCOutOperand";
Tab.
> }
>
> // ARM special operands for disassembly only.
> @@ -199,15 +202,19 @@
> // 64 64 -<imm> is encoded in imm6<5:0>
> def shr_imm8 : Operand<i32> {
> let EncoderMethod = "getShiftRight8Imm";
> + let DecoderMethod = "DecodeShiftRight8Imm";
> }
> def shr_imm16 : Operand<i32> {
> let EncoderMethod = "getShiftRight16Imm";
> + let DecoderMethod = "DecodeShiftRight16Imm";
> }
> def shr_imm32 : Operand<i32> {
> let EncoderMethod = "getShiftRight32Imm";
> + let DecoderMethod = "DecodeShiftRight32Imm";
> }
> def shr_imm64 : Operand<i32> {
> let EncoderMethod = "getShiftRight64Imm";
> + let DecoderMethod = "DecodeShiftRight64Imm";
> }
>
> //===----------------------------------------------------------------------===//
> @@ -579,6 +586,8 @@
> let Inst{11-8} = addr{7-4}; // imm7_4/zero
> let Inst{7-4} = op;
> let Inst{3-0} = addr{3-0}; // imm3_0/Rm
> +
> + let DecoderMethod = "DecodeAddrMode3Instruction";
> }
>
> class AI3ldstidx<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops,
> @@ -1265,6 +1274,7 @@
> let AsmString = !strconcat(opc, "${p}", asm);
> let Pattern = pattern;
> let PostEncoderMethod = "VFPThumb2PostEncoder";
> + let DecoderNamespace = "VFP";
> list<Predicate> Predicates = [HasVFP2];
> }
>
> @@ -1280,6 +1290,7 @@
> let AsmString = asm;
> let Pattern = pattern;
> let PostEncoderMethod = "VFPThumb2PostEncoder";
> + let DecoderNamespace = "VFP";
> list<Predicate> Predicates = [HasVFP2];
> }
>
> @@ -1597,6 +1608,7 @@
> let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
> let Pattern = pattern;
> list<Predicate> Predicates = [HasNEON];
> + let DecoderNamespace = "NEON";
> }
>
> // Same as NeonI except it does not have a "data type" specifier.
> @@ -1609,6 +1621,7 @@
> let AsmString = !strconcat(opc, "${p}", "\t", asm);
> let Pattern = pattern;
> list<Predicate> Predicates = [HasNEON];
> + let DecoderNamespace = "NEON";
> }
>
> class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
> @@ -1700,6 +1713,7 @@
> let Inst{24} = SIMM{7};
> let Inst{18-16} = SIMM{6-4};
> let Inst{3-0} = SIMM{3-0};
> + let DecoderMethod = "DecodeNEONModImmInstruction";
> }
>
> // NEON 2 vector register format.
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=137144&r1=137143&r2=137144&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Aug 9 15:55:18 2011
> @@ -315,6 +315,7 @@
> def brtarget : Operand<OtherVT> {
> let EncoderMethod = "getBranchTargetOpValue";
> let OperandType = "OPERAND_PCREL";
> + let DecoderMethod = "DecodeT2BROperand";
> }
>
> // FIXME: get rid of this one?
> @@ -343,6 +344,7 @@
> // Encoded the same as branch targets.
> let EncoderMethod = "getARMBranchTargetOpValue";
> let OperandType = "OPERAND_PCREL";
> + let DecoderMethod = "DecodeBLTargetOperand";
Tab.
> }
>
>
> @@ -352,6 +354,7 @@
> let EncoderMethod = "getRegisterListOpValue";
> let ParserMatchClass = RegListAsmOperand;
> let PrintMethod = "printRegisterList";
> + let DecoderMethod = "DecodeRegListOperand";
> }
>
> def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
> @@ -359,6 +362,7 @@
> let EncoderMethod = "getRegisterListOpValue";
> let ParserMatchClass = DPRRegListAsmOperand;
> let PrintMethod = "printRegisterList";
> + let DecoderMethod = "DecodeDPRRegListOperand";
> }
>
> def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
> @@ -366,6 +370,7 @@
> let EncoderMethod = "getRegisterListOpValue";
> let ParserMatchClass = SPRRegListAsmOperand;
> let PrintMethod = "printRegisterList";
> + let DecoderMethod = "DecodeSPRRegListOperand";
> }
>
> // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
> @@ -385,6 +390,7 @@
>
> def neon_vcvt_imm32 : Operand<i32> {
> let EncoderMethod = "getNEONVcvtImm32OpValue";
> + let DecoderMethod = "DecodeVCVTImmOperand";
> }
>
> // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
> @@ -431,6 +437,7 @@
> [shl, srl, sra, rotr]> {
> let EncoderMethod = "getSORegRegOpValue";
> let PrintMethod = "printSORegRegOperand";
> + let DecoderMethod = "DecodeSORegRegOperand";
> let ParserMatchClass = ShiftedRegAsmOperand;
> let MIOperandInfo = (ops GPR, GPR, i32imm);
> }
> @@ -441,6 +448,7 @@
> [shl, srl, sra, rotr]> {
> let EncoderMethod = "getSORegImmOpValue";
> let PrintMethod = "printSORegImmOperand";
> + let DecoderMethod = "DecodeSORegImmOperand";
> let ParserMatchClass = ShiftedImmAsmOperand;
> let MIOperandInfo = (ops GPR, i32imm);
> }
> @@ -451,6 +459,7 @@
> [shl,srl,sra,rotr]> {
> let EncoderMethod = "getSORegRegOpValue";
> let PrintMethod = "printSORegRegOperand";
> + let DecoderMethod = "DecodeSORegRegOperand";
> let MIOperandInfo = (ops GPR, GPR, i32imm);
> }
>
> @@ -460,6 +469,7 @@
> [shl,srl,sra,rotr]> {
> let EncoderMethod = "getSORegImmOpValue";
> let PrintMethod = "printSORegImmOperand";
> + let DecoderMethod = "DecodeSORegImmOperand";
> let MIOperandInfo = (ops GPR, i32imm);
> }
>
> @@ -472,6 +482,7 @@
> }]> {
> let EncoderMethod = "getSOImmOpValue";
> let ParserMatchClass = SOImmAsmOperand;
> + let DecoderMethod = "DecodeSOImmOperand";
Tab.
> }
>
> // Break so_imm's up into two pieces. This handles immediates with up to 16
> @@ -552,6 +563,7 @@
> }]> {
> let EncoderMethod = "getBitfieldInvertedMaskOpValue";
> let PrintMethod = "printBitfieldInvMaskImmOperand";
> + let DecoderMethod = "DecodeBitfieldMaskOperand";
> let ParserMatchClass = BitfieldAsmOperand;
> }
>
> @@ -599,6 +611,7 @@
>
> let EncoderMethod = "getAddrModeImm12OpValue";
> let PrintMethod = "printAddrModeImm12Operand";
> + let DecoderMethod = "DecodeAddrModeImm12Operand";
> let ParserMatchClass = MemImm12OffsetAsmOperand;
> let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
> }
> @@ -610,6 +623,7 @@
> let EncoderMethod = "getLdStSORegOpValue";
> // FIXME: Simplify the printer
> let PrintMethod = "printAddrMode2Operand";
> + let DecoderMethod = "DecodeSORegMemOperand";
> let ParserMatchClass = MemRegOffsetAsmOperand;
> let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$shift);
> }
> @@ -645,6 +659,7 @@
> }
> def postidx_reg : Operand<i32> {
> let EncoderMethod = "getPostIdxRegOpValue";
> + let DecoderMethod = "DecodePostIdxReg";
> let PrintMethod = "printPostIdxRegOperand";
> let ParserMatchClass = PostIdxRegAsmOperand;
> let MIOperandInfo = (ops GPR, i32imm);
> @@ -707,6 +722,7 @@
> ComplexPattern<i32, 2, "SelectAddrMode3Offset",
> [], [SDNPWantRoot]> {
> let EncoderMethod = "getAddrMode3OffsetOpValue";
> + let DecoderMethod = "DecodeAddrMode3Offset";
> let PrintMethod = "printAddrMode3OffsetOperand";
> let MIOperandInfo = (ops GPR, i32imm);
> }
> @@ -725,6 +741,7 @@
> ComplexPattern<i32, 2, "SelectAddrMode5", []> {
> let PrintMethod = "printAddrMode5Operand";
> let EncoderMethod = "getAddrMode5OpValue";
> + let DecoderMethod = "DecodeAddrMode5Operand";
> let ParserMatchClass = AddrMode5AsmOperand;
> let MIOperandInfo = (ops GPR:$base, i32imm);
> }
> @@ -736,6 +753,7 @@
> let PrintMethod = "printAddrMode6Operand";
> let MIOperandInfo = (ops GPR:$addr, i32imm);
> let EncoderMethod = "getAddrMode6AddressOpValue";
> + let DecoderMethod = "DecodeAddrMode6Operand";
> }
>
> def am6offset : Operand<i32>,
> @@ -744,6 +762,7 @@
> let PrintMethod = "printAddrMode6OffsetOperand";
> let MIOperandInfo = (ops GPR);
> let EncoderMethod = "getAddrMode6OffsetOpValue";
> + let DecoderMethod = "DecodeGPRRegisterClass";
> }
>
> // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
> @@ -778,6 +797,7 @@
> def addr_offset_none : Operand<i32>,
> ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
> let PrintMethod = "printAddrMode7Operand";
> + let DecoderMethod = "DecodeAddrMode7Operand";
> let ParserMatchClass = MemNoOffsetAsmOperand;
> let MIOperandInfo = (ops GPR:$base);
> }
> @@ -793,6 +813,7 @@
> def p_imm : Operand<i32> {
> let PrintMethod = "printPImmediate";
> let ParserMatchClass = CoprocNumAsmOperand;
> + let DecoderMethod = "DecodeCoprocessor";
> }
>
> def CoprocRegAsmOperand : AsmOperandClass {
> @@ -1654,6 +1675,7 @@
> [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
> bits<24> target;
> let Inst{23-0} = target;
> + let DecoderMethod = "DecodeBranchImmInstruction";
> }
>
> let isBarrier = 1 in {
> @@ -1917,6 +1939,7 @@
> let Inst{23} = addr{12};
> let Inst{19-16} = addr{17-14};
> let Inst{11-0} = addr{11-0};
> + let DecoderMethod = "DecodeAddrMode2IdxInstruction";
> let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
> }
>
> @@ -1933,6 +1956,8 @@
> let Inst{23} = offset{12};
> let Inst{19-16} = addr;
> let Inst{11-0} = offset{11-0};
> +
> + let DecoderMethod = "DecodeAddrMode2IdxInstruction";
> }
>
> def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
> @@ -1948,7 +1973,10 @@
> let Inst{23} = offset{12};
> let Inst{19-16} = addr;
> let Inst{11-0} = offset{11-0};
> +
> + let DecoderMethod = "DecodeAddrMode2IdxInstruction";
> }
> +
> }
>
> let mayLoad = 1, neverHasSideEffects = 1 in {
> @@ -2019,20 +2047,39 @@
>
> // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
> let mayLoad = 1, neverHasSideEffects = 1 in {
> -def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$base_wb),
> - (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_ru,
> +def LDRTr : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$base_wb),
> + (ins ldst_so_reg:$addr), IndexModePost, LdFrm, IIC_iLoad_ru,
> + "ldrt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
> + // {17-14} Rn
> + // {13} 1 == Rm, 0 == imm12
> + // {12} isAdd
> + // {11-0} imm12/Rm
> + bits<18> addr;
> + let Inst{25} = 1;
> + let Inst{23} = addr{12};
> + let Inst{21} = 1; // overwrite
> + let Inst{19-16} = addr{17-14};
> + let Inst{11-5} = addr{11-5};
> + let Inst{4} = 0;
> + let Inst{3-0} = addr{3-0};
> + let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
> + let DecoderMethod = "DecodeAddrMode2IdxInstruction";
> +}
> +def LDRTi : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$base_wb),
> + (ins addrmode_imm12:$addr), IndexModePost, LdFrm, IIC_iLoad_ru,
> "ldrt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
> // {17-14} Rn
> // {13} 1 == Rm, 0 == imm12
> // {12} isAdd
> // {11-0} imm12/Rm
> bits<18> addr;
> - let Inst{25} = addr{13};
> + let Inst{25} = 0;
> let Inst{23} = addr{12};
> let Inst{21} = 1; // overwrite
> let Inst{19-16} = addr{17-14};
> let Inst{11-0} = addr{11-0};
> let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
> + let DecoderMethod = "DecodeAddrMode2IdxInstruction";
> }
>
> def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
> @@ -2049,6 +2096,7 @@
> let Inst{21} = 1; // overwrite
> let Inst{19-16} = addr;
> let Inst{11-0} = offset{11-0};
> + let DecoderMethod = "DecodeAddrMode2IdxInstruction";
> }
>
> def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
> @@ -2065,6 +2113,7 @@
> let Inst{21} = 1; // overwrite
> let Inst{19-16} = addr;
> let Inst{11-0} = offset{11-0};
> + let DecoderMethod = "DecodeAddrMode2IdxInstruction";
> }
>
> multiclass AI3ldrT<bits<4> op, string opc> {
> @@ -2151,6 +2200,8 @@
> let Inst{23} = offset{12};
> let Inst{19-16} = addr;
> let Inst{11-0} = offset{11-0};
> +
> + let DecoderMethod = "DecodeAddrMode2IdxInstruction";
> }
>
> def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
> @@ -2166,6 +2217,8 @@
> let Inst{23} = offset{12};
> let Inst{19-16} = addr;
> let Inst{11-0} = offset{11-0};
> +
> + let DecoderMethod = "DecodeAddrMode2IdxInstruction";
> }
> }
>
> @@ -2287,6 +2340,7 @@
> let Inst{21} = 1; // overwrite
> let Inst{4} = 0;
> let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
> + let DecoderMethod = "DecodeAddrMode2IdxInstruction";
> }
>
> def STRTi : AI2stridxT<0, 0, (outs GPR:$Rn_wb),
> @@ -2297,6 +2351,7 @@
> let Inst{25} = 0;
> let Inst{21} = 1; // overwrite
> let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
> + let DecoderMethod = "DecodeAddrMode2IdxInstruction";
> }
>
>
> @@ -2309,6 +2364,7 @@
> let Inst{21} = 1; // overwrite
> let Inst{4} = 0;
> let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
> + let DecoderMethod = "DecodeAddrMode2IdxInstruction";
> }
>
> def STRBTi : AI2stridxT<1, 0, (outs GPR:$Rn_wb),
> @@ -2319,6 +2375,7 @@
> let Inst{25} = 0;
> let Inst{21} = 1; // overwrite
> let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
> + let DecoderMethod = "DecodeAddrMode2IdxInstruction";
> }
>
> multiclass AI3strT<bits<4> op, string opc> {
> @@ -2373,6 +2430,8 @@
> let Inst{24-23} = 0b01; // Increment After
> let Inst{21} = 1; // Writeback
> let Inst{20} = L_bit;
> +
> + let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
> }
> def DA :
> AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
> @@ -2389,6 +2448,8 @@
> let Inst{24-23} = 0b00; // Decrement After
> let Inst{21} = 1; // Writeback
> let Inst{20} = L_bit;
> +
> + let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
> }
> def DB :
> AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
> @@ -2405,6 +2466,8 @@
> let Inst{24-23} = 0b10; // Decrement Before
> let Inst{21} = 1; // Writeback
> let Inst{20} = L_bit;
> +
> + let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
> }
> def IB :
> AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
> @@ -2421,6 +2484,8 @@
> let Inst{24-23} = 0b11; // Increment Before
> let Inst{21} = 1; // Writeback
> let Inst{20} = L_bit;
> +
> + let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
> }
> }
>
> @@ -2504,8 +2569,6 @@
> let Inst{25} = 0;
> }
>
> -
> -
> let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
> def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
> "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
> @@ -3383,6 +3446,7 @@
>
>
> multiclass AI_smla<string opc, PatFrag opnode> {
> + let DecoderMethod = "DecodeSMLAInstruction" in {
> def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
> (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
> IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
> @@ -3425,6 +3489,7 @@
> [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
> (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
> Requires<[IsARM, HasV5TE]>;
> + }
> }
>
> defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
> @@ -3989,7 +4054,7 @@
> }
>
> multiclass LdStCop<bits<4> op31_28, bit load, dag ops, string opc, string cond>{
> -
> + let DecoderNamespace = "Common" in {
> def _OFFSET : ACI<(outs),
> !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
> !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr"> {
> @@ -3998,6 +4063,7 @@
> let Inst{21} = 0; // W = 0
> let Inst{22} = 0; // D = 0
> let Inst{20} = load;
> + let DecoderMethod = "DecodeCopMemInstruction";
> }
>
> def _PRE : ACI<(outs),
> @@ -4008,6 +4074,7 @@
> let Inst{21} = 1; // W = 1
> let Inst{22} = 0; // D = 0
> let Inst{20} = load;
> + let DecoderMethod = "DecodeCopMemInstruction";
> }
>
> def _POST : ACI<(outs),
> @@ -4018,6 +4085,7 @@
> let Inst{21} = 1; // W = 1
> let Inst{22} = 0; // D = 0
> let Inst{20} = load;
> + let DecoderMethod = "DecodeCopMemInstruction";
> }
>
> def _OPTION : ACI<(outs),
> @@ -4030,6 +4098,7 @@
> let Inst{21} = 0; // W = 0
> let Inst{22} = 0; // D = 0
> let Inst{20} = load;
> + let DecoderMethod = "DecodeCopMemInstruction";
> }
>
> def L_OFFSET : ACI<(outs),
> @@ -4040,6 +4109,7 @@
> let Inst{21} = 0; // W = 0
> let Inst{22} = 1; // D = 1
> let Inst{20} = load;
> + let DecoderMethod = "DecodeCopMemInstruction";
> }
>
> def L_PRE : ACI<(outs),
> @@ -4051,6 +4121,7 @@
> let Inst{21} = 1; // W = 1
> let Inst{22} = 1; // D = 1
> let Inst{20} = load;
> + let DecoderMethod = "DecodeCopMemInstruction";
> }
>
> def L_POST : ACI<(outs),
> @@ -4063,6 +4134,7 @@
> let Inst{21} = 1; // W = 1
> let Inst{22} = 1; // D = 1
> let Inst{20} = load;
> + let DecoderMethod = "DecodeCopMemInstruction";
> }
>
> def L_OPTION : ACI<(outs),
> @@ -4076,6 +4148,8 @@
> let Inst{21} = 0; // W = 0
> let Inst{22} = 1; // D = 1
> let Inst{20} = load;
> + let DecoderMethod = "DecodeCopMemInstruction";
> + }
> }
> }
>
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=137144&r1=137143&r2=137144&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Aug 9 15:55:18 2011
> @@ -191,6 +191,7 @@
> "vld1", Dt, "\\{$Vd\\}, $Rn", "", []> {
> let Rm = 0b1111;
> let Inst{4} = Rn{4};
> + let DecoderMethod = "DecodeVLDInstruction";
> }
> class VLD1Q<bits<4> op7_4, string Dt>
> : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2),
> @@ -198,6 +199,7 @@
> "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
> let Rm = 0b1111;
> let Inst{5-4} = Rn{5-4};
> + let DecoderMethod = "DecodeVLDInstruction";
> }
>
> def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
> @@ -222,6 +224,7 @@
> "vld1", Dt, "\\{$Vd\\}, $Rn$Rm",
> "$Rn.addr = $wb", []> {
> let Inst{4} = Rn{4};
> + let DecoderMethod = "DecodeVLDInstruction";
> }
> class VLD1QWB<bits<4> op7_4, string Dt>
> : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
> @@ -229,6 +232,7 @@
> "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
> "$Rn.addr = $wb", []> {
> let Inst{5-4} = Rn{5-4};
> + let DecoderMethod = "DecodeVLDInstruction";
> }
>
> def VLD1d8_UPD : VLD1DWB<{0,0,0,?}, "8">;
> @@ -253,12 +257,14 @@
> "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
> let Rm = 0b1111;
> let Inst{4} = Rn{4};
> + let DecoderMethod = "DecodeVLDInstruction";
> }
> class VLD1D3WB<bits<4> op7_4, string Dt>
> : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
> (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x3u, "vld1", Dt,
> "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
> let Inst{4} = Rn{4};
> + let DecoderMethod = "DecodeVLDInstruction";
> }
>
> def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
> @@ -281,6 +287,7 @@
> "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
> let Rm = 0b1111;
> let Inst{5-4} = Rn{5-4};
> + let DecoderMethod = "DecodeVLDInstruction";
> }
> class VLD1D4WB<bits<4> op7_4, string Dt>
> : NLdSt<0,0b10,0b0010,op7_4,
> @@ -289,6 +296,7 @@
> "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", "$Rn.addr = $wb",
> []> {
> let Inst{5-4} = Rn{5-4};
> + let DecoderMethod = "DecodeVLDInstruction";
> }
>
> def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
> @@ -311,6 +319,7 @@
> "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
> let Rm = 0b1111;
> let Inst{5-4} = Rn{5-4};
> + let DecoderMethod = "DecodeVLDInstruction";
> }
> class VLD2Q<bits<4> op7_4, string Dt>
> : NLdSt<0, 0b10, 0b0011, op7_4,
> @@ -319,6 +328,7 @@
> "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
> let Rm = 0b1111;
> let Inst{5-4} = Rn{5-4};
> + let DecoderMethod = "DecodeVLDInstruction";
> }
>
> def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8">;
> @@ -344,6 +354,7 @@
> "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
> "$Rn.addr = $wb", []> {
> let Inst{5-4} = Rn{5-4};
> + let DecoderMethod = "DecodeVLDInstruction";
> }
> class VLD2QWB<bits<4> op7_4, string Dt>
> : NLdSt<0, 0b10, 0b0011, op7_4,
> @@ -352,6 +363,7 @@
> "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
> "$Rn.addr = $wb", []> {
> let Inst{5-4} = Rn{5-4};
> + let DecoderMethod = "DecodeVLDInstruction";
> }
>
> def VLD2d8_UPD : VLD2DWB<0b1000, {0,0,?,?}, "8">;
> @@ -385,6 +397,7 @@
> "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
> let Rm = 0b1111;
> let Inst{4} = Rn{4};
> + let DecoderMethod = "DecodeVLDInstruction";
> }
>
> def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
> @@ -403,6 +416,7 @@
> "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
> "$Rn.addr = $wb", []> {
> let Inst{4} = Rn{4};
> + let DecoderMethod = "DecodeVLDInstruction";
> }
>
> def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
> @@ -442,6 +456,7 @@
> "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
> let Rm = 0b1111;
> let Inst{5-4} = Rn{5-4};
> + let DecoderMethod = "DecodeVLDInstruction";
> }
>
> def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
> @@ -460,6 +475,7 @@
> "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
> "$Rn.addr = $wb", []> {
> let Inst{5-4} = Rn{5-4};
> + let DecoderMethod = "DecodeVLDInstruction";
> }
>
> def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
> @@ -826,6 +842,7 @@
> [(set DPR:$Vd, (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
> let Rm = 0b1111;
> let Inst{4} = Rn{4};
> + let DecoderMethod = "DecodeVLD1DupInstruction";
> }
> class VLD1QDUPPseudo<ValueType Ty, PatFrag LoadOp> : VLDQPseudo<IIC_VLD1dup> {
> let Pattern = [(set QPR:$dst,
> @@ -853,6 +870,7 @@
> "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
> let Rm = 0b1111;
> let Inst{4} = Rn{4};
> + let DecoderMethod = "DecodeVLD1DupInstruction";
> }
>
> def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8">;
> @@ -865,12 +883,14 @@
> (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
> "vld1", Dt, "\\{$Vd[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
> let Inst{4} = Rn{4};
> + let DecoderMethod = "DecodeVLD1DupInstruction";
> }
> class VLD1QDUPWB<bits<4> op7_4, string Dt>
> : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
> (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
> "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
> let Inst{4} = Rn{4};
> + let DecoderMethod = "DecodeVLD1DupInstruction";
> }
>
> def VLD1DUPd8_UPD : VLD1DUPWB<{0,0,0,0}, "8">;
> @@ -892,6 +912,7 @@
> "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
> let Rm = 0b1111;
> let Inst{4} = Rn{4};
> + let DecoderMethod = "DecodeVLD2DupInstruction";
> }
>
> def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8">;
> @@ -913,6 +934,7 @@
> (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD2dupu,
> "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
> let Inst{4} = Rn{4};
> + let DecoderMethod = "DecodeVLD2DupInstruction";
> }
>
> def VLD2DUPd8_UPD : VLD2DUPWB<{0,0,0,0}, "8">;
> @@ -934,6 +956,7 @@
> "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
> let Rm = 0b1111;
> let Inst{4} = Rn{4};
> + let DecoderMethod = "DecodeVLD3DupInstruction";
> }
>
> def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
> @@ -956,6 +979,7 @@
> "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
> "$Rn.addr = $wb", []> {
> let Inst{4} = Rn{4};
> + let DecoderMethod = "DecodeVLD3DupInstruction";
> }
>
> def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
> @@ -978,6 +1002,7 @@
> "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
> let Rm = 0b1111;
> let Inst{4} = Rn{4};
> + let DecoderMethod = "DecodeVLD4DupInstruction";
> }
>
> def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
> @@ -1001,6 +1026,7 @@
> "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
> "$Rn.addr = $wb", []> {
> let Inst{4} = Rn{4};
> + let DecoderMethod = "DecodeVLD4DupInstruction";
> }
>
> def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
> @@ -1046,6 +1072,7 @@
> IIC_VST1, "vst1", Dt, "\\{$Vd\\}, $Rn", "", []> {
> let Rm = 0b1111;
> let Inst{4} = Rn{4};
> + let DecoderMethod = "DecodeVSTInstruction";
> }
> class VST1Q<bits<4> op7_4, string Dt>
> : NLdSt<0,0b00,0b1010,op7_4, (outs),
> @@ -1053,6 +1080,7 @@
> "vst1", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
> let Rm = 0b1111;
> let Inst{5-4} = Rn{5-4};
> + let DecoderMethod = "DecodeVSTInstruction";
> }
>
> def VST1d8 : VST1D<{0,0,0,?}, "8">;
> @@ -1076,6 +1104,7 @@
> (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd), IIC_VST1u,
> "vst1", Dt, "\\{$Vd\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
> let Inst{4} = Rn{4};
> + let DecoderMethod = "DecodeVSTInstruction";
> }
> class VST1QWB<bits<4> op7_4, string Dt>
> : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
> @@ -1083,6 +1112,7 @@
> IIC_VST1x2u, "vst1", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
> "$Rn.addr = $wb", []> {
> let Inst{5-4} = Rn{5-4};
> + let DecoderMethod = "DecodeVSTInstruction";
> }
>
> def VST1d8_UPD : VST1DWB<{0,0,0,?}, "8">;
> @@ -1107,6 +1137,7 @@
> IIC_VST1x3, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
> let Rm = 0b1111;
> let Inst{4} = Rn{4};
> + let DecoderMethod = "DecodeVSTInstruction";
> }
> class VST1D3WB<bits<4> op7_4, string Dt>
> : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
> @@ -1115,6 +1146,7 @@
> IIC_VST1x3u, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
> "$Rn.addr = $wb", []> {
> let Inst{4} = Rn{4};
> + let DecoderMethod = "DecodeVSTInstruction";
> }
>
> def VST1d8T : VST1D3<{0,0,0,?}, "8">;
> @@ -1138,6 +1170,7 @@
> []> {
> let Rm = 0b1111;
> let Inst{5-4} = Rn{5-4};
> + let DecoderMethod = "DecodeVSTInstruction";
> }
> class VST1D4WB<bits<4> op7_4, string Dt>
> : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
> @@ -1146,6 +1179,7 @@
> "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
> "$Rn.addr = $wb", []> {
> let Inst{5-4} = Rn{5-4};
> + let DecoderMethod = "DecodeVSTInstruction";
> }
>
> def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
> @@ -1168,6 +1202,7 @@
> IIC_VST2, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
> let Rm = 0b1111;
> let Inst{5-4} = Rn{5-4};
> + let DecoderMethod = "DecodeVSTInstruction";
> }
> class VST2Q<bits<4> op7_4, string Dt>
> : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
> @@ -1176,6 +1211,7 @@
> "", []> {
> let Rm = 0b1111;
> let Inst{5-4} = Rn{5-4};
> + let DecoderMethod = "DecodeVSTInstruction";
> }
>
> def VST2d8 : VST2D<0b1000, {0,0,?,?}, "8">;
> @@ -1201,6 +1237,7 @@
> IIC_VST2u, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
> "$Rn.addr = $wb", []> {
> let Inst{5-4} = Rn{5-4};
> + let DecoderMethod = "DecodeVSTInstruction";
> }
> class VST2QWB<bits<4> op7_4, string Dt>
> : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
> @@ -1209,6 +1246,7 @@
> "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
> "$Rn.addr = $wb", []> {
> let Inst{5-4} = Rn{5-4};
> + let DecoderMethod = "DecodeVSTInstruction";
> }
>
> def VST2d8_UPD : VST2DWB<0b1000, {0,0,?,?}, "8">;
> @@ -1242,6 +1280,7 @@
> "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
> let Rm = 0b1111;
> let Inst{4} = Rn{4};
> + let DecoderMethod = "DecodeVSTInstruction";
> }
>
> def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
> @@ -1260,6 +1299,7 @@
> "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
> "$Rn.addr = $wb", []> {
> let Inst{4} = Rn{4};
> + let DecoderMethod = "DecodeVSTInstruction";
> }
>
> def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
> @@ -1299,6 +1339,7 @@
> "", []> {
> let Rm = 0b1111;
> let Inst{5-4} = Rn{5-4};
> + let DecoderMethod = "DecodeVSTInstruction";
> }
>
> def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
> @@ -1317,6 +1358,7 @@
> "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
> "$Rn.addr = $wb", []> {
> let Inst{5-4} = Rn{5-4};
> + let DecoderMethod = "DecodeVSTInstruction";
> }
>
> def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
> @@ -4040,6 +4082,7 @@
> : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
> ResTy, OpTy, OpNode> {
> let Inst{21-16} = op21_16;
> + let DecoderMethod = "DecodeVSHLMaxInstruction";
> }
> def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
> v8i16, v8i8, NEONvshlli>;
> @@ -4754,6 +4797,7 @@
> // Vector Table Lookup and Table Extension.
>
> // VTBL : Vector Table Lookup
> +let DecoderMethod = "DecodeTBLInstruction" in {
> def VTBL1
> : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
> (ins DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
> @@ -4816,6 +4860,7 @@
> def VTBX4Pseudo
> : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
> IIC_VTBX4, "$orig = $dst", []>;
> +} // DecoderMethod = "DecodeTBLInstruction"
>
> //===----------------------------------------------------------------------===//
> // NEON instructions for single-precision FP math
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=137144&r1=137143&r2=137144&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Tue Aug 9 15:55:18 2011
> @@ -82,14 +82,17 @@
> let OperandType = "OPERAND_PCREL" in {
> def t_brtarget : Operand<OtherVT> {
> let EncoderMethod = "getThumbBRTargetOpValue";
> + let DecoderMethod = "DecodeThumbBROperand";
> }
>
> def t_bcctarget : Operand<i32> {
> let EncoderMethod = "getThumbBCCTargetOpValue";
> + let DecoderMethod = "DecodeThumbBCCTargetOperand";
> }
>
> def t_cbtarget : Operand<i32> {
> let EncoderMethod = "getThumbCBTargetOpValue";
> + let DecoderMethod = "DecodeThumbCmpBROperand";
> }
>
> def t_bltarget : Operand<i32> {
> @@ -119,12 +122,14 @@
> ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
> let EncoderMethod = "getThumbAddrModeRegRegOpValue";
> let PrintMethod = "printThumbAddrModeRROperand";
> + let DecoderMethod = "DecodeThumbAddrModeRR";
> let ParserMatchClass = t_addrmode_rr_asm_operand;
> let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
> }
> def t_addrmode_rrs2 : Operand<i32>,
> ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
> let EncoderMethod = "getThumbAddrModeRegRegOpValue";
> + let DecoderMethod = "DecodeThumbAddrModeRR";
> let PrintMethod = "printThumbAddrModeRROperand";
> let ParserMatchClass = t_addrmode_rr_asm_operand;
> let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
> @@ -132,6 +137,7 @@
> def t_addrmode_rrs4 : Operand<i32>,
> ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
> let EncoderMethod = "getThumbAddrModeRegRegOpValue";
> + let DecoderMethod = "DecodeThumbAddrModeRR";
> let PrintMethod = "printThumbAddrModeRROperand";
> let ParserMatchClass = t_addrmode_rr_asm_operand;
> let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
> @@ -142,6 +148,7 @@
> def t_addrmode_is4 : Operand<i32>,
> ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
> let EncoderMethod = "getAddrModeISOpValue";
> + let DecoderMethod = "DecodeThumbAddrModeIS";
> let PrintMethod = "printThumbAddrModeImm5S4Operand";
> let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
> }
> @@ -151,6 +158,7 @@
> def t_addrmode_is2 : Operand<i32>,
> ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
> let EncoderMethod = "getAddrModeISOpValue";
> + let DecoderMethod = "DecodeThumbAddrModeIS";
> let PrintMethod = "printThumbAddrModeImm5S2Operand";
> let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
> }
> @@ -160,6 +168,7 @@
> def t_addrmode_is1 : Operand<i32>,
> ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
> let EncoderMethod = "getAddrModeISOpValue";
> + let DecoderMethod = "DecodeThumbAddrModeIS";
> let PrintMethod = "printThumbAddrModeImm5S1Operand";
> let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
> }
> @@ -178,6 +187,7 @@
> //
> def t_addrmode_pc : Operand<i32> {
> let EncoderMethod = "getAddrModePCOpValue";
> + let DecoderMethod = "DecodeThumbAddrModePC";
> }
>
> //===----------------------------------------------------------------------===//
> @@ -259,6 +269,7 @@
> let Inst{4} = imod;
> let Inst{3} = 0;
> let Inst{2-0} = iflags;
> + let DecoderMethod = "DecodeThumbCPS";
> }
>
> // For both thumb1 and thumb2.
> @@ -272,17 +283,6 @@
> let Inst{2-0} = dst;
> }
>
> -// PC relative add (ADR).
> -def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
> - "add\t$dst, pc, $rhs", []>,
> - T1Encoding<{1,0,1,0,0,?}> {
> - // A6.2& A8.6.10
> - bits<3> dst;
> - bits<8> rhs;
> - let Inst{10-8} = dst;
> - let Inst{7-0} = rhs;
> -}
> -
What replaced this?
> // ADD<Rd>, sp, #<imm8>
> // This is rematerializable, which is particularly useful for taking the
> // address of locals.
> @@ -295,6 +295,7 @@
> bits<8> rhs;
> let Inst{10-8} = dst;
> let Inst{7-0} = rhs;
> + let DecoderMethod = "DecodeThumbAddSpecialReg";
> }
>
> // ADD sp, sp, #<imm7>
> @@ -304,6 +305,7 @@
> // A6.2.5& A8.6.8
> bits<7> rhs;
> let Inst{6-0} = rhs;
> + let DecoderMethod = "DecodeThumbAddSPImm";
> }
>
> // SUB sp, sp, #<imm7>
> @@ -314,6 +316,7 @@
> // A6.2.5& A8.6.214
> bits<7> rhs;
> let Inst{6-0} = rhs;
> + let DecoderMethod = "DecodeThumbAddSPImm";
> }
>
> // ADD<Rm>, sp
> @@ -325,6 +328,7 @@
> let Inst{7} = dst{3};
> let Inst{6-3} = 0b1101;
> let Inst{2-0} = dst{2-0};
> + let DecoderMethod = "DecodeThumbAddSPReg";
> }
>
> // ADD sp,<Rm>
> @@ -336,6 +340,7 @@
> let Inst{7} = 1;
> let Inst{6-3} = dst;
> let Inst{2-0} = 0b101;
> + let DecoderMethod = "DecodeThumbAddSPReg";
> }
>
> //===----------------------------------------------------------------------===//
> @@ -1189,6 +1194,7 @@
> bits<8> addr;
> let Inst{10-8} = Rd;
> let Inst{7-0} = addr;
> + let DecoderMethod = "DecodeThumbAddSpecialReg";
> }
>
> let neverHasSideEffects = 1, isReMaterializable = 1 in
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=137144&r1=137143&r2=137144&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Aug 9 15:55:18 2011
> @@ -50,6 +50,7 @@
> }]> {
> let ParserMatchClass = t2_so_imm_asmoperand;
> let EncoderMethod = "getT2SOImmOpValue";
> + let DecoderMethod = "DecodeT2SOImm";
> }
>
> // t2_so_imm_not - Match an immediate that is a complement
> @@ -100,6 +101,7 @@
> ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
> let PrintMethod = "printAddrModeImm12Operand";
> let EncoderMethod = "getAddrModeImm12OpValue";
> + let DecoderMethod = "DecodeT2AddrModeImm12";
> let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
> }
>
> @@ -121,6 +123,7 @@
> ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
> let PrintMethod = "printT2AddrModeImm8Operand";
> let EncoderMethod = "getT2AddrModeImm8OpValue";
> + let DecoderMethod = "DecodeT2AddrModeImm8";
> let ParserMatchClass = MemImm8OffsetAsmOperand;
> let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
> }
> @@ -130,12 +133,14 @@
> [], [SDNPWantRoot]> {
> let PrintMethod = "printT2AddrModeImm8OffsetOperand";
> let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
> + let DecoderMethod = "DecodeT2Imm8";
> }
>
> // t2addrmode_imm8s4 := reg +/- (imm8<< 2)
> def t2addrmode_imm8s4 : Operand<i32> {
> let PrintMethod = "printT2AddrModeImm8s4Operand";
> let EncoderMethod = "getT2AddrModeImm8s4OpValue";
> + let DecoderMethod = "DecodeT2AddrModeImm8s4";
> let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
> }
>
> @@ -149,6 +154,7 @@
> ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
> let PrintMethod = "printT2AddrModeSoRegOperand";
> let EncoderMethod = "getT2AddrModeSORegOpValue";
> + let DecoderMethod = "DecodeT2AddrModeSOReg";
> let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
> }
>
> @@ -158,6 +164,7 @@
> //
> def t2addrmode_reg : Operand<i32> {
> let PrintMethod = "printAddrMode7Operand";
> + let DecoderMethod = "DecodeGPRRegisterClass";
> let MIOperandInfo = (ops GPR);
> }
>
> @@ -892,6 +899,8 @@
> let Inst{19-16} = addr{9-6}; // Rn
> let Inst{3-0} = addr{5-2}; // Rm
> let Inst{5-4} = addr{1-0}; // imm
> +
> + let DecoderMethod = "DecodeT2LoadShift";
> }
>
> // FIXME: Is the pci variant actually needed?
> @@ -1430,6 +1439,8 @@
> let Inst{19-16} = addr{9-6}; // Rn
> let Inst{3-0} = addr{5-2}; // Rm
> let Inst{5-4} = addr{1-0}; // imm2
> +
> + let DecoderMethod = "DecodeT2LoadShift";
> }
> }
>
> @@ -2994,6 +3005,8 @@
> let Inst{13} = target{18};
> let Inst{21-16} = target{17-12};
> let Inst{10-0} = target{11-1};
> +
> + let DecoderMethod = "DecodeThumb2BCCInstruction";
> }
>
> // Tail calls. The Darwin version of thumb tail calls uses a t2 branch, so
>
> Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=137144&r1=137143&r2=137144&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Tue Aug 9 15:55:18 2011
> @@ -6,584 +6,2328 @@
> // License. See LICENSE.TXT for details.
> //
> //===----------------------------------------------------------------------===//
> -//
> -// This file is part of the ARM Disassembler.
> -// It contains code to implement the public interfaces of ARMDisassembler and
> -// ThumbDisassembler, both of which are instances of MCDisassembler.
> -//
> -//===----------------------------------------------------------------------===//
>
> #define DEBUG_TYPE "arm-disassembler"
>
> #include "ARMDisassembler.h"
> -#include "ARMDisassemblerCore.h"
> -
> -#include "llvm/ADT/OwningPtr.h"
> +#include "ARM.h"
> +#include "ARMRegisterInfo.h"
> +#include "MCTargetDesc/ARMAddressingModes.h"
> +#include "MCTargetDesc/ARMBaseInfo.h"
> #include "llvm/MC/EDInstInfo.h"
> #include "llvm/MC/MCInst.h"
> +#include "llvm/MC/MCExpr.h"
> +#include "llvm/MC/MCContext.h"
> #include "llvm/Target/TargetRegistry.h"
> #include "llvm/Support/Debug.h"
> #include "llvm/Support/MemoryObject.h"
> #include "llvm/Support/ErrorHandling.h"
> #include "llvm/Support/raw_ostream.h"
>
> -//#define DEBUG(X) do { X; } while (0)
> -
> -/// ARMGenDecoderTables.inc - ARMDecoderTables.inc is tblgen'ed from
> -/// ARMDecoderEmitter.cpp TableGen backend. It contains:
> -///
> -/// o Mappings from opcode to ARM/Thumb instruction format
> -///
> -/// o static uint16_t decodeInstruction(uint32_t insn) - the decoding function
> -/// for an ARM instruction.
> -///
> -/// o static uint16_t decodeThumbInstruction(field_t insn) - the decoding
> -/// function for a Thumb instruction.
> -///
> -#include "ARMGenDecoderTables.inc"
> +// Forward declare these because the autogenerated code will reference them.
> +// Definitions are further down.
> +static bool DecodeGPRRegisterClass(llvm::MCInst&Inst, unsigned RegNo,
> + uint64_t Address, const void *Decoder);
> +static bool DecodetGPRRegisterClass(llvm::MCInst&Inst, unsigned RegNo,
> + uint64_t Address, const void *Decoder);
> +static bool DecodetcGPRRegisterClass(llvm::MCInst&Inst, unsigned RegNo,
> + uint64_t Address, const void *Decoder);
> +static bool DecoderGPRRegisterClass(llvm::MCInst&Inst, unsigned RegNo,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeSPRRegisterClass(llvm::MCInst&Inst, unsigned RegNo,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeDPRRegisterClass(llvm::MCInst&Inst, unsigned RegNo,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeDPR_8RegisterClass(llvm::MCInst&Inst, unsigned RegNo,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst&Inst, unsigned RegNo,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeQPRRegisterClass(llvm::MCInst&Inst, unsigned RegNo,
> + uint64_t Address, const void *Decoder);
> +
> +static bool DecodePredicateOperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeCCOutOperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeSOImmOperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeBLTargetOperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeRegListOperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeSPRRegListOperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeDPRRegListOperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +
> +static bool DecodeBitfieldMaskOperand(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeCopMemInstruction(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeAddrMode2IdxInstruction(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeSORegMemOperand(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeAddrMode3Instruction(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeSORegImmOperand(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeSORegRegOperand(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder);
> +
> +static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst& Inst,
> + unsigned Insn,
> + uint64_t Adddress,
> + const void *Decoder);
> +static bool DecodeSMLAInstruction(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeAddrModeImm12Operand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeAddrMode5Operand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeAddrMode7Operand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeBranchImmInstruction(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeVCVTImmOperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeAddrMode6Operand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeVLDInstruction(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeVSTInstruction(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeVLD1DupInstruction(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeVLD2DupInstruction(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeVLD3DupInstruction(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeVLD4DupInstruction(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeNEONModImmInstruction(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeVSHLMaxInstruction(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeShiftRight8Imm(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeShiftRight16Imm(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeShiftRight32Imm(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeShiftRight64Imm(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeTBLInstruction(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeVFPfpImm(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodePostIdxReg(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeCoprocessor(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeAddrMode3Offset(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder);
> +
> +
> +static bool DecodeThumbAddSpecialReg(llvm::MCInst&Inst, uint16_t Insn,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeThumbBROperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeT2BROperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeThumbCmpBROperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeThumbAddrModeRR(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeThumbAddrModeIS(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeThumbAddrModePC(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeThumbAddrModeSP(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeT2AddrModeSOReg(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeT2LoadShift(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeT2Imm8S4(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeT2AddrModeImm8s4(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeT2Imm8(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeT2AddrModeImm8(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeThumbAddSPImm(llvm::MCInst&Inst, uint16_t Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeThumbAddSPReg(llvm::MCInst&Inst, uint16_t Insn,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeThumbCPS(llvm::MCInst&Inst, uint16_t Insn,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeThumbBLXOffset(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeT2AddrModeImm12(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeThumbSRImm(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeThumb2BCCInstruction(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeT2SOImm(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeThumbBCCTargetOperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
> +static bool DecodeThumbBLTargetOperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder);
>
> +#include "ARMGenDisassemblerTables.inc"
> +#include "ARMGenInstrInfo.inc"
> #include "ARMGenEDInfo.inc"
>
> using namespace llvm;
>
> -/// showBitVector - Use the raw_ostream to log a diagnostic message describing
> -/// the inidividual bits of the instruction.
> -///
> -static inline void showBitVector(raw_ostream&os, const uint32_t&insn) {
> - // Split the bit position markers into more than one lines to fit 80 columns.
> - os<< " 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11"
> -<< " 10 9 8 7 6 5 4 3 2 1 0 \n";
> - os<< "---------------------------------------------------------------"
> -<< "----------------------------------\n";
> - os<< '|';
> - for (unsigned i = 32; i != 0; --i) {
> - if (insn>> (i - 1)& 0x01)
> - os<< " 1";
> - else
> - os<< " 0";
> - os<< (i%4 == 1 ? '|' : ':');
> +static MCDisassembler *createARMDisassembler(const Target&T) {
> + return new ARMDisassembler;
> +}
> +
> +static MCDisassembler *createThumbDisassembler(const Target&T) {
> + return new ThumbDisassembler;
> +}
> +
> +EDInstInfo *ARMDisassembler::getEDInfo() const {
> + return instInfoARM;
> +}
> +
> +EDInstInfo *ThumbDisassembler::getEDInfo() const {
> + return instInfoARM;
> +}
> +
> +
> +bool ARMDisassembler::getInstruction(MCInst&MI, uint64_t&Size,
> + const MemoryObject&Region,
> + uint64_t Address,raw_ostream&os) const {
> + uint8_t bytes[4];
> +
> + // We want to read exactly 4 bytes of data.
> + if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1)
> + return false;
> +
> + // Encoded as a small-endian 32-bit word in the stream.
> + uint32_t insn = (bytes[3]<< 24) |
> + (bytes[2]<< 16) |
> + (bytes[1]<< 8) |
> + (bytes[0]<< 0);
> +
> + // Calling the auto-generated decoder function.
> + bool result = decodeARMInstruction32(MI, insn, Address, this);
> + if (result) {
> + Size = 4;
> + return true;
> }
> - os<< '\n';
> - // Split the bit position markers into more than one lines to fit 80 columns.
> - os<< "---------------------------------------------------------------"
> -<< "----------------------------------\n";
> - os<< '\n';
> -}
> -
> -/// decodeARMInstruction is a decorator function which tries special cases of
> -/// instruction matching before calling the auto-generated decoder function.
> -static unsigned decodeARMInstruction(uint32_t&insn) {
> - if (slice(insn, 31, 28) == 15)
> - goto AutoGenedDecoder;
> -
> - // Special case processing, if any, goes here....
> -
> - // LLVM combines the offset mode of A8.6.197& A8.6.198 into STRB.
> - // The insufficient encoding information of the combined instruction confuses
> - // the decoder wrt BFC/BFI. Therefore, we try to recover here.
> - // For BFC, Inst{27-21} = 0b0111110& Inst{6-0} = 0b0011111.
> - // For BFI, Inst{27-21} = 0b0111110& Inst{6-4} = 0b001& Inst{3-0} =! 0b1111.
> - if (slice(insn, 27, 21) == 0x3e&& slice(insn, 6, 4) == 1) {
> - if (slice(insn, 3, 0) == 15)
> - return ARM::BFC;
> - else
> - return ARM::BFI;
> +
> + // Instructions that are shared between ARM and Thumb modes.
> + // FIXME: This shouldn't really exist. It's an artifact of the
> + // fact that we fail to encode a few instructions properly for Thumb.
> + MI.clear();
> + result = decodeCommonInstruction32(MI, insn, Address, this);
> + if (result) {
> + Size = 4;
> + return true;
> }
>
> - // Ditto for STRBT, which is a super-instruction for A8.6.199 Encodings
> - // A1& A2.
> - // As a result, the decoder fails to deocode USAT properly.
> - if (slice(insn, 27, 21) == 0x37&& slice(insn, 5, 4) == 1)
> - return ARM::USAT;
> - // As a result, the decoder fails to deocode UQADD16 properly.
> - if (slice(insn, 27, 20) == 0x66&& slice(insn, 7, 4) == 1)
> - return ARM::UQADD16;
> -
> - // Ditto for ADDSrs, which is a super-instruction for A8.6.7& A8.6.8.
> - // As a result, the decoder fails to decode UMULL properly.
> - if (slice(insn, 27, 21) == 0x04&& slice(insn, 7, 4) == 9) {
> - return ARM::UMULL;
> - }
> -
> - // Ditto for STR_PRE, which is a super-instruction for A8.6.194& A8.6.195.
> - // As a result, the decoder fails to decode SBFX properly.
> - if (slice(insn, 27, 21) == 0x3d&& slice(insn, 6, 4) == 5)
> - return ARM::SBFX;
> -
> - // And STRB_PRE, which is a super-instruction for A8.6.197& A8.6.198.
> - // As a result, the decoder fails to decode UBFX properly.
> - if (slice(insn, 27, 21) == 0x3f&& slice(insn, 6, 4) == 5)
> - return ARM::UBFX;
> -
> - // Ditto for STRT, which is a super-instruction for A8.6.210 Encoding A1& A2.
> - // As a result, the decoder fails to deocode SSAT properly.
> - if (slice(insn, 27, 21) == 0x35&& slice(insn, 5, 4) == 1)
> - return ARM::SSAT;
> -
> - // Ditto for RSCrs, which is a super-instruction for A8.6.146& A8.6.147.
> - // As a result, the decoder fails to decode STRHT/LDRHT/LDRSHT/LDRSBT.
> - if (slice(insn, 27, 24) == 0) {
> - switch (slice(insn, 21, 20)) {
> - case 2:
> - switch (slice(insn, 7, 4)) {
> - case 11:
> - return slice(insn, 22, 22) ? ARM::STRHTi : ARM::STRHTr;
> - default:
> - break; // fallthrough
> - }
> - break;
> - case 3:
> - switch (slice(insn, 7, 4)) {
> - case 11:
> - return slice(insn, 22, 22) ? ARM::LDRHTi : ARM::LDRHTr;
> - case 13:
> - return slice(insn, 22, 22) ? ARM::LDRSBTi : ARM::LDRSBTr;
> - case 15:
> - return slice(insn, 22, 22) ? ARM::LDRSHTi : ARM::LDRSHTr;
> - default:
> - break; // fallthrough
> - }
> - break;
> - default:
> - break; // fallthrough
> - }
> + // VFP and NEON instructions, similarly, are shared between ARM
> + // and Thumb modes.
> + MI.clear();
> + result = decodeVFPInstruction32(MI, insn, Address, this);
> + if (result) {
> + Size = 4;
> + return true;
> }
>
> - // Ditto for SBCrs, which is a super-instruction for A8.6.152& A8.6.153.
> - // As a result, the decoder fails to decode STRH_Post/LDRD_POST/STRD_POST
> - // properly.
> - if (slice(insn, 27, 25) == 0&& slice(insn, 20, 20) == 0) {
> - unsigned PW = slice(insn, 24, 24)<< 1 | slice(insn, 21, 21);
> - switch (slice(insn, 7, 4)) {
> - case 11:
> - switch (PW) {
> - case 2: // Offset
> - return ARM::STRH;
> - case 3: // Pre-indexed
> - return ARM::STRH_PRE;
> - case 0: // Post-indexed
> - return ARM::STRH_POST;
> - default:
> - break; // fallthrough
> - }
> - break;
> - case 13:
> - switch (PW) {
> - case 2: // Offset
> - return ARM::LDRD;
> - case 3: // Pre-indexed
> - return ARM::LDRD_PRE;
> - case 0: // Post-indexed
> - return ARM::LDRD_POST;
> - default:
> - break; // fallthrough
> - }
> - break;
> - case 15:
> - switch (PW) {
> - case 2: // Offset
> - return ARM::STRD;
> - case 3: // Pre-indexed
> - return ARM::STRD_PRE;
> - case 0: // Post-indexed
> - return ARM::STRD_POST;
> - default:
> - break; // fallthrough
> - }
> - break;
> - default:
> - break; // fallthrough
> - }
> + MI.clear();
> + result = decodeNEONInstruction32(MI, insn, Address, this);
> + if (result) {
> + // Add a fake predicate operand, because we share these instruction
> + // definitions with Thumb2 where these instructions are predicable.
> + if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false;
> + Size = 4;
> + return true;
> }
>
> - // Ditto for SBCSSrs, which is a super-instruction for A8.6.152& A8.6.153.
> - // As a result, the decoder fails to decode LDRH_POST/LDRSB_POST/LDRSH_POST
> - // properly.
> - if (slice(insn, 27, 25) == 0&& slice(insn, 20, 20) == 1) {
> - unsigned PW = slice(insn, 24, 24)<< 1 | slice(insn, 21, 21);
> - switch (slice(insn, 7, 4)) {
> - case 11:
> - switch (PW) {
> - case 2: // Offset
> - return ARM::LDRH;
> - case 3: // Pre-indexed
> - return ARM::LDRH_PRE;
> - case 0: // Post-indexed
> - return ARM::LDRH_POST;
> - default:
> - break; // fallthrough
> - }
> - break;
> - case 13:
> - switch (PW) {
> - case 2: // Offset
> - return ARM::LDRSB;
> - case 3: // Pre-indexed
> - return ARM::LDRSB_PRE;
> - case 0: // Post-indexed
> - return ARM::LDRSB_POST;
> - default:
> - break; // fallthrough
> - }
> - break;
> - case 15:
> - switch (PW) {
> - case 2: // Offset
> - return ARM::LDRSH;
> - case 3: // Pre-indexed
> - return ARM::LDRSH_PRE;
> - case 0: // Post-indexed
> - return ARM::LDRSH_POST;
> - default:
> - break; // fallthrough
> - }
> - break;
> - default:
> - break; // fallthrough
> + MI.clear();
> +
> + return false;
> +}
> +
> +namespace llvm {
> +extern MCInstrDesc ARMInsts[];
> +}
> +
> +// Thumb1 instructions don't have explicit S bits. Rather, they
> +// implicitly set CPSR. Since it's not represented in the encoding, the
> +// auto-generated decoder won't inject the CPSR operand. We need to fix
> +// that as a post-pass.
> +static void AddThumb1SBit(MCInst&MI, bool InITBlock) {
> + const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
> + MCInst::iterator I = MI.begin();
> + for (unsigned i = 0; i< MI.size(); ++i, ++I) {
> + if (OpInfo[i].isOptionalDef()&& OpInfo[i].RegClass == ARM::CCRRegClassID) {
> + MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
> + return;
Please don't re-test MI.size() each loop iteration.
> }
> }
>
> -AutoGenedDecoder:
> - // Calling the auto-generated decoder function.
> - return decodeInstruction(insn);
> + if (OpInfo[MI.size()].isOptionalDef()&&
> + OpInfo[MI.size()].RegClass == ARM::CCRRegClassID)
> + MI.insert(MI.end(), MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
> }
>
> -// Helper function for special case handling of LDR (literal) and friends.
> -// See, for example, A6.3.7 Load word: Table A6-18 Load word.
> -// See A8.6.57 T3, T4& A8.6.60 T2 and friends for why we morphed the opcode
> -// before returning it.
> -static unsigned T2Morph2LoadLiteral(unsigned Opcode) {
> - switch (Opcode) {
> - default:
> - return Opcode; // Return unmorphed opcode.
> -
> - case ARM::t2LDR_POST: case ARM::t2LDR_PRE:
> - case ARM::t2LDRi12: case ARM::t2LDRi8:
> - case ARM::t2LDRs: case ARM::t2LDRT:
> - return ARM::t2LDRpci;
> -
> - case ARM::t2LDRB_POST: case ARM::t2LDRB_PRE:
> - case ARM::t2LDRBi12: case ARM::t2LDRBi8:
> - case ARM::t2LDRBs: case ARM::t2LDRBT:
> - return ARM::t2LDRBpci;
> -
> - case ARM::t2LDRH_POST: case ARM::t2LDRH_PRE:
> - case ARM::t2LDRHi12: case ARM::t2LDRHi8:
> - case ARM::t2LDRHs: case ARM::t2LDRHT:
> - return ARM::t2LDRHpci;
> -
> - case ARM::t2LDRSB_POST: case ARM::t2LDRSB_PRE:
> - case ARM::t2LDRSBi12: case ARM::t2LDRSBi8:
> - case ARM::t2LDRSBs: case ARM::t2LDRSBT:
> - return ARM::t2LDRSBpci;
> -
> - case ARM::t2LDRSH_POST: case ARM::t2LDRSH_PRE:
> - case ARM::t2LDRSHi12: case ARM::t2LDRSHi8:
> - case ARM::t2LDRSHs: case ARM::t2LDRSHT:
> - return ARM::t2LDRSHpci;
> - }
> -}
> -
> -// Helper function for special case handling of PLD (literal) and friends.
> -// See A8.6.117 T1& T2 and friends for why we morphed the opcode
> -// before returning it.
> -static unsigned T2Morph2PLDLiteral(unsigned Opcode) {
> - switch (Opcode) {
> - default:
> - return Opcode; // Return unmorphed opcode.
> -
> - case ARM::t2PLDi8: case ARM::t2PLDs:
> - case ARM::t2PLDWi12: case ARM::t2PLDWi8:
> - case ARM::t2PLDWs:
> - return ARM::t2PLDi12;
> -
> - case ARM::t2PLIi8: case ARM::t2PLIs:
> - return ARM::t2PLIi12;
> - }
> -}
> -
> -/// decodeThumbSideEffect is a decorator function which can potentially twiddle
> -/// the instruction or morph the returned opcode under Thumb2.
> -///
> -/// First it checks whether the insn is a NEON or VFP instr; if true, bit
> -/// twiddling could be performed on insn to turn it into an ARM NEON/VFP
> -/// equivalent instruction and decodeInstruction is called with the transformed
> -/// insn.
> -///
> -/// Next, there is special handling for Load byte/halfword/word instruction by
> -/// checking whether Rn=0b1111 and call T2Morph2LoadLiteral() on the decoded
> -/// Thumb2 instruction. See comments below for further details.
> -///
> -/// Finally, one last check is made to see whether the insn is a NEON/VFP and
> -/// decodeInstruction(insn) is invoked on the original insn.
> -///
> -/// Otherwise, decodeThumbInstruction is called with the original insn.
> -static unsigned decodeThumbSideEffect(bool IsThumb2, unsigned&insn) {
> - if (IsThumb2) {
> - uint16_t op1 = slice(insn, 28, 27);
> - uint16_t op2 = slice(insn, 26, 20);
> -
> - // A6.3 32-bit Thumb instruction encoding
> - // Table A6-9 32-bit Thumb instruction encoding
> -
> - // The coprocessor instructions of interest are transformed to their ARM
> - // equivalents.
> -
> - // --------- Transform Begin Marker ---------
> - if ((op1 == 1 || op1 == 3)&& slice(op2, 6, 4) == 7) {
> - // A7.4 Advanced SIMD data-processing instructions
> - // U bit of Thumb corresponds to Inst{24} of ARM.
> - uint16_t U = slice(op1, 1, 1);
> -
> - // Inst{28-24} of ARM = {1,0,0,1,U};
> - uint16_t bits28_24 = 9<< 1 | U;
> - DEBUG(showBitVector(errs(), insn));
> - setSlice(insn, 28, 24, bits28_24);
> - return decodeInstruction(insn);
> - }
> -
> - if (op1 == 3&& slice(op2, 6, 4) == 1&& slice(op2, 0, 0) == 0) {
> - // A7.7 Advanced SIMD element or structure load/store instructions
> - // Inst{27-24} of Thumb = 0b1001
> - // Inst{27-24} of ARM = 0b0100
> - DEBUG(showBitVector(errs(), insn));
> - setSlice(insn, 27, 24, 4);
> - return decodeInstruction(insn);
> - }
> - // --------- Transform End Marker ---------
> -
> - unsigned unmorphed = decodeThumbInstruction(insn);
> -
> - // See, for example, A6.3.7 Load word: Table A6-18 Load word.
> - // See A8.6.57 T3, T4& A8.6.60 T2 and friends for why we morphed the opcode
> - // before returning it to our caller.
> - if (op1 == 3&& slice(op2, 6, 5) == 0&& slice(op2, 0, 0) == 1
> -&& slice(insn, 19, 16) == 15) {
> - unsigned morphed = T2Morph2LoadLiteral(unmorphed);
> - if (morphed != unmorphed)
> - return morphed;
> - }
> -
> - // See, for example, A8.6.117 PLD,PLDW (immediate) T1& T2, and friends for
> - // why we morphed the opcode before returning it to our caller.
> - if (slice(insn, 31, 25) == 0x7C&& slice(insn, 15, 12) == 0xF
> -&& slice(insn, 22, 22) == 0&& slice(insn, 20, 20) == 1
> -&& slice(insn, 19, 16) == 15) {
> - unsigned morphed = T2Morph2PLDLiteral(unmorphed);
> - if (morphed != unmorphed)
> - return morphed;
> - }
> -
> - // One last check for NEON/VFP instructions.
> - if ((op1 == 1 || op1 == 3)&& slice(op2, 6, 6) == 1)
> - return decodeInstruction(insn);
> +// Most Thumb instructions don't have explicit predicates in the
> +// encoding, but rather get their predicates from IT context. We need
> +// to fix up the predicate operands using this context information as a
> +// post-pass.
> +void ThumbDisassembler::AddThumbPredicate(MCInst&MI) const {
> + // A few instructions actually have predicates encoded in them. Don't
> + // try to overwrite it if we're seeing one of those.
> + switch (MI.getOpcode()) {
> + case ARM::tBcc:
> + case ARM::t2Bcc:
> + return;
> + default:
> + break;
> + }
>
> - // Fall through.
> + // If we're in an IT block, base the predicate on that. Otherwise,
> + // assume a predicate of AL.
> + unsigned CC;
> + if (ITBlock.size()) {
ITBlock.empty()? It's an std::vector<unsigned>.
> + CC = ITBlock.back();
> + ITBlock.pop_back();
> + } else
> + CC = ARMCC::AL;
> +
> + const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
> + MCInst::iterator I = MI.begin();
> + for (unsigned i = 0; i< MI.size(); ++i, ++I) {
> + if (OpInfo[i].isPredicate()) {
> + I = MI.insert(I, MCOperand::CreateImm(CC));
> + ++I;
> + if (CC == ARMCC::AL)
> + MI.insert(I, MCOperand::CreateReg(0));
> + else
> + MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
> + return;
> + }
This can be written without testing MI.size() every iteration.
> }
>
> - return decodeThumbInstruction(insn);
> + MI.insert(MI.end(), MCOperand::CreateImm(CC));
> + if (CC == ARMCC::AL)
> + MI.insert(MI.end(), MCOperand::CreateReg(0));
> + else
> + MI.insert(MI.end(), MCOperand::CreateReg(ARM::CPSR));
> }
>
> -//
> -// Public interface for the disassembler
> -//
> +// Thumb VFP instructions are a special case. Because we share their
> +// encodings between ARM and Thumb modes, and they are predicable in ARM
> +// mode, the auto-generated decoder will give them an (incorrect)
> +// predicate operand. We need to rewrite these operands based on the IT
> +// context as a post-pass.
> +void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst&MI) const {
> + unsigned CC;
> + if (ITBlock.size()) {
ITBlock.empty().
> + CC = ITBlock.back();
> + ITBlock.pop_back();
> + } else
> + CC = ARMCC::AL;
> +
> + const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
> + MCInst::iterator I = MI.begin();
> + for (unsigned i = 0; i< MI.size(); ++i, ++I) {
MI.size().
> + if (OpInfo[i].isPredicate() ) {
> + I->setImm(CC);
> + ++I;
> + if (CC == ARMCC::AL)
> + I->setReg(0);
> + else
> + I->setReg(ARM::CPSR);
> + return;
> + }
> + }
> +}
>
> -bool ARMDisassembler::getInstruction(MCInst&MI,
> - uint64_t&Size,
> - const MemoryObject&Region,
> - uint64_t Address,
> - raw_ostream&os) const {
> - // The machine instruction.
> - uint32_t insn;
> +
> +bool ThumbDisassembler::getInstruction(MCInst&MI, uint64_t&Size,
> + const MemoryObject&Region,
> + uint64_t Address,raw_ostream&os) const {
> uint8_t bytes[4];
>
> + // We want to read exactly 2 bytes of data.
> + if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1)
> + return false;
> +
> + uint16_t insn16 = (bytes[1]<< 8) | bytes[0];
> + bool result = decodeThumbInstruction16(MI, insn16, Address, this);
> + if (result) {
> + Size = 2;
> + bool InITBlock = ITBlock.size();
ITBlock.empty? :)
> + AddThumbPredicate(MI);
> + AddThumb1SBit(MI, InITBlock);
> + return true;
> + }
> +
> + MI.clear();
> + result = decodeThumb2Instruction16(MI, insn16, Address, this);
> + if (result) {
> + Size = 2;
> + AddThumbPredicate(MI);
> +
> + // If we find an IT instruction, we need to parse its condition
> + // code and mask operands so that we can apply them correctly
> + // to the subsequent instructions.
> + if (MI.getOpcode() == ARM::t2IT) {
> + unsigned firstcond = MI.getOperand(0).getImm();
> + uint32_t mask = MI.getOperand(1).getImm();
> + unsigned zeros = CountTrailingZeros_32(mask);
> + mask>>= zeros+1;
> +
> + for (unsigned i = 0; i< 4 - (zeros+1); ++i) {
> + if (firstcond ^ (mask& 1))
> + ITBlock.push_back(firstcond ^ 1);
> + else
> + ITBlock.push_back(firstcond);
> + mask>>= 1;
> + }
> + ITBlock.push_back(firstcond);
> + }
> +
> + return true;
> + }
> +
> // We want to read exactly 4 bytes of data.
> if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1)
> return false;
>
> - // Encoded as a small-endian 32-bit word in the stream.
> - insn = (bytes[3]<< 24) |
> - (bytes[2]<< 16) |
> - (bytes[1]<< 8) |
> - (bytes[0]<< 0);
> + uint32_t insn32 = (bytes[3]<< 8) |
> + (bytes[2]<< 0) |
> + (bytes[1]<< 24) |
> + (bytes[0]<< 16);
> + MI.clear();
> + result = decodeThumbInstruction32(MI, insn32, Address, this);
> + if (result) {
> + Size = 4;
> + bool InITBlock = ITBlock.size();
> + AddThumbPredicate(MI);
> + AddThumb1SBit(MI, InITBlock);
> + return true;
> + }
> +
> + MI.clear();
> + result = decodeThumb2Instruction32(MI, insn32, Address, this);
> + if (result) {
> + Size = 4;
> + AddThumbPredicate(MI);
> + return true;
> + }
> +
> + MI.clear();
> + result = decodeVFPInstruction32(MI, insn32, Address, this);
> + if (result) {
> + Size = 4;
> + UpdateThumbVFPPredicate(MI);
> + return true;
> + }
> +
> + MI.clear();
> + result = decodeCommonInstruction32(MI, insn32, Address, this);
> + if (result) {
> + Size = 4;
> + AddThumbPredicate(MI);
> + return true;
> + }
> +
> + return false;
> +}
>
> - unsigned Opcode = decodeARMInstruction(insn);
> - ARMFormat Format = ARMFormats[Opcode];
> - Size = 4;
>
> - DEBUG({
> - errs()<< "\nOpcode="<< Opcode<< " Name="<<ARMUtils::OpcodeName(Opcode)
> -<< " Format="<< stringForARMFormat(Format)<< '('<< (int)Format
> -<< ")\n";
> - showBitVector(errs(), insn);
> - });
> +extern "C" void LLVMInitializeARMDisassembler() {
> + TargetRegistry::RegisterMCDisassembler(TheARMTarget,
> + createARMDisassembler);
> + TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
> + createThumbDisassembler);
> +}
>
> - OwningPtr<ARMBasicMCBuilder> Builder(CreateMCBuilder(Opcode, Format));
> - if (!Builder)
> +static const unsigned GPRDecoderTable[] = {
> + ARM::R0, ARM::R1, ARM::R2, ARM::R3,
> + ARM::R4, ARM::R5, ARM::R6, ARM::R7,
> + ARM::R8, ARM::R9, ARM::R10, ARM::R11,
> + ARM::R12, ARM::SP, ARM::LR, ARM::PC
> +};
> +
> +static bool DecodeGPRRegisterClass(llvm::MCInst&Inst, unsigned RegNo,
> + uint64_t Address, const void *Decoder) {
> + if (RegNo> 15)
> return false;
>
> - Builder->setupBuilderForSymbolicDisassembly(getLLVMOpInfoCallback(),
> - getDisInfoBlock(), getMCContext(),
> - Address);
> + unsigned Register = GPRDecoderTable[RegNo];
> + Inst.addOperand(MCOperand::CreateReg(Register));
> + return true;
> +}
>
> - if (!Builder->Build(MI, insn))
> +static bool DecodetGPRRegisterClass(llvm::MCInst&Inst, unsigned RegNo,
> + uint64_t Address, const void *Decoder) {
> + if (RegNo> 7)
> return false;
> + return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
> +}
> +
> +static bool DecodetcGPRRegisterClass(llvm::MCInst&Inst, unsigned RegNo,
> + uint64_t Address, const void *Decoder) {
> + unsigned Register = 0;
> + switch (RegNo) {
> + case 0:
> + Register = ARM::R0;
> + break;
> + case 1:
> + Register = ARM::R1;
> + break;
> + case 2:
> + Register = ARM::R2;
> + break;
> + case 3:
> + Register = ARM::R3;
> + break;
> + case 9:
> + Register = ARM::R9;
> + break;
> + case 12:
> + Register = ARM::R12;
> + break;
> + default:
> + return false;
> + }
>
> + Inst.addOperand(MCOperand::CreateReg(Register));
> return true;
> }
>
> -bool ThumbDisassembler::getInstruction(MCInst&MI,
> - uint64_t&Size,
> - const MemoryObject&Region,
> - uint64_t Address,
> - raw_ostream&os) const {
> - // The Thumb instruction stream is a sequence of halfwords.
> -
> - // This represents the first halfword as well as the machine instruction
> - // passed to decodeThumbInstruction(). For 16-bit Thumb instruction, the top
> - // halfword of insn is 0x00 0x00; otherwise, the first halfword is moved to
> - // the top half followed by the second halfword.
> - unsigned insn = 0;
> - // Possible second halfword.
> - uint16_t insn1 = 0;
> -
> - // A6.1 Thumb instruction set encoding
> - //
> - // If bits [15:11] of the halfword being decoded take any of the following
> - // values, the halfword is the first halfword of a 32-bit instruction:
> - // o 0b11101
> - // o 0b11110
> - // o 0b11111.
> - //
> - // Otherwise, the halfword is a 16-bit instruction.
> +static bool DecoderGPRRegisterClass(llvm::MCInst&Inst, unsigned RegNo,
> + uint64_t Address, const void *Decoder) {
> + if (RegNo == 13 || RegNo == 15) return false;
> + return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
> +}
>
> - // Read 2 bytes of data first.
> - uint8_t bytes[2];
> - if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1)
> +static const unsigned SPRDecoderTable[] = {
> + ARM::S0, ARM::S1, ARM::S2, ARM::S3,
> + ARM::S4, ARM::S5, ARM::S6, ARM::S7,
> + ARM::S8, ARM::S9, ARM::S10, ARM::S11,
> + ARM::S12, ARM::S13, ARM::S14, ARM::S15,
> + ARM::S16, ARM::S17, ARM::S18, ARM::S19,
> + ARM::S20, ARM::S21, ARM::S22, ARM::S23,
> + ARM::S24, ARM::S25, ARM::S26, ARM::S27,
> + ARM::S28, ARM::S29, ARM::S30, ARM::S31
> +};
> +
> +static bool DecodeSPRRegisterClass(llvm::MCInst&Inst, unsigned RegNo,
> + uint64_t Address, const void *Decoder) {
> + if (RegNo> 31)
> return false;
>
> - // Encoded as a small-endian 16-bit halfword in the stream.
> - insn = (bytes[1]<< 8) | bytes[0];
> - unsigned bits15_11 = slice(insn, 15, 11);
> - bool IsThumb2 = false;
> -
> - // 32-bit instructions if the bits [15:11] of the halfword matches
> - // { 0b11101 /* 0x1D */, 0b11110 /* 0x1E */, ob11111 /* 0x1F */ }.
> - if (bits15_11 == 0x1D || bits15_11 == 0x1E || bits15_11 == 0x1F) {
> - IsThumb2 = true;
> - if (Region.readBytes(Address + 2, 2, (uint8_t*)bytes, NULL) == -1)
> - return false;
> - // Encoded as a small-endian 16-bit halfword in the stream.
> - insn1 = (bytes[1]<< 8) | bytes[0];
> - insn = (insn<< 16 | insn1);
> - }
> + unsigned Register = SPRDecoderTable[RegNo];
> + Inst.addOperand(MCOperand::CreateReg(Register));
> + return true;
> +}
>
> - // The insn could potentially be bit-twiddled in order to be decoded as an ARM
> - // NEON/VFP opcode. In such case, the modified insn is later disassembled as
> - // an ARM NEON/VFP instruction.
> - //
> - // This is a short term solution for lack of encoding bits specified for the
> - // Thumb2 NEON/VFP instructions. The long term solution could be adding some
> - // infrastructure to have each instruction support more than one encodings.
> - // Which encoding is used would be based on which subtarget the compiler/
> - // disassembler is working with at the time. This would allow the sharing of
> - // the NEON patterns between ARM and Thumb2, as well as potential greater
> - // sharing between the regular ARM instructions and the 32-bit wide Thumb2
> - // instructions as well.
> - unsigned Opcode = decodeThumbSideEffect(IsThumb2, insn);
> +static const unsigned DPRDecoderTable[] = {
> + ARM::D0, ARM::D1, ARM::D2, ARM::D3,
> + ARM::D4, ARM::D5, ARM::D6, ARM::D7,
> + ARM::D8, ARM::D9, ARM::D10, ARM::D11,
> + ARM::D12, ARM::D13, ARM::D14, ARM::D15,
> + ARM::D16, ARM::D17, ARM::D18, ARM::D19,
> + ARM::D20, ARM::D21, ARM::D22, ARM::D23,
> + ARM::D24, ARM::D25, ARM::D26, ARM::D27,
> + ARM::D28, ARM::D29, ARM::D30, ARM::D31
> +};
> +
> +static bool DecodeDPRRegisterClass(llvm::MCInst&Inst, unsigned RegNo,
> + uint64_t Address, const void *Decoder) {
> + if (RegNo> 31)
> + return false;
>
> - ARMFormat Format = ARMFormats[Opcode];
> - Size = IsThumb2 ? 4 : 2;
> + unsigned Register = DPRDecoderTable[RegNo];
> + Inst.addOperand(MCOperand::CreateReg(Register));
> + return true;
> +}
>
> - DEBUG({
> - errs()<< "Opcode="<< Opcode<< " Name="<< ARMUtils::OpcodeName(Opcode)
> -<< " Format="<< stringForARMFormat(Format)<< '('<< (int)Format
> -<< ")\n";
> - showBitVector(errs(), insn);
> - });
> +static bool DecodeDPR_8RegisterClass(llvm::MCInst&Inst, unsigned RegNo,
> + uint64_t Address, const void *Decoder) {
> + if (RegNo> 7)
> + return false;
> + return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
> +}
>
> - OwningPtr<ARMBasicMCBuilder> Builder(CreateMCBuilder(Opcode, Format));
> - if (!Builder)
> +static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst&Inst, unsigned RegNo,
> + uint64_t Address, const void *Decoder) {
> + if (RegNo> 15)
> return false;
> + return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
> +}
>
> - Builder->SetSession(const_cast<Session *>(&SO));
> +static const unsigned QPRDecoderTable[] = {
> + ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
> + ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
> + ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
> + ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
> +};
>
> - Builder->setupBuilderForSymbolicDisassembly(getLLVMOpInfoCallback(),
> - getDisInfoBlock(), getMCContext(),
> - Address);
>
> - if (!Builder->Build(MI, insn))
> +static bool DecodeQPRRegisterClass(llvm::MCInst&Inst, unsigned RegNo,
> + uint64_t Address, const void *Decoder) {
> + if (RegNo> 31)
> return false;
> + RegNo>>= 1;
>
> + unsigned Register = QPRDecoderTable[RegNo];
> + Inst.addOperand(MCOperand::CreateReg(Register));
> return true;
> }
>
> -// A8.6.50
> -// Valid return values are {1, 2, 3, 4}, with 0 signifying an error condition.
> -static unsigned short CountITSize(unsigned ITMask) {
> - // First count the trailing zeros of the IT mask.
> - unsigned TZ = CountTrailingZeros_32(ITMask);
> - if (TZ> 3) {
> - DEBUG(errs()<< "Encoding error: IT Mask '0000'");
> - return 0;
> - }
> - return (4 - TZ);
> +static bool DecodePredicateOperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> + if (Val == 0xF) return false;
> + Inst.addOperand(MCOperand::CreateImm(Val));
> + if (Val == ARMCC::AL) {
> + Inst.addOperand(MCOperand::CreateReg(0));
> + } else
> + Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
> + return true;
> }
>
> -/// Init ITState. Note that at least one bit is always 1 in mask.
> -bool Session::InitIT(unsigned short bits7_0) {
> - ITCounter = CountITSize(slice(bits7_0, 3, 0));
> - if (ITCounter == 0)
> - return false;
> +static bool DecodeCCOutOperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> + if (Val)
> + Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
> + else
> + Inst.addOperand(MCOperand::CreateReg(0));
> + return true;
> +}
>
> - // A8.6.50 IT
> - unsigned short FirstCond = slice(bits7_0, 7, 4);
> - if (FirstCond == 0xF) {
> - DEBUG(errs()<< "Encoding error: IT FirstCond '1111'");
> - return false;
> +static bool DecodeSOImmOperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> + uint32_t imm = Val& 0xFF;
> + uint32_t rot = (Val& 0xF00)>> 7;
> + uint32_t rot_imm = (imm>> rot) | (imm<< (32-rot));
> + Inst.addOperand(MCOperand::CreateImm(rot_imm));
> + return true;
> +}
> +
> +static bool DecodeBLTargetOperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> + Val<<= 2;
> + Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val)));
> + return true;
> +}
> +
> +static bool DecodeSORegImmOperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> +
> + unsigned Rm = fieldFromInstruction32(Val, 0, 4);
> + unsigned type = fieldFromInstruction32(Val, 5, 2);
> + unsigned imm = fieldFromInstruction32(Val, 7, 5);
> +
> + // Register-immediate
> + DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
> +
> + ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
> + switch (type) {
> + case 0:
> + Shift = ARM_AM::lsl;
> + break;
> + case 1:
> + Shift = ARM_AM::lsr;
> + break;
> + case 2:
> + Shift = ARM_AM::asr;
> + break;
> + case 3:
> + Shift = ARM_AM::ror;
> + break;
> }
> - if (FirstCond == 0xE&& ITCounter != 1) {
> - DEBUG(errs()<< "Encoding error: IT FirstCond '1110'&& Mask != '1000'");
> - return false;
> +
> + if (Shift == ARM_AM::ror&& imm == 0)
> + Shift = ARM_AM::rrx;
> +
> + unsigned Op = Shift | (imm<< 3);
> + Inst.addOperand(MCOperand::CreateImm(Op));
> +
> + return true;
> +}
> +
> +static bool DecodeSORegRegOperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> +
> + unsigned Rm = fieldFromInstruction32(Val, 0, 4);
> + unsigned type = fieldFromInstruction32(Val, 5, 2);
> + unsigned Rs = fieldFromInstruction32(Val, 8, 4);
> +
> + // Register-register
> + DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
> + DecodeGPRRegisterClass(Inst, Rs, Address, Decoder);
> +
> + ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
> + switch (type) {
> + case 0:
> + Shift = ARM_AM::lsl;
> + break;
> + case 1:
> + Shift = ARM_AM::lsr;
> + break;
> + case 2:
> + Shift = ARM_AM::asr;
> + break;
> + case 3:
> + Shift = ARM_AM::ror;
> + break;
> }
>
> - ITState = bits7_0;
> + Inst.addOperand(MCOperand::CreateImm(Shift));
>
> return true;
> }
>
> -/// Update ITState if necessary.
> -void Session::UpdateIT() {
> - assert(ITCounter);
> - --ITCounter;
> - if (ITCounter == 0)
> - ITState = 0;
> - else {
> - unsigned short NewITState4_0 = slice(ITState, 4, 0)<< 1;
> - setSlice(ITState, 4, 0, NewITState4_0);
> +static bool DecodeRegListOperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> + for (unsigned i = 0; i< 16; ++i) {
> + if (Val& (1<< i))
> + DecodeGPRRegisterClass(Inst, i, Address, Decoder);
> }
> +
> + return true;
> }
>
> -static MCDisassembler *createARMDisassembler(const Target&T) {
> - return new ARMDisassembler;
> +static bool DecodeSPRRegListOperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> + unsigned Vd = fieldFromInstruction32(Val, 8, 4);
> + unsigned regs = Val& 0xFF;
> +
> + DecodeSPRRegisterClass(Inst, Vd, Address, Decoder);
> + for (unsigned i = 0; i< (regs - 1); ++i)
> + DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder);
> +
> + return true;
> }
>
> -static MCDisassembler *createThumbDisassembler(const Target&T) {
> - return new ThumbDisassembler;
> +static bool DecodeDPRRegListOperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> + unsigned Vd = fieldFromInstruction32(Val, 8, 4);
> + unsigned regs = (Val& 0xFF) / 2;
> +
> + DecodeDPRRegisterClass(Inst, Vd, Address, Decoder);
> + for (unsigned i = 0; i< (regs - 1); ++i)
> + DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder);
> +
> + return true;
> }
>
> -extern "C" void LLVMInitializeARMDisassembler() {
> - // Register the disassembler.
> - TargetRegistry::RegisterMCDisassembler(TheARMTarget,
> - createARMDisassembler);
> - TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
> - createThumbDisassembler);
> +static bool DecodeBitfieldMaskOperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> + unsigned msb = fieldFromInstruction32(Val, 5, 5);
> + unsigned lsb = fieldFromInstruction32(Val, 0, 5);
> + uint32_t msb_mask = (1<< (msb+1)) - 1;
> + uint32_t lsb_mask = (1<< lsb) - 1;
> + Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
What? I think this code has earned some comments. :)
> + return true;
> }
>
> -EDInstInfo *ARMDisassembler::getEDInfo() const {
> - return instInfoARM;
> +static bool DecodeCopMemInstruction(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder) {
> + unsigned pred = fieldFromInstruction32(Insn, 28, 4);
> + unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
> + unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
> + unsigned imm = fieldFromInstruction32(Insn, 0, 8);
> + unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> + unsigned U = fieldFromInstruction32(Insn, 23, 1);
> +
> + switch (Inst.getOpcode()) {
> + case ARM::LDC_OFFSET:
> + case ARM::LDC_PRE:
> + case ARM::LDC_POST:
> + case ARM::LDC_OPTION:
> + case ARM::LDCL_OFFSET:
> + case ARM::LDCL_PRE:
> + case ARM::LDCL_POST:
> + case ARM::LDCL_OPTION:
> + case ARM::STC_OFFSET:
> + case ARM::STC_PRE:
> + case ARM::STC_POST:
> + case ARM::STC_OPTION:
> + case ARM::STCL_OFFSET:
> + case ARM::STCL_PRE:
> + case ARM::STCL_POST:
> + case ARM::STCL_OPTION:
> + if (coproc == 0xA || coproc == 0xB)
> + return false;
> + break;
> + default:
> + break;
> + }
> +
> + Inst.addOperand(MCOperand::CreateImm(coproc));
> + Inst.addOperand(MCOperand::CreateImm(CRd));
> + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
> + switch (Inst.getOpcode()) {
> + case ARM::LDC_OPTION:
> + case ARM::LDCL_OPTION:
> + case ARM::LDC2_OPTION:
> + case ARM::LDC2L_OPTION:
> + case ARM::STC_OPTION:
> + case ARM::STCL_OPTION:
> + case ARM::STC2_OPTION:
> + case ARM::STC2L_OPTION:
> + case ARM::LDCL_POST:
> + case ARM::STCL_POST:
> + break;
> + default:
> + Inst.addOperand(MCOperand::CreateReg(0));
> + break;
> + }
> +
> + unsigned P = fieldFromInstruction32(Insn, 24, 1);
> + unsigned W = fieldFromInstruction32(Insn, 21, 1);
> +
> + bool writeback = (P == 0) || (W == 1);
> + unsigned idx_mode = 0;
> + if (P&& writeback)
> + idx_mode = ARMII::IndexModePre;
> + else if (!P&& writeback)
> + idx_mode = ARMII::IndexModePost;
> +
> + switch (Inst.getOpcode()) {
> + case ARM::LDCL_POST:
> + case ARM::STCL_POST:
> + imm |= U<< 8;
> + case ARM::LDC_OPTION:
> + case ARM::LDCL_OPTION:
> + case ARM::LDC2_OPTION:
> + case ARM::LDC2L_OPTION:
> + case ARM::STC_OPTION:
> + case ARM::STCL_OPTION:
> + case ARM::STC2_OPTION:
> + case ARM::STC2L_OPTION:
> + Inst.addOperand(MCOperand::CreateImm(imm));
> + break;
> + default:
> + if (U)
> + Inst.addOperand(MCOperand::CreateImm(
> + ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode)));
> + else
> + Inst.addOperand(MCOperand::CreateImm(
> + ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode)));
> + break;
> + }
> +
> + switch (Inst.getOpcode()) {
> + case ARM::LDC_OFFSET:
> + case ARM::LDC_PRE:
> + case ARM::LDC_POST:
> + case ARM::LDC_OPTION:
> + case ARM::LDCL_OFFSET:
> + case ARM::LDCL_PRE:
> + case ARM::LDCL_POST:
> + case ARM::LDCL_OPTION:
> + case ARM::STC_OFFSET:
> + case ARM::STC_PRE:
> + case ARM::STC_POST:
> + case ARM::STC_OPTION:
> + case ARM::STCL_OFFSET:
> + case ARM::STCL_PRE:
> + case ARM::STCL_POST:
> + case ARM::STCL_OPTION:
> + if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
> + break;
> + default:
> + break;
> + }
> +
> + return true;
> }
>
> -EDInstInfo *ThumbDisassembler::getEDInfo() const {
> - return instInfoARM;
> +static bool DecodeAddrMode2IdxInstruction(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder) {
> + unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> + unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
> + unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> + unsigned imm = fieldFromInstruction32(Insn, 0, 12);
> + unsigned pred = fieldFromInstruction32(Insn, 28, 4);
> + unsigned reg = fieldFromInstruction32(Insn, 25, 1);
> + unsigned P = fieldFromInstruction32(Insn, 24, 1);
> + unsigned W = fieldFromInstruction32(Insn, 21, 1);
> +
> + // On stores, the writeback operand precedes Rt.
> + switch (Inst.getOpcode()) {
> + case ARM::STR_POST_IMM:
> + case ARM::STR_POST_REG:
> + case ARM::STRTr:
> + case ARM::STRTi:
> + case ARM::STRBTr:
> + case ARM::STRBTi:
> + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
> + break;
> + default:
> + break;
> + }
> +
> + DecodeGPRRegisterClass(Inst, Rt, Address, Decoder);
> +
> + // On loads, the writeback operand comes after Rt.
> + switch (Inst.getOpcode()) {
> + case ARM::LDR_POST_IMM:
> + case ARM::LDR_POST_REG:
> + case ARM::LDR_PRE:
> + case ARM::LDRBT_POST_REG:
> + case ARM::LDRBT_POST_IMM:
> + case ARM::LDRTr:
> + case ARM::LDRTi:
> + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
> + break;
> + default:
> + break;
> + }
> +
> + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
> +
> + ARM_AM::AddrOpc Op = ARM_AM::add;
> + if (!fieldFromInstruction32(Insn, 23, 1))
> + Op = ARM_AM::sub;
> +
> + bool writeback = (P == 0) || (W == 1);
> + unsigned idx_mode = 0;
> + if (P&& writeback)
> + idx_mode = ARMII::IndexModePre;
> + else if (!P&& writeback)
> + idx_mode = ARMII::IndexModePost;
> +
> + if (reg) {
> + DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
> + ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
> + switch( fieldFromInstruction32(Insn, 5, 2)) {
> + case 0:
> + Opc = ARM_AM::lsl;
> + break;
> + case 1:
> + Opc = ARM_AM::lsr;
> + break;
> + case 2:
> + Opc = ARM_AM::asr;
> + break;
> + case 3:
> + Opc = ARM_AM::ror;
> + break;
> + default:
> + return false;
> + }
> + unsigned amt = fieldFromInstruction32(Insn, 7, 5);
> + unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
> +
> + Inst.addOperand(MCOperand::CreateImm(imm));
> + } else {
> + Inst.addOperand(MCOperand::CreateReg(0));
> + unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
> + Inst.addOperand(MCOperand::CreateImm(tmp));
> + }
> +
> + if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
> +
> + return true;
> +}
> +
> +static bool DecodeSORegMemOperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> + unsigned Rn = fieldFromInstruction32(Val, 13, 4);
> + unsigned Rm = fieldFromInstruction32(Val, 0, 4);
> + unsigned type = fieldFromInstruction32(Val, 5, 2);
> + unsigned imm = fieldFromInstruction32(Val, 7, 5);
> + unsigned U = fieldFromInstruction32(Val, 12, 1);
> +
> + ARM_AM::ShiftOpc ShOp;
> + switch (type) {
> + case 0:
> + ShOp = ARM_AM::lsl;
> + break;
> + case 1:
> + ShOp = ARM_AM::lsr;
> + break;
> + case 2:
> + ShOp = ARM_AM::asr;
> + break;
> + case 3:
> + ShOp = ARM_AM::ror;
> + break;
> + }
> +
> + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
> + DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
> + unsigned shift;
> + if (U)
> + shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
> + else
> + shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
> + Inst.addOperand(MCOperand::CreateImm(shift));
> +
> + return true;
> +}
> +
> +static bool DecodeAddrMode3Instruction(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder) {
> + unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
> + unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> + unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> + unsigned type = fieldFromInstruction32(Insn, 22, 1);
> + unsigned imm = fieldFromInstruction32(Insn, 8, 4);
> + unsigned U = ((~fieldFromInstruction32(Insn, 23, 1))& 1)<< 8;
> + unsigned pred = fieldFromInstruction32(Insn, 28, 4);
> + unsigned W = fieldFromInstruction32(Insn, 21, 1);
> + unsigned P = fieldFromInstruction32(Insn, 24, 1);
> +
> + bool writeback = (W == 1) | (P == 0);
> + if (writeback) { // Writeback
> + if (P)
> + U |= ARMII::IndexModePre<< 9;
> + else
> + U |= ARMII::IndexModePost<< 9;
> +
> + // On stores, the writeback operand precedes Rt.
> + switch (Inst.getOpcode()) {
> + case ARM::STRD:
> + case ARM::STRD_PRE:
> + case ARM::STRD_POST:
> + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
> + break;
> + default:
> + break;
> + }
> + }
> +
> + DecodeGPRRegisterClass(Inst, Rt, Address, Decoder);
> + switch (Inst.getOpcode()) {
> + case ARM::STRD:
> + case ARM::STRD_PRE:
> + case ARM::STRD_POST:
> + case ARM::LDRD:
> + case ARM::LDRD_PRE:
> + case ARM::LDRD_POST:
> + DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder);
> + break;
> + default:
> + break;
> + }
> +
> + if (writeback) {
> + // On loads, the writeback operand comes after Rt.
> + switch (Inst.getOpcode()) {
> + case ARM::LDRD:
> + case ARM::LDRD_PRE:
> + case ARM::LDRD_POST:
> + case ARM::LDRHTr:
> + case ARM::LDRSBTr:
> + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
> + break;
> + default:
> + break;
> + }
> + }
> +
> + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
> +
> + if (type) {
> + Inst.addOperand(MCOperand::CreateReg(0));
> + Inst.addOperand(MCOperand::CreateImm(U | (imm<< 4) | Rm));
> + } else {
> + DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
> + Inst.addOperand(MCOperand::CreateImm(U));
> + }
> +
> + if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
> +
> + return true;
> +}
> +
> +static bool DecodeRFEInstruction(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder) {
> + unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> + unsigned mode = fieldFromInstruction32(Insn, 23, 2);
> +
> + switch (mode) {
> + case 0:
> + mode = ARM_AM::da;
> + break;
> + case 1:
> + mode = ARM_AM::ia;
> + break;
> + case 2:
> + mode = ARM_AM::db;
> + break;
> + case 3:
> + mode = ARM_AM::ib;
> + break;
> + }
> +
> + Inst.addOperand(MCOperand::CreateImm(mode));
> + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
> +
> + return true;
> +}
> +
> +static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst&Inst,
> + unsigned Insn,
> + uint64_t Address, const void *Decoder) {
> + unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> + unsigned pred = fieldFromInstruction32(Insn, 28, 4);
> + unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
> +
> + if (pred == 0xF) {
> + switch (Inst.getOpcode()) {
> + case ARM::STMDA:
> + Inst.setOpcode(ARM::RFEDA);
> + break;
> + case ARM::STMDA_UPD:
> + Inst.setOpcode(ARM::RFEDA_UPD);
> + break;
> + case ARM::STMDB:
> + Inst.setOpcode(ARM::RFEDB);
> + break;
> + case ARM::STMDB_UPD:
> + Inst.setOpcode(ARM::RFEDB_UPD);
> + break;
> + case ARM::STMIA:
> + Inst.setOpcode(ARM::RFEIA);
> + break;
> + case ARM::STMIA_UPD:
> + Inst.setOpcode(ARM::RFEIA_UPD);
> + break;
> + case ARM::STMIB:
> + Inst.setOpcode(ARM::RFEIB);
> + break;
> + case ARM::STMIB_UPD:
> + Inst.setOpcode(ARM::RFEIB_UPD);
> + break;
> +
Extra newline.
> + }
> + return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
> + }
> +
> + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
> + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); // Tied
> + if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
> + DecodeRegListOperand(Inst, reglist, Address, Decoder);
> +
> + return true;
> +}
> +
> +static bool DecodeCPSInstruction(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder) {
> + unsigned imod = fieldFromInstruction32(Insn, 18, 2);
> + unsigned M = fieldFromInstruction32(Insn, 17, 1);
> + unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
> + unsigned mode = fieldFromInstruction32(Insn, 0, 5);
> +
> + if (M&& mode&& imod&& iflags) {
> + Inst.setOpcode(ARM::CPS3p);
> + Inst.addOperand(MCOperand::CreateImm(imod));
> + Inst.addOperand(MCOperand::CreateImm(iflags));
> + Inst.addOperand(MCOperand::CreateImm(mode));
> + return true;
> + } else if (!mode&& !M) {
> + Inst.setOpcode(ARM::CPS2p);
> + Inst.addOperand(MCOperand::CreateImm(imod));
> + Inst.addOperand(MCOperand::CreateImm(iflags));
> + return true;
> + } else if (!imod&& !iflags&& M) {
> + Inst.setOpcode(ARM::CPS1p);
> + Inst.addOperand(MCOperand::CreateImm(mode));
> + return true;
> + }
> +
> + return false;
> +}
> +
> +static bool DecodeSMLAInstruction(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder) {
> + unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
> + unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
> + unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
> + unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
> + unsigned pred = fieldFromInstruction32(Insn, 28, 4);
> +
> + if (pred == 0xF)
> + return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
> +
> + DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
> + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
> + DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
> + DecodeGPRRegisterClass(Inst, Ra, Address, Decoder);
> +
> + return true;
> +}
> +
> +static bool DecodeAddrModeImm12Operand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> + unsigned add = fieldFromInstruction32(Val, 12, 1);
> + unsigned imm = fieldFromInstruction32(Val, 0, 12);
> + unsigned Rn = fieldFromInstruction32(Val, 13, 4);
> +
> + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
> +
> + if (!add) imm *= -1;
> + if (imm == 0&& !add) imm = INT32_MIN;
> + Inst.addOperand(MCOperand::CreateImm(imm));
> +
> + return true;
> +}
> +
> +static bool DecodeAddrMode5Operand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> + unsigned Rn = fieldFromInstruction32(Val, 9, 4);
> + unsigned U = fieldFromInstruction32(Val, 8, 1);
> + unsigned imm = fieldFromInstruction32(Val, 0, 8);
> +
> + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
> +
> + if (U)
> + Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
> + else
> + Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
> +
> + return true;
> +}
> +
> +static bool DecodeAddrMode7Operand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> + return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
> +}
> +
> +static bool DecodeBranchImmInstruction(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder) {
> + unsigned pred = fieldFromInstruction32(Insn, 28, 4);
> + unsigned imm = fieldFromInstruction32(Insn, 0, 24)<< 2;
> +
> + if (pred == 0xF) {
> + Inst.setOpcode(ARM::BLXi);
> + imm |= fieldFromInstruction32(Insn, 24, 1)<< 1;
> + Inst.addOperand(MCOperand::CreateImm(imm));
> + return true;
> + }
> +
> + Inst.addOperand(MCOperand::CreateImm(imm));
> + if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
> +
> + return true;
> +}
> +
> +
> +static bool DecodeVCVTImmOperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> + Inst.addOperand(MCOperand::CreateImm(64 - Val));
> + return true;
> +}
> +
> +static bool DecodeAddrMode6Operand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> + unsigned Rm = fieldFromInstruction32(Val, 0, 4);
> + unsigned align = fieldFromInstruction32(Val, 4, 2);
> +
> + DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
> + if (!align)
> + Inst.addOperand(MCOperand::CreateImm(0));
> + else
> + Inst.addOperand(MCOperand::CreateImm(4<< align));
> +
> + return true;
> +}
> +
> +static bool DecodeVLDInstruction(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder) {
> + unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> + Rd |= fieldFromInstruction32(Insn, 22, 1)<< 4;
> + unsigned wb = fieldFromInstruction32(Insn, 16, 4);
> + unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> + Rn |= fieldFromInstruction32(Insn, 4, 2)<< 4;
> + unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> +
> + // First output register
> + DecodeDPRRegisterClass(Inst, Rd, Address, Decoder);
> +
> + // Second output register
> + switch (Inst.getOpcode()) {
> + case ARM::VLD1q8:
> + case ARM::VLD1q16:
> + case ARM::VLD1q32:
> + case ARM::VLD1q64:
> + case ARM::VLD1q8_UPD:
> + case ARM::VLD1q16_UPD:
> + case ARM::VLD1q32_UPD:
> + case ARM::VLD1q64_UPD:
> + case ARM::VLD1d8T:
> + case ARM::VLD1d16T:
> + case ARM::VLD1d32T:
> + case ARM::VLD1d64T:
> + case ARM::VLD1d8T_UPD:
> + case ARM::VLD1d16T_UPD:
> + case ARM::VLD1d32T_UPD:
> + case ARM::VLD1d64T_UPD:
> + case ARM::VLD1d8Q:
> + case ARM::VLD1d16Q:
> + case ARM::VLD1d32Q:
> + case ARM::VLD1d64Q:
> + case ARM::VLD1d8Q_UPD:
> + case ARM::VLD1d16Q_UPD:
> + case ARM::VLD1d32Q_UPD:
> + case ARM::VLD1d64Q_UPD:
> + case ARM::VLD2d8:
> + case ARM::VLD2d16:
> + case ARM::VLD2d32:
> + case ARM::VLD2d8_UPD:
> + case ARM::VLD2d16_UPD:
> + case ARM::VLD2d32_UPD:
> + case ARM::VLD2q8:
> + case ARM::VLD2q16:
> + case ARM::VLD2q32:
> + case ARM::VLD2q8_UPD:
> + case ARM::VLD2q16_UPD:
> + case ARM::VLD2q32_UPD:
> + case ARM::VLD3d8:
> + case ARM::VLD3d16:
> + case ARM::VLD3d32:
> + case ARM::VLD3d8_UPD:
> + case ARM::VLD3d16_UPD:
> + case ARM::VLD3d32_UPD:
> + case ARM::VLD4d8:
> + case ARM::VLD4d16:
> + case ARM::VLD4d32:
> + case ARM::VLD4d8_UPD:
> + case ARM::VLD4d16_UPD:
> + case ARM::VLD4d32_UPD:
> + DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder);
> + break;
> + case ARM::VLD2b8:
> + case ARM::VLD2b16:
> + case ARM::VLD2b32:
> + case ARM::VLD2b8_UPD:
> + case ARM::VLD2b16_UPD:
> + case ARM::VLD2b32_UPD:
> + case ARM::VLD3q8:
> + case ARM::VLD3q16:
> + case ARM::VLD3q32:
> + case ARM::VLD3q8_UPD:
> + case ARM::VLD3q16_UPD:
> + case ARM::VLD3q32_UPD:
> + case ARM::VLD4q8:
> + case ARM::VLD4q16:
> + case ARM::VLD4q32:
> + case ARM::VLD4q8_UPD:
> + case ARM::VLD4q16_UPD:
> + case ARM::VLD4q32_UPD:
> + DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder);
> + default:
> + break;
> + }
> +
> + // Third output register
> + switch(Inst.getOpcode()) {
> + case ARM::VLD1d8T:
> + case ARM::VLD1d16T:
> + case ARM::VLD1d32T:
> + case ARM::VLD1d64T:
> + case ARM::VLD1d8T_UPD:
> + case ARM::VLD1d16T_UPD:
> + case ARM::VLD1d32T_UPD:
> + case ARM::VLD1d64T_UPD:
> + case ARM::VLD1d8Q:
> + case ARM::VLD1d16Q:
> + case ARM::VLD1d32Q:
> + case ARM::VLD1d64Q:
> + case ARM::VLD1d8Q_UPD:
> + case ARM::VLD1d16Q_UPD:
> + case ARM::VLD1d32Q_UPD:
> + case ARM::VLD1d64Q_UPD:
> + case ARM::VLD2q8:
> + case ARM::VLD2q16:
> + case ARM::VLD2q32:
> + case ARM::VLD2q8_UPD:
> + case ARM::VLD2q16_UPD:
> + case ARM::VLD2q32_UPD:
> + case ARM::VLD3d8:
> + case ARM::VLD3d16:
> + case ARM::VLD3d32:
> + case ARM::VLD3d8_UPD:
> + case ARM::VLD3d16_UPD:
> + case ARM::VLD3d32_UPD:
> + case ARM::VLD4d8:
> + case ARM::VLD4d16:
> + case ARM::VLD4d32:
> + case ARM::VLD4d8_UPD:
> + case ARM::VLD4d16_UPD:
> + case ARM::VLD4d32_UPD:
> + DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder);
> + break;
> + case ARM::VLD3q8:
> + case ARM::VLD3q16:
> + case ARM::VLD3q32:
> + case ARM::VLD3q8_UPD:
> + case ARM::VLD3q16_UPD:
> + case ARM::VLD3q32_UPD:
> + case ARM::VLD4q8:
> + case ARM::VLD4q16:
> + case ARM::VLD4q32:
> + case ARM::VLD4q8_UPD:
> + case ARM::VLD4q16_UPD:
> + case ARM::VLD4q32_UPD:
> + DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder);
> + break;
> + default:
> + break;
> + }
> +
> + // Fourth output register
> + switch (Inst.getOpcode()) {
> + case ARM::VLD1d8Q:
> + case ARM::VLD1d16Q:
> + case ARM::VLD1d32Q:
> + case ARM::VLD1d64Q:
> + case ARM::VLD1d8Q_UPD:
> + case ARM::VLD1d16Q_UPD:
> + case ARM::VLD1d32Q_UPD:
> + case ARM::VLD1d64Q_UPD:
> + case ARM::VLD2q8:
> + case ARM::VLD2q16:
> + case ARM::VLD2q32:
> + case ARM::VLD2q8_UPD:
> + case ARM::VLD2q16_UPD:
> + case ARM::VLD2q32_UPD:
> + case ARM::VLD4d8:
> + case ARM::VLD4d16:
> + case ARM::VLD4d32:
> + case ARM::VLD4d8_UPD:
> + case ARM::VLD4d16_UPD:
> + case ARM::VLD4d32_UPD:
> + DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder);
> + break;
> + case ARM::VLD4q8:
> + case ARM::VLD4q16:
> + case ARM::VLD4q32:
> + case ARM::VLD4q8_UPD:
> + case ARM::VLD4q16_UPD:
> + case ARM::VLD4q32_UPD:
> + DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder);
> + break;
> + default:
> + break;
> + }
> +
> + // Writeback operand
> + switch (Inst.getOpcode()) {
> + case ARM::VLD1d8_UPD:
> + case ARM::VLD1d16_UPD:
> + case ARM::VLD1d32_UPD:
> + case ARM::VLD1d64_UPD:
> + case ARM::VLD1q8_UPD:
> + case ARM::VLD1q16_UPD:
> + case ARM::VLD1q32_UPD:
> + case ARM::VLD1q64_UPD:
> + case ARM::VLD1d8T_UPD:
> + case ARM::VLD1d16T_UPD:
> + case ARM::VLD1d32T_UPD:
> + case ARM::VLD1d64T_UPD:
> + case ARM::VLD1d8Q_UPD:
> + case ARM::VLD1d16Q_UPD:
> + case ARM::VLD1d32Q_UPD:
> + case ARM::VLD1d64Q_UPD:
> + case ARM::VLD2d8_UPD:
> + case ARM::VLD2d16_UPD:
> + case ARM::VLD2d32_UPD:
> + case ARM::VLD2q8_UPD:
> + case ARM::VLD2q16_UPD:
> + case ARM::VLD2q32_UPD:
> + case ARM::VLD2b8_UPD:
> + case ARM::VLD2b16_UPD:
> + case ARM::VLD2b32_UPD:
> + case ARM::VLD3d8_UPD:
> + case ARM::VLD3d16_UPD:
> + case ARM::VLD3d32_UPD:
> + case ARM::VLD3q8_UPD:
> + case ARM::VLD3q16_UPD:
> + case ARM::VLD3q32_UPD:
> + case ARM::VLD4d8_UPD:
> + case ARM::VLD4d16_UPD:
> + case ARM::VLD4d32_UPD:
> + case ARM::VLD4q8_UPD:
> + case ARM::VLD4q16_UPD:
> + case ARM::VLD4q32_UPD:
> + DecodeGPRRegisterClass(Inst, wb, Address, Decoder);
> + break;
> + default:
> + break;
> + }
> +
> + // AddrMode6 Base (register+alignment)
> + DecodeAddrMode6Operand(Inst, Rn, Address, Decoder);
> +
> + // AddrMode6 Offset (register)
> + if (Rm == 0xD)
> + Inst.addOperand(MCOperand::CreateReg(0));
> + else if (Rm != 0xF)
> + DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
> +
> + return true;
> +}
> +
> +static bool DecodeVSTInstruction(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder) {
> + unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> + Rd |= fieldFromInstruction32(Insn, 22, 1)<< 4;
> + unsigned wb = fieldFromInstruction32(Insn, 16, 4);
> + unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> + Rn |= fieldFromInstruction32(Insn, 4, 2)<< 4;
> + unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> +
> + // Writeback Operand
> + switch (Inst.getOpcode()) {
> + case ARM::VST1d8_UPD:
> + case ARM::VST1d16_UPD:
> + case ARM::VST1d32_UPD:
> + case ARM::VST1d64_UPD:
> + case ARM::VST1q8_UPD:
> + case ARM::VST1q16_UPD:
> + case ARM::VST1q32_UPD:
> + case ARM::VST1q64_UPD:
> + case ARM::VST1d8T_UPD:
> + case ARM::VST1d16T_UPD:
> + case ARM::VST1d32T_UPD:
> + case ARM::VST1d64T_UPD:
> + case ARM::VST1d8Q_UPD:
> + case ARM::VST1d16Q_UPD:
> + case ARM::VST1d32Q_UPD:
> + case ARM::VST1d64Q_UPD:
> + case ARM::VST2d8_UPD:
> + case ARM::VST2d16_UPD:
> + case ARM::VST2d32_UPD:
> + case ARM::VST2q8_UPD:
> + case ARM::VST2q16_UPD:
> + case ARM::VST2q32_UPD:
> + case ARM::VST2b8_UPD:
> + case ARM::VST2b16_UPD:
> + case ARM::VST2b32_UPD:
> + case ARM::VST3d8_UPD:
> + case ARM::VST3d16_UPD:
> + case ARM::VST3d32_UPD:
> + case ARM::VST3q8_UPD:
> + case ARM::VST3q16_UPD:
> + case ARM::VST3q32_UPD:
> + case ARM::VST4d8_UPD:
> + case ARM::VST4d16_UPD:
> + case ARM::VST4d32_UPD:
> + case ARM::VST4q8_UPD:
> + case ARM::VST4q16_UPD:
> + case ARM::VST4q32_UPD:
> + DecodeGPRRegisterClass(Inst, wb, Address, Decoder);
> + break;
> + default:
> + break;
> + }
> +
> + // AddrMode6 Base (register+alignment)
> + DecodeAddrMode6Operand(Inst, Rn, Address, Decoder);
> +
> + // AddrMode6 Offset (register)
> + if (Rm == 0xD)
> + Inst.addOperand(MCOperand::CreateReg(0));
> + else if (Rm != 0xF)
> + DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
> +
> + // First input register
> + DecodeDPRRegisterClass(Inst, Rd, Address, Decoder);
> +
> + // Second input register
> + switch (Inst.getOpcode()) {
> + case ARM::VST1q8:
> + case ARM::VST1q16:
> + case ARM::VST1q32:
> + case ARM::VST1q64:
> + case ARM::VST1q8_UPD:
> + case ARM::VST1q16_UPD:
> + case ARM::VST1q32_UPD:
> + case ARM::VST1q64_UPD:
> + case ARM::VST1d8T:
> + case ARM::VST1d16T:
> + case ARM::VST1d32T:
> + case ARM::VST1d64T:
> + case ARM::VST1d8T_UPD:
> + case ARM::VST1d16T_UPD:
> + case ARM::VST1d32T_UPD:
> + case ARM::VST1d64T_UPD:
> + case ARM::VST1d8Q:
> + case ARM::VST1d16Q:
> + case ARM::VST1d32Q:
> + case ARM::VST1d64Q:
> + case ARM::VST1d8Q_UPD:
> + case ARM::VST1d16Q_UPD:
> + case ARM::VST1d32Q_UPD:
> + case ARM::VST1d64Q_UPD:
> + case ARM::VST2d8:
> + case ARM::VST2d16:
> + case ARM::VST2d32:
> + case ARM::VST2d8_UPD:
> + case ARM::VST2d16_UPD:
> + case ARM::VST2d32_UPD:
> + case ARM::VST2q8:
> + case ARM::VST2q16:
> + case ARM::VST2q32:
> + case ARM::VST2q8_UPD:
> + case ARM::VST2q16_UPD:
> + case ARM::VST2q32_UPD:
> + case ARM::VST3d8:
> + case ARM::VST3d16:
> + case ARM::VST3d32:
> + case ARM::VST3d8_UPD:
> + case ARM::VST3d16_UPD:
> + case ARM::VST3d32_UPD:
> + case ARM::VST4d8:
> + case ARM::VST4d16:
> + case ARM::VST4d32:
> + case ARM::VST4d8_UPD:
> + case ARM::VST4d16_UPD:
> + case ARM::VST4d32_UPD:
> + DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder);
> + break;
> + case ARM::VST2b8:
> + case ARM::VST2b16:
> + case ARM::VST2b32:
> + case ARM::VST2b8_UPD:
> + case ARM::VST2b16_UPD:
> + case ARM::VST2b32_UPD:
> + case ARM::VST3q8:
> + case ARM::VST3q16:
> + case ARM::VST3q32:
> + case ARM::VST3q8_UPD:
> + case ARM::VST3q16_UPD:
> + case ARM::VST3q32_UPD:
> + case ARM::VST4q8:
> + case ARM::VST4q16:
> + case ARM::VST4q32:
> + case ARM::VST4q8_UPD:
> + case ARM::VST4q16_UPD:
> + case ARM::VST4q32_UPD:
> + DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder);
> + break;
> + default:
> + break;
> + }
> +
> + // Third input register
> + switch (Inst.getOpcode()) {
> + case ARM::VST1d8T:
> + case ARM::VST1d16T:
> + case ARM::VST1d32T:
> + case ARM::VST1d64T:
> + case ARM::VST1d8T_UPD:
> + case ARM::VST1d16T_UPD:
> + case ARM::VST1d32T_UPD:
> + case ARM::VST1d64T_UPD:
> + case ARM::VST1d8Q:
> + case ARM::VST1d16Q:
> + case ARM::VST1d32Q:
> + case ARM::VST1d64Q:
> + case ARM::VST1d8Q_UPD:
> + case ARM::VST1d16Q_UPD:
> + case ARM::VST1d32Q_UPD:
> + case ARM::VST1d64Q_UPD:
> + case ARM::VST2q8:
> + case ARM::VST2q16:
> + case ARM::VST2q32:
> + case ARM::VST2q8_UPD:
> + case ARM::VST2q16_UPD:
> + case ARM::VST2q32_UPD:
> + case ARM::VST3d8:
> + case ARM::VST3d16:
> + case ARM::VST3d32:
> + case ARM::VST3d8_UPD:
> + case ARM::VST3d16_UPD:
> + case ARM::VST3d32_UPD:
> + case ARM::VST4d8:
> + case ARM::VST4d16:
> + case ARM::VST4d32:
> + case ARM::VST4d8_UPD:
> + case ARM::VST4d16_UPD:
> + case ARM::VST4d32_UPD:
> + DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder);
> + break;
> + case ARM::VST3q8:
> + case ARM::VST3q16:
> + case ARM::VST3q32:
> + case ARM::VST3q8_UPD:
> + case ARM::VST3q16_UPD:
> + case ARM::VST3q32_UPD:
> + case ARM::VST4q8:
> + case ARM::VST4q16:
> + case ARM::VST4q32:
> + case ARM::VST4q8_UPD:
> + case ARM::VST4q16_UPD:
> + case ARM::VST4q32_UPD:
> + DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder);
> + break;
> + default:
> + break;
> + }
> +
> + // Fourth input register
> + switch (Inst.getOpcode()) {
> + case ARM::VST1d8Q:
> + case ARM::VST1d16Q:
> + case ARM::VST1d32Q:
> + case ARM::VST1d64Q:
> + case ARM::VST1d8Q_UPD:
> + case ARM::VST1d16Q_UPD:
> + case ARM::VST1d32Q_UPD:
> + case ARM::VST1d64Q_UPD:
> + case ARM::VST2q8:
> + case ARM::VST2q16:
> + case ARM::VST2q32:
> + case ARM::VST2q8_UPD:
> + case ARM::VST2q16_UPD:
> + case ARM::VST2q32_UPD:
> + case ARM::VST4d8:
> + case ARM::VST4d16:
> + case ARM::VST4d32:
> + case ARM::VST4d8_UPD:
> + case ARM::VST4d16_UPD:
> + case ARM::VST4d32_UPD:
> + DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder);
> + break;
> + case ARM::VST4q8:
> + case ARM::VST4q16:
> + case ARM::VST4q32:
> + case ARM::VST4q8_UPD:
> + case ARM::VST4q16_UPD:
> + case ARM::VST4q32_UPD:
> + DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder);
> + break;
> + default:
> + break;
> + }
> +
> + return true;
> +}
> +
> +static bool DecodeVLD1DupInstruction(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder) {
> + unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> + Rd |= fieldFromInstruction32(Insn, 22, 1)<< 4;
> + unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> + unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> + unsigned align = fieldFromInstruction32(Insn, 4, 1);
> + unsigned size = fieldFromInstruction32(Insn, 6, 2);
> + unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
> +
> + align *= (1<< size);
> +
> + DecodeDPRRegisterClass(Inst, Rd, Address, Decoder);
> + if (regs == 2) DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder);
> + if (Rm == 0xD) DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
> +
> + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
> + Inst.addOperand(MCOperand::CreateImm(align));
> +
> + if (Rm == 0xD)
> + Inst.addOperand(MCOperand::CreateReg(0));
> + else if (Rm != 0xF)
> + DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
> +
> + return true;
> +}
> +
> +static bool DecodeVLD2DupInstruction(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder) {
> + unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> + Rd |= fieldFromInstruction32(Insn, 22, 1)<< 4;
> + unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> + unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> + unsigned align = fieldFromInstruction32(Insn, 4, 1);
> + unsigned size = 1<< fieldFromInstruction32(Insn, 6, 2);
> + unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
> + align *= 2*size;
> +
> + DecodeDPRRegisterClass(Inst, Rd, Address, Decoder);
> + DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder);
> + if (Rm == 0xD) DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
> +
> + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
> + Inst.addOperand(MCOperand::CreateImm(align));
> +
> + if (Rm == 0xD)
> + Inst.addOperand(MCOperand::CreateReg(0));
> + else if (Rm != 0xF)
> + DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
> +
> + return true;
> +}
> +
> +static bool DecodeVLD3DupInstruction(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder) {
> + unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> + Rd |= fieldFromInstruction32(Insn, 22, 1)<< 4;
> + unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> + unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> + unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
> +
> + DecodeDPRRegisterClass(Inst, Rd, Address, Decoder);
> + DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder);
> + DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder);
> + if (Rm == 0xD) DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
> +
> + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
> + Inst.addOperand(MCOperand::CreateImm(0));
> +
> + if (Rm == 0xD)
> + Inst.addOperand(MCOperand::CreateReg(0));
> + else if (Rm != 0xF)
> + DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
> +
> + return true;
> +}
> +
> +static bool DecodeVLD4DupInstruction(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder) {
> + unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> + Rd |= fieldFromInstruction32(Insn, 22, 1)<< 4;
> + unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> + unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> + unsigned size = fieldFromInstruction32(Insn, 6, 2);
> + unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
> + unsigned align = fieldFromInstruction32(Insn, 4, 1);
> +
> + if (size == 0x3) {
> + size = 4;
> + align = 16;
> + } else {
> + if (size == 2) {
> + size = 1<< size;
> + align *= 8;
> + } else {
> + size = 1<< size;
> + align *= 4*size;
> + }
> + }
> +
> + DecodeDPRRegisterClass(Inst, Rd, Address, Decoder);
> + DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder);
> + DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder);
> + DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder);
> + if (Rm == 0xD) DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
> +
> + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
> + Inst.addOperand(MCOperand::CreateImm(align));
> +
> + if (Rm == 0xD)
> + Inst.addOperand(MCOperand::CreateReg(0));
> + else if (Rm != 0xF)
> + DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
> +
> + return true;
> +}
> +
> +static bool DecodeNEONModImmInstruction(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder) {
> + unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> + Rd |= fieldFromInstruction32(Insn, 22, 1)<< 4;
> + unsigned imm = fieldFromInstruction32(Insn, 0, 4);
> + imm |= fieldFromInstruction32(Insn, 16, 3)<< 4;
> + imm |= fieldFromInstruction32(Insn, 24, 1)<< 7;
> + imm |= fieldFromInstruction32(Insn, 8, 4)<< 8;
> + imm |= fieldFromInstruction32(Insn, 5, 1)<< 12;
> + unsigned Q = fieldFromInstruction32(Insn, 6, 1);
> +
> + if (Q)
> + DecodeQPRRegisterClass(Inst, Rd, Address, Decoder);
> + else
> + DecodeDPRRegisterClass(Inst, Rd, Address, Decoder);
> +
> + Inst.addOperand(MCOperand::CreateImm(imm));
> +
> + switch (Inst.getOpcode()) {
> + case ARM::VORRiv4i16:
> + case ARM::VORRiv2i32:
> + case ARM::VBICiv4i16:
> + case ARM::VBICiv2i32:
> + DecodeDPRRegisterClass(Inst, Rd, Address, Decoder);
> + break;
> + case ARM::VORRiv8i16:
> + case ARM::VORRiv4i32:
> + case ARM::VBICiv8i16:
> + case ARM::VBICiv4i32:
> + DecodeQPRRegisterClass(Inst, Rd, Address, Decoder);
> + break;
> + default:
> + break;
> + }
> +
> +
Extra newline.
> + return true;
> +}
> +
> +static bool DecodeVSHLMaxInstruction(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder) {
> + unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> + Rd |= fieldFromInstruction32(Insn, 22, 1)<< 4;
> + unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> + Rm |= fieldFromInstruction32(Insn, 5, 1)<< 4;
> + unsigned size = fieldFromInstruction32(Insn, 18, 2);
> +
> + DecodeQPRRegisterClass(Inst, Rd, Address, Decoder);
> + DecodeDPRRegisterClass(Inst, Rm, Address, Decoder);
> + Inst.addOperand(MCOperand::CreateImm(8<< size));
> +
> + return true;
> +}
> +
> +static bool DecodeShiftRight8Imm(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> + Inst.addOperand(MCOperand::CreateImm(8 - Val));
> + return true;
> +}
> +
> +static bool DecodeShiftRight16Imm(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> + Inst.addOperand(MCOperand::CreateImm(16 - Val));
> + return true;
> +}
> +
> +static bool DecodeShiftRight32Imm(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> + Inst.addOperand(MCOperand::CreateImm(32 - Val));
> + return true;
> +}
> +
> +static bool DecodeShiftRight64Imm(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> + Inst.addOperand(MCOperand::CreateImm(64 - Val));
> + return true;
> +}
> +
> +static bool DecodeTBLInstruction(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder) {
> + unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> + Rd |= fieldFromInstruction32(Insn, 22, 1)<< 4;
> + unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> + Rn |= fieldFromInstruction32(Insn, 7, 1)<< 4;
> + unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> + Rm |= fieldFromInstruction32(Insn, 5, 1)<< 4;
> + unsigned op = fieldFromInstruction32(Insn, 6, 1);
> + unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
> +
> + DecodeDPRRegisterClass(Inst, Rd, Address, Decoder);
> + if (op) DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); // Writeback
> +
> + for (unsigned i = 0; i< length; ++i)
> + DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder);
> +
> + DecodeDPRRegisterClass(Inst, Rm, Address, Decoder);
> +
> + return true;
> +}
> +
> +static bool DecodeVFPfpImm(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> + // The immediate needs to be a fully instantiated float. However, the
> + // auto-generated decoder is only able to fill in some of the bits
> + // necessary. For instance, the 'b' bit is replicated multiple times,
> + // and is even present in inverted form in one bit. We do a little
> + // binary parsing here to fill in those missing bits, and then
> + // reinterpret it all as a float.
> + union {
> + uint32_t integer;
> + float fp;
> + } fp_conv;
> +
> + fp_conv.integer = Val;
> + uint32_t b = fieldFromInstruction32(Val, 25, 1);
> + fp_conv.integer |= b<< 26;
> + fp_conv.integer |= b<< 27;
> + fp_conv.integer |= b<< 28;
> + fp_conv.integer |= b<< 29;
> + fp_conv.integer |= (~b& 0x1)<< 30;
> +
> + Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp));
> + return true;
> +}
> +
> +static bool DecodeThumbAddSpecialReg(llvm::MCInst&Inst, uint16_t Insn,
> + uint64_t Address, const void *Decoder) {
> + unsigned dst = fieldFromInstruction16(Insn, 8, 3);
> + unsigned imm = fieldFromInstruction16(Insn, 0, 8);
> +
> + DecodetGPRRegisterClass(Inst, dst, Address, Decoder);
> +
> + if (Inst.getOpcode() == ARM::tADR)
> + Inst.addOperand(MCOperand::CreateReg(ARM::PC));
> + else if (Inst.getOpcode() == ARM::tADDrSPi)
> + Inst.addOperand(MCOperand::CreateReg(ARM::SP));
> + else
> + return false;
> +
> + Inst.addOperand(MCOperand::CreateImm(imm));
> + return true;
> +}
> +
> +static bool DecodeThumbBROperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> + Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val<< 1)));
> + return true;
> +}
> +
> +static bool DecodeT2BROperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> + Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
> + return true;
> +}
> +
> +static bool DecodeThumbCmpBROperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> + Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val<< 1)));
> + return true;
> +}
> +
> +static bool DecodeThumbAddrModeRR(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> + unsigned Rn = fieldFromInstruction32(Val, 0, 3);
> + unsigned Rm = fieldFromInstruction32(Val, 3, 3);
> +
> + DecodetGPRRegisterClass(Inst, Rn, Address, Decoder);
> + DecodetGPRRegisterClass(Inst, Rm, Address, Decoder);
> +
> + return true;
> +}
> +
> +static bool DecodeThumbAddrModeIS(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> + unsigned Rn = fieldFromInstruction32(Val, 0, 3);
> + unsigned imm = fieldFromInstruction32(Val, 3, 5);
> +
> + DecodetGPRRegisterClass(Inst, Rn, Address, Decoder);
> + Inst.addOperand(MCOperand::CreateImm(imm));
> +
> + return true;
> +}
> +
> +static bool DecodeThumbAddrModePC(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> + Inst.addOperand(MCOperand::CreateImm(Val<< 2));
> +
> + return true;
> +}
> +
> +static bool DecodeThumbAddrModeSP(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> + Inst.addOperand(MCOperand::CreateReg(ARM::SP));
> + Inst.addOperand(MCOperand::CreateImm(Val<< 2));
> +
> + return true;
> +}
> +
> +static bool DecodeT2AddrModeSOReg(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> + unsigned Rn = fieldFromInstruction32(Val, 6, 4);
> + unsigned Rm = fieldFromInstruction32(Val, 2, 4);
> + unsigned imm = fieldFromInstruction32(Val, 0, 2);
> +
> + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
> + DecoderGPRRegisterClass(Inst, Rm, Address, Decoder);
> + Inst.addOperand(MCOperand::CreateImm(imm));
> +
> + return true;
> +}
> +
> +static bool DecodeT2LoadShift(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder) {
> + if (Inst.getOpcode() != ARM::t2PLDs) {
> + unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
> + DecodeGPRRegisterClass(Inst, Rt, Address, Decoder);
> + }
> +
> + unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> + if (Rn == 0xF) {
> + switch (Inst.getOpcode()) {
> + case ARM::t2LDRBs:
> + Inst.setOpcode(ARM::t2LDRBpci);
> + break;
> + case ARM::t2LDRHs:
> + Inst.setOpcode(ARM::t2LDRHpci);
> + break;
> + case ARM::t2LDRSHs:
> + Inst.setOpcode(ARM::t2LDRSHpci);
> + break;
> + case ARM::t2LDRSBs:
> + Inst.setOpcode(ARM::t2LDRSBpci);
> + break;
> + case ARM::t2PLDs:
> + Inst.setOpcode(ARM::t2PLDi12);
> + Inst.addOperand(MCOperand::CreateReg(ARM::PC));
> + break;
> + default:
> + return false;
> + }
> +
> + int imm = fieldFromInstruction32(Insn, 0, 12);
> + if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
> + Inst.addOperand(MCOperand::CreateImm(imm));
> +
> + return true;
> + }
> +
> + unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
> + addrmode |= fieldFromInstruction32(Insn, 0, 4)<< 2;
> + addrmode |= fieldFromInstruction32(Insn, 16, 4)<< 6;
> + DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder);
> +
> + return true;
> +}
> +
> +static bool DecodeT2Imm8S4(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
Please fix whitespace!
> + int imm = Val& 0xFF;
> + if (!(Val& 0x100)) imm *= -1;
> + Inst.addOperand(MCOperand::CreateImm(imm<< 2));
> +
> + return true;
> +}
> +
> +static bool DecodeT2AddrModeImm8s4(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
Whitespace.
> + unsigned Rn = fieldFromInstruction32(Val, 9, 4);
> + unsigned imm = fieldFromInstruction32(Val, 0, 9);
> +
> + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
> + DecodeT2Imm8S4(Inst, imm, Address, Decoder);
> +
> + return true;
> +}
> +
> +static bool DecodeT2Imm8(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
Whitespace!
> + int imm = Val& 0xFF;
> + if (!(Val& 0x100)) imm *= -1;
> + Inst.addOperand(MCOperand::CreateImm(imm));
> +
> + return true;
> +}
> +
> +
> +static bool DecodeT2AddrModeImm8(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
Spacing.
> + unsigned Rn = fieldFromInstruction32(Val, 9, 4);
> + unsigned imm = fieldFromInstruction32(Val, 0, 9);
> +
> + // Some instructions always use an additive offset.
> + switch (Inst.getOpcode()) {
> + case ARM::t2LDRT:
> + case ARM::t2LDRBT:
> + case ARM::t2LDRHT:
> + case ARM::t2LDRSBT:
> + case ARM::t2LDRSHT:
> + imm |= 0x100;
> + break;
> + default:
> + break;
> + }
> +
> + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
> + DecodeT2Imm8(Inst, imm, Address, Decoder);
> +
> + return true;
> +}
> +
> +
> +static bool DecodeT2AddrModeImm12(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
Spacing.
> + unsigned Rn = fieldFromInstruction32(Val, 13, 4);
> + unsigned imm = fieldFromInstruction32(Val, 0, 12);
> +
> + DecodeGPRRegisterClass(Inst, Rn, Address, Decoder);
> + Inst.addOperand(MCOperand::CreateImm(imm));
> +
> + return true;
> +}
> +
> +
> +static bool DecodeThumbAddSPImm(llvm::MCInst&Inst, uint16_t Insn,
> + uint64_t Address, const void *Decoder) {
Spacing.
> + unsigned imm = fieldFromInstruction16(Insn, 0, 7);
> +
> + Inst.addOperand(MCOperand::CreateReg(ARM::SP));
> + Inst.addOperand(MCOperand::CreateReg(ARM::SP));
> + Inst.addOperand(MCOperand::CreateImm(imm));
> +
> + return true;
> +}
> +
> +static bool DecodeThumbAddSPReg(llvm::MCInst&Inst, uint16_t Insn,
> + uint64_t Address, const void *Decoder) {
Spacing?
> + if (Inst.getOpcode() == ARM::tADDrSP) {
> + unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
> + Rdm |= fieldFromInstruction16(Insn, 7, 1)<< 3;
> +
> + DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder);
> + Inst.addOperand(MCOperand::CreateReg(ARM::SP));
> + DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder);
> + } else if (Inst.getOpcode() == ARM::tADDspr) {
> + unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
> +
> + Inst.addOperand(MCOperand::CreateReg(ARM::SP));
> + Inst.addOperand(MCOperand::CreateReg(ARM::SP));
> + DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
> + }
> +
> + return true;
> +}
> +
> +static bool DecodeThumbCPS(llvm::MCInst&Inst, uint16_t Insn,
> + uint64_t Address, const void *Decoder) {
Spacing!
> + unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
> + unsigned flags = fieldFromInstruction16(Insn, 0, 3);
> +
> + Inst.addOperand(MCOperand::CreateImm(imod));
> + Inst.addOperand(MCOperand::CreateImm(flags));
> +
> + return true;
> +}
> +
> +static bool DecodePostIdxReg(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder) {
whitespace
> + unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> + unsigned add = fieldFromInstruction32(Insn, 4, 1);
> +
> + DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
> + Inst.addOperand(MCOperand::CreateImm(add));
> +
> + return true;
> +}
> +
> +static bool DecodeThumbBLXOffset(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
whitespace
> + Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val<< 1)));
> + return true;
> +}
> +
> +static bool DecodeCoprocessor(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> + if (Val == 0xA || Val == 0xB)
> + return false;
> +
> + Inst.addOperand(MCOperand::CreateImm(Val));
> + return true;
> +}
> +
> +static bool DecodeThumbSRImm(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
whitespace
> + if (Val == 0)
> + Inst.addOperand(MCOperand::CreateImm(32));
> + else
> + Inst.addOperand(MCOperand::CreateImm(Val));
> + return true;
> +}
> +
> +static bool DecodeThumb2BCCInstruction(llvm::MCInst&Inst, unsigned Insn,
> + uint64_t Address, const void *Decoder) {
> + unsigned pred = fieldFromInstruction32(Insn, 22, 4);
> + if (pred == 0xE || pred == 0xF) {
> + unsigned opc = fieldFromInstruction32(Insn, 4, 2);
> + switch (opc) {
> + default:
> + return false;
> + case 0:
> + Inst.setOpcode(ARM::t2DSB);
> + break;
> + case 1:
> + Inst.setOpcode(ARM::t2DMB);
> + break;
> + case 2:
> + Inst.setOpcode(ARM::t2ISB);
> + return true;
> + }
> +
> + unsigned imm = fieldFromInstruction32(Insn, 0, 4);
> + Inst.addOperand(MCOperand::CreateImm(imm));
> + return true;
> + }
> +
> + unsigned brtarget = fieldFromInstruction32(Insn, 0, 11)<< 1;
> + brtarget |= fieldFromInstruction32(Insn, 11, 1)<< 19;
> + brtarget |= fieldFromInstruction32(Insn, 13, 1)<< 18;
> + brtarget |= fieldFromInstruction32(Insn, 16, 6)<< 12;
> + brtarget |= fieldFromInstruction32(Insn, 26, 1)<< 20;
> +
> + DecodeT2BROperand(Inst, brtarget, Address, Decoder);
> + if (!DecodePredicateOperand(Inst, pred, Address, Decoder))
> + return false;
> +
> + return true;
> +}
> +
> +// Decode a shifted immediate operand. These basically consist
> +// of an 8-bit value, and a 4-bit directive that specifies either
> +// a splat operation or a rotation.
> +static bool DecodeT2SOImm(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder) {
> + unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
> + if (ctrl == 0) {
> + unsigned byte = fieldFromInstruction32(Val, 8, 2);
> + unsigned imm = fieldFromInstruction32(Val, 0, 8);
> + switch (byte) {
> + case 0:
> + Inst.addOperand(MCOperand::CreateImm(imm));
> + break;
> + case 1:
> + Inst.addOperand(MCOperand::CreateImm((imm<< 16) | imm));
> + break;
> + case 2:
> + Inst.addOperand(MCOperand::CreateImm((imm<< 24) | (imm<< 8)));
> + break;
> + case 3:
> + Inst.addOperand(MCOperand::CreateImm((imm<< 24) | (imm<< 16) |
> + (imm<< 8) | imm));
> + break;
> + }
> + } else {
> + unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
> + unsigned rot = fieldFromInstruction32(Val, 7, 5);
> + unsigned imm = (unrot>> rot) | (unrot<< ((32-rot)&31));
> + Inst.addOperand(MCOperand::CreateImm(imm));
> + }
> +
> + return true;
> +}
> +
> +static bool DecodeThumbBCCTargetOperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder){
> + Inst.addOperand(MCOperand::CreateImm(Val<< 1));
> + return true;
> +}
> +
> +static bool DecodeThumbBLTargetOperand(llvm::MCInst&Inst, unsigned Val,
> + uint64_t Address, const void *Decoder){
Whitespace.
Nick
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