[llvm-commits] [llvm] r137176 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/Disassembler/ARMDisassembler.cpp test/MC/Disassembler/ARM/invalid-DMB-thumb.txt test/MC/Disassembler/ARM/invalid-DSB-arm.txt test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt
Owen Anderson
resistor at mac.com
Tue Aug 9 16:25:42 PDT 2011
Author: resistor
Date: Tue Aug 9 18:25:42 2011
New Revision: 137176
URL: http://llvm.org/viewvc/llvm-project?rev=137176&view=rev
Log:
Tighten operand checking on memory barrier instructions.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
llvm/trunk/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-DSB-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=137176&r1=137175&r2=137176&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Aug 9 18:25:42 2011
@@ -3814,6 +3814,7 @@
def memb_opt : Operand<i32> {
let PrintMethod = "printMemBOption";
let ParserMatchClass = MemBarrierOptOperand;
+ let DecoderMethod = "DecodeMemBarrierOption";
}
// memory barriers protect the atomic sequences
Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=137176&r1=137175&r2=137176&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Tue Aug 9 18:25:42 2011
@@ -131,6 +131,8 @@
uint64_t Address, const void *Decoder);
static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
+static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder);
static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
@@ -2268,8 +2270,7 @@
}
unsigned imm = fieldFromInstruction32(Insn, 0, 4);
- Inst.addOperand(MCOperand::CreateImm(imm));
- return true;
+ return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
}
unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
@@ -2347,3 +2348,24 @@
return true;
}
+
+static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
+ uint64_t Address, const void *Decoder) {
+ switch (Val) {
+ default:
+ return false;
+ case 0xF: // SY
+ case 0xE: // ST
+ case 0xB: // ISH
+ case 0xA: // ISHST
+ case 0x7: // NSH
+ case 0x6: // NSHST
+ case 0x3: // OSH
+ case 0x2: // OSHST
+ break;
+ }
+
+ Inst.addOperand(MCOperand::CreateImm(Val));
+ return true;
+}
+
Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt?rev=137176&r1=137175&r2=137176&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt Tue Aug 9 18:25:42 2011
@@ -1,12 +1,11 @@
# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding}
-# XFAIL: *
# Opcode=1908 Name=t2DMB Format=ARM_FORMAT_THUMBFRM(25)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 1| 0: 0: 1: 1| 1: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 1: 0: 1| 0: 0: 0: 1|
# -------------------------------------------------------------------------------------------------
-#
+#
# Inst{3-0} encodes the option: SY, ST, ISH, ISHST, NSH, NSHST, OSH, OSHST.
# Reject invalid encodings.
#
Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-DSB-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-DSB-arm.txt?rev=137176&r1=137175&r2=137176&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-DSB-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-DSB-arm.txt Tue Aug 9 18:25:42 2011
@@ -1,12 +1,11 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
-# XFAIL: *
# Opcode=102 Name=DSB Format=ARM_FORMAT_MISCFRM(26)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 1| 0: 1: 0: 1| 0: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 0: 0|
# -------------------------------------------------------------------------------------------------
-#
+#
# Inst{3-0} encodes the option: SY, ST, ISH, ISHST, NSH, NSHST, OSH, OSHST.
# Reject invalid encodings.
#
Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt?rev=137176&r1=137175&r2=137176&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt Tue Aug 9 18:25:42 2011
@@ -1,12 +1,11 @@
# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding}
-# XFAIL: *
# Opcode=1894 Name=t2Bcc Format=ARM_FORMAT_THUMBFRM(25)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 1| 0: 1: 1: 1| 1: 0: 1: 0| 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 1: 1| 0: 1: 0: 0| 0: 1: 0: 0|
# -------------------------------------------------------------------------------------------------
-#
+#
# A8.6.16 B
# if cond<3:1> == '111' then SEE "Related Encodings"
0xaf 0xf7 0x44 0x8b
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