[llvm-commits] [llvm] r137172 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/Disassembler/ARMDisassembler.cpp test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt

[Owen Anderson]

Author: resistor
Date: Tue Aug  9 18:05:39 2011
New Revision: 137172

URL: http://llvm.org/viewvc/llvm-project?rev=137172&view=rev
Log:
Tighten operand checking on CPS instructions.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt
    llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=137172&r1=137171&r2=137172&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Aug  9 18:05:39 2011
@@ -1390,6 +1390,7 @@
   let Inst{4-0}   = mode;
 }
 
+let DecoderMethod = "DecodeCPSInstruction" in {
 let M = 1 in
   def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
                   "$imod\t$iflags, $mode">;
@@ -1398,6 +1399,7 @@
 
 let imod = 0, iflags = 0, M = 1 in
   def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
+}
 
 // Preload signals the memory system of possible future data/instruction access.
 // These are for disassembly only.

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=137172&r1=137171&r2=137172&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Tue Aug  9 18:05:39 2011
@@ -83,6 +83,8 @@
                                                   const void *Decoder);
 static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
+static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
+                               uint64_t Address, const void *Decoder);
 static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
 static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
@@ -1139,6 +1141,9 @@
   unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
   unsigned mode = fieldFromInstruction32(Insn, 0, 5);
 
+  // imod == '01' --> UNPREDICTABLE
+  if (imod == 1) return false;
+
   if (M && mode && imod && iflags) {
     Inst.setOpcode(ARM::CPS3p);
     Inst.addOperand(MCOperand::CreateImm(imod));

Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt?rev=137172&r1=137171&r2=137172&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt Tue Aug  9 18:05:39 2011
@@ -1,5 +1,4 @@
 # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
-# XFAIL: *
 
 # invalid imod value (0b01)
 0xc0 0x67 0x4 0xf1

Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt?rev=137172&r1=137171&r2=137172&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt Tue Aug  9 18:05:39 2011
@@ -1,5 +1,4 @@
 # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
-# XFAIL: *
 
 # invalid (imod, M, iflags) combination
 0x93 0x1c 0x02 0xf1