[llvm-commits] [llvm] r136623 - in /llvm/trunk: lib/Target/XCore/XCoreISelLowering.cpp test/CodeGen/XCore/2011-08-01-VarargsBug.ll

[Richard Osborne]

Author: friedgold
Date: Mon Aug  1 11:45:59 2011
New Revision: 136623

URL: http://llvm.org/viewvc/llvm-project?rev=136623&view=rev
Log:
Fix crash with varargs function with no named parameters.

Added:
    llvm/trunk/test/CodeGen/XCore/2011-08-01-VarargsBug.ll
Modified:
    llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp

Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=136623&r1=136622&r2=136623&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Mon Aug  1 11:45:59 2011
@@ -1148,10 +1148,10 @@
       int offset = 0;
       // Save remaining registers, storing higher register numbers at a higher
       // address
-      for (unsigned i = array_lengthof(ArgRegs) - 1; i >= FirstVAReg; --i) {
+      for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) {
         // Create a stack slot
         int FI = MFI->CreateFixedObject(4, offset, true);
-        if (i == FirstVAReg) {
+        if (i == (int)FirstVAReg) {
           XFI->setVarArgsFrameIndex(FI);
         }
         offset -= StackSlotSize;

Added: llvm/trunk/test/CodeGen/XCore/2011-08-01-VarargsBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/XCore/2011-08-01-VarargsBug.ll?rev=136623&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/XCore/2011-08-01-VarargsBug.ll (added)
+++ llvm/trunk/test/CodeGen/XCore/2011-08-01-VarargsBug.ll Mon Aug  1 11:45:59 2011
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=xcore | FileCheck %s
+define void @_Z1fz(...) {
+entry:
+; CHECK: _Z1fz:
+; CHECK: extsp 3
+; CHECK: stw r[[REG:[0-3]{1,1}]]
+; CHECK: , sp{{\[}}[[REG]]{{\]}}
+; CHECK: stw r[[REG:[0-3]{1,1}]]
+; CHECK: , sp{{\[}}[[REG]]{{\]}}
+; CHECK: stw r[[REG:[0-3]{1,1}]]
+; CHECK: , sp{{\[}}[[REG]]{{\]}}
+; CHECK: stw r[[REG:[0-3]{1,1}]]
+; CHECK: , sp{{\[}}[[REG]]{{\]}}
+; CHECK: ldaw sp, sp[3]
+; CHECK: retsp 0
+  ret void
+}