[llvm-commits] [llvm] r136548 - in /llvm/trunk: lib/CodeGen/MachineVerifier.cpp lib/CodeGen/RegisterScavenging.cpp test/CodeGen/X86/vector.ll

[Jakob Stoklund Olesen]

Author: stoklund
Date: Fri Jul 29 19:57:25 2011
New Revision: 136548

URL: http://llvm.org/viewvc/llvm-project?rev=136548&view=rev
Log:
Revert "Don't check liveness of unallocatable registers."

The ARM target depends on CPSR liveness being tracked after register
allocation.

Modified:
    llvm/trunk/lib/CodeGen/MachineVerifier.cpp
    llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
    llvm/trunk/test/CodeGen/X86/vector.ll

Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=136548&r1=136547&r2=136548&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Fri Jul 29 19:57:25 2011
@@ -664,15 +664,8 @@
       // Use of a dead register.
       if (!regsLive.count(Reg)) {
         if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
-          // Reserved registers may be used even when 'dead', but allocatable
-          // registers can't.
-          // We track the liveness of unreserved, unallocatable registers while
-          // the machine function is still in SSA form. That lets us check for
-          // bad EFLAGS uses. After register allocation, the unallocatable
-          // registers are probably quite wrong. For example, the x87 ST0-ST7
-          // registers don't track liveness at all.
-          if (!isReserved(Reg) &&
-              (MRI->isSSA() || TRI->isInAllocatableClass(Reg)))
+          // Reserved registers may be used even when 'dead'.
+          if (!isReserved(Reg))
             report("Using an undefined physical register", MO, MONum);
         } else {
           BBInfo &MInfo = MBBInfoMap[MI->getParent()];

Modified: llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterScavenging.cpp?rev=136548&r1=136547&r2=136548&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterScavenging.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Fri Jul 29 19:57:25 2011
@@ -157,7 +157,7 @@
     if (!MO.isReg())
       continue;
     unsigned Reg = MO.getReg();
-    if (!Reg || isReserved(Reg) || !TRI->isInAllocatableClass(Reg))
+    if (!Reg || isReserved(Reg))
       continue;
 
     if (MO.isUse()) {
@@ -184,7 +184,7 @@
     if (!MO.isReg())
       continue;
     unsigned Reg = MO.getReg();
-    if (!Reg || isReserved(Reg) || !TRI->isInAllocatableClass(Reg))
+    if (!Reg || isReserved(Reg))
       continue;
     if (MO.isUse()) {
       if (MO.isUndef())

Modified: llvm/trunk/test/CodeGen/X86/vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector.ll?rev=136548&r1=136547&r2=136548&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vector.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vector.ll Fri Jul 29 19:57:25 2011
@@ -1,6 +1,6 @@
 ; Test that vectors are scalarized/lowered correctly.
 ; RUN: llc < %s -march=x86 -mcpu=i386 > %t
-; RUN: llc < %s -march=x86 -mcpu=yonah -verify-machineinstrs >> %t
+; RUN: llc < %s -march=x86 -mcpu=yonah >> %t
 
 %d8 = type <8 x double>
 %f1 = type <1 x float>