[llvm-commits] [llvm] r136541 - in /llvm/trunk: lib/CodeGen/MachineVerifier.cpp lib/CodeGen/RegisterScavenging.cpp test/CodeGen/X86/vector.ll

Jakob Stoklund Olesen stoklund at 2pi.dk
Fri Jul 29 16:36:21 PDT 2011


Author: stoklund
Date: Fri Jul 29 18:36:21 2011
New Revision: 136541

URL: http://llvm.org/viewvc/llvm-project?rev=136541&view=rev
Log:
Don't check liveness of unallocatable registers.

This includes registers like EFLAGS and ST0-ST7. We don't check for
liveness issues in the verifier and scavenger because registers will
never be allocated from these classes.

While in SSA form, we do care about the liveness of unallocatable
unreserved registers. Liveness of EFLAGS and ST0 neds to be correct for
MachineDCE and MachineSinking.

Modified:
    llvm/trunk/lib/CodeGen/MachineVerifier.cpp
    llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
    llvm/trunk/test/CodeGen/X86/vector.ll

Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=136541&r1=136540&r2=136541&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Fri Jul 29 18:36:21 2011
@@ -664,8 +664,15 @@
       // Use of a dead register.
       if (!regsLive.count(Reg)) {
         if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
-          // Reserved registers may be used even when 'dead'.
-          if (!isReserved(Reg))
+          // Reserved registers may be used even when 'dead', but allocatable
+          // registers can't.
+          // We track the liveness of unreserved, unallocatable registers while
+          // the machine function is still in SSA form. That lets us check for
+          // bad EFLAGS uses. After register allocation, the unallocatable
+          // registers are probably quite wrong. For example, the x87 ST0-ST7
+          // registers don't track liveness at all.
+          if (!isReserved(Reg) &&
+              (MRI->isSSA() || TRI->isInAllocatableClass(Reg)))
             report("Using an undefined physical register", MO, MONum);
         } else {
           BBInfo &MInfo = MBBInfoMap[MI->getParent()];

Modified: llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterScavenging.cpp?rev=136541&r1=136540&r2=136541&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterScavenging.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Fri Jul 29 18:36:21 2011
@@ -157,7 +157,7 @@
     if (!MO.isReg())
       continue;
     unsigned Reg = MO.getReg();
-    if (!Reg || isReserved(Reg))
+    if (!Reg || isReserved(Reg) || !TRI->isInAllocatableClass(Reg))
       continue;
 
     if (MO.isUse()) {
@@ -184,7 +184,7 @@
     if (!MO.isReg())
       continue;
     unsigned Reg = MO.getReg();
-    if (!Reg || isReserved(Reg))
+    if (!Reg || isReserved(Reg) || !TRI->isInAllocatableClass(Reg))
       continue;
     if (MO.isUse()) {
       if (MO.isUndef())

Modified: llvm/trunk/test/CodeGen/X86/vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector.ll?rev=136541&r1=136540&r2=136541&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vector.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vector.ll Fri Jul 29 18:36:21 2011
@@ -1,6 +1,6 @@
 ; Test that vectors are scalarized/lowered correctly.
 ; RUN: llc < %s -march=x86 -mcpu=i386 > %t
-; RUN: llc < %s -march=x86 -mcpu=yonah >> %t
+; RUN: llc < %s -march=x86 -mcpu=yonah -verify-machineinstrs >> %t
 
 %d8 = type <8 x double>
 %f1 = type <1 x float>





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