[llvm-commits] [llvm] r136523 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/inlineasm3.ll

[Eric Christopher]

Author: echristo
Date: Fri Jul 29 16:18:58 2011
New Revision: 136523

URL: http://llvm.org/viewvc/llvm-project?rev=136523&view=rev
Log:
Add support for the 'Q' constraint.

Fixes rdar://9866494

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/test/CodeGen/ARM/inlineasm3.ll

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=136523&r1=136522&r2=136523&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Jul 29 16:18:58 2011
@@ -7596,6 +7596,9 @@
     case 'x': return C_RegisterClass;
     case 't': return C_RegisterClass;
     case 'j': return C_Other; // Constant for movw.
+      // An address with a single base register. Due to the way we
+      // currently handle addresses it is the same as an 'r' memory constraint.
+    case 'Q': return C_Memory;
     }
   } else if (Constraint.size() == 2) {
     switch (Constraint[0]) {

Modified: llvm/trunk/test/CodeGen/ARM/inlineasm3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/inlineasm3.ll?rev=136523&r1=136522&r2=136523&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/inlineasm3.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/inlineasm3.ll Fri Jul 29 16:18:58 2011
@@ -98,3 +98,15 @@
   %0 = tail call i32 asm "movw $0, $1", "=r,j"(i32 27182) nounwind
   ret i32 %0
 }
+
+; Radar 9866494
+
+define void @t10(i8* %f, i32 %g) nounwind {
+entry:
+; CHECK: t10
+; CHECK: str r1, [r0]
+  %f.addr = alloca i8*, align 4
+  store i8* %f, i8** %f.addr, align 4
+  call void asm "str $1, $0", "=*Q,r"(i8** %f.addr, i32 %g) nounwind
+  ret void
+}