[llvm-commits] [llvm] r136292 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp lib/Target/X86/AsmParser/X86AsmParser.cpp lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp test/MC/X86/3DNow.s test/MC/X86/x86-32-coverage.s test/MC/X86/x86_errors.s utils/TableGen/RegisterInfoEmitter.cpp
Evan Cheng
evan.cheng at apple.com
Wed Jul 27 16:22:03 PDT 2011
Author: evancheng
Date: Wed Jul 27 18:22:03 2011
New Revision: 136292
URL: http://llvm.org/viewvc/llvm-project?rev=136292&view=rev
Log:
Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.
This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.
rdar://8204588
Modified:
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
llvm/trunk/test/MC/X86/3DNow.s
llvm/trunk/test/MC/X86/x86-32-coverage.s
llvm/trunk/test/MC/X86/x86_errors.s
llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=136292&r1=136291&r2=136292&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Jul 27 18:22:03 2011
@@ -161,11 +161,6 @@
};
} // end anonymous namespace
-namespace llvm {
- // FIXME: TableGen this?
- extern MCRegisterClass ARMMCRegisterClasses[]; // In ARMGenRegisterInfo.inc.
-}
-
namespace {
/// ARMOperand - Instances of this class represent a parsed ARM machine
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=136292&r1=136291&r2=136292&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Wed Jul 27 18:22:03 2011
@@ -1152,11 +1152,6 @@
return msb;
}
-namespace llvm {
- // FIXME: TableGen this?
- extern MCRegisterClass ARMMCRegisterClasses[]; // In ARMGenRegisterInfo.inc.
-}
-
unsigned ARMMCCodeEmitter::
getRegisterListOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const {
Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=136292&r1=136291&r2=136292&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Wed Jul 27 18:22:03 2011
@@ -13,6 +13,7 @@
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCParser/MCAsmLexer.h"
#include "llvm/MC/MCParser/MCAsmParser.h"
@@ -400,19 +401,25 @@
if (Tok.isNot(AsmToken::Identifier))
return Error(Tok.getLoc(), "invalid register name");
- // FIXME: Validate register for the current architecture; we have to do
- // validation later, so maybe there is no need for this here.
RegNo = MatchRegisterName(Tok.getString());
// If the match failed, try the register name as lowercase.
if (RegNo == 0)
RegNo = MatchRegisterName(LowercaseString(Tok.getString()));
- // FIXME: This should be done using Requires<In32BitMode> and
- // Requires<In64BitMode> so "eiz" usage in 64-bit instructions
- // can be also checked.
- if (RegNo == X86::RIZ && !is64BitMode())
- return Error(Tok.getLoc(), "riz register in 64-bit mode only");
+ if (!is64BitMode()) {
+ // FIXME: This should be done using Requires<In32BitMode> and
+ // Requires<In64BitMode> so "eiz" usage in 64-bit instructions can be also
+ // checked.
+ // FIXME: Check AH, CH, DH, BH cannot be used in an instruction requiring a
+ // REX prefix.
+ if (RegNo == X86::RIZ ||
+ X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||
+ X86II::isX86_64NonExtLowByteReg(RegNo) ||
+ X86II::isX86_64ExtendedReg(RegNo))
+ return Error(Tok.getLoc(), "register %"
+ + Tok.getString() + " is only available in 64-bit mode");
+ }
// Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) {
@@ -490,7 +497,7 @@
SMLoc Start, End;
if (ParseRegister(RegNo, Start, End)) return 0;
if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
- Error(Start, "eiz and riz can only be used as index registers");
+ Error(Start, "%eiz and %riz can only be used as index registers");
return 0;
}
Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp?rev=136292&r1=136291&r2=136292&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp Wed Jul 27 18:22:03 2011
@@ -155,11 +155,6 @@
return MCFixup::getKindForSize(Size, isPCRel);
}
-namespace llvm {
- // FIXME: TableGen this?
- extern MCRegisterClass X86MCRegisterClasses[]; // In X86GenRegisterInfo.inc.
-}
-
/// Is32BitMemOperand - Return true if the specified instruction with a memory
/// operand should emit the 0x67 prefix byte in 64-bit mode due to a 32-bit
/// memory operand. Op specifies the operand # of the memoperand.
Modified: llvm/trunk/test/MC/X86/3DNow.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/3DNow.s?rev=136292&r1=136291&r2=136292&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/3DNow.s (original)
+++ llvm/trunk/test/MC/X86/3DNow.s Wed Jul 27 18:22:03 2011
@@ -1,18 +1,18 @@
-// RUN: llvm-mc -triple i386-unknown-unknown --show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
// PR8283
// CHECK: pavgusb %mm2, %mm1 # encoding: [0x0f,0x0f,0xca,0xbf]
pavgusb %mm2, %mm1
-// CHECK: pavgusb 9(%esi,%edx), %mm3 # encoding: [0x0f,0x0f,0x5c,0x16,0x09,0xbf]
+// CHECK: pavgusb 9(%esi,%edx), %mm3 # encoding: [0x67,0x0f,0x0f,0x5c,0x16,0x09,0xbf]
pavgusb 9(%esi,%edx), %mm3
// CHECK: pf2id %mm2, %mm1 # encoding: [0x0f,0x0f,0xca,0x1d]
pf2id %mm2, %mm1
-// CHECK: pf2id 9(%esi,%edx), %mm3 # encoding: [0x0f,0x0f,0x5c,0x16,0x09,0x1d]
+// CHECK: pf2id 9(%esi,%edx), %mm3 # encoding: [0x67,0x0f,0x0f,0x5c,0x16,0x09,0x1d]
pf2id 9(%esi,%edx), %mm3
// CHECK: pfacc %mm2, %mm1 # encoding: [0x0f,0x0f,0xca,0xae]
Modified: llvm/trunk/test/MC/X86/x86-32-coverage.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-32-coverage.s?rev=136292&r1=136291&r2=136292&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-32-coverage.s (original)
+++ llvm/trunk/test/MC/X86/x86-32-coverage.s Wed Jul 27 18:22:03 2011
@@ -19571,8 +19571,8 @@
// CHECK: aeskeygenassist $125, (%edx,%eax,4), %xmm2
aeskeygenassist $125, (%edx,%eax,4), %xmm2
-// CHECK: blendvps (%rax), %xmm1 # encoding: [0x66,0x0f,0x38,0x14,0x08]
- blendvps (%rax), %xmm1
+// CHECK: blendvps (%eax), %xmm1 # encoding: [0x66,0x0f,0x38,0x14,0x08]
+ blendvps (%eax), %xmm1
// CHECK: blendvps %xmm2, %xmm1 # encoding: [0x66,0x0f,0x38,0x14,0xca]
blendvps %xmm2, %xmm1
Modified: llvm/trunk/test/MC/X86/x86_errors.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86_errors.s?rev=136292&r1=136291&r2=136292&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86_errors.s (original)
+++ llvm/trunk/test/MC/X86/x86_errors.s Wed Jul 27 18:22:03 2011
@@ -1,5 +1,12 @@
// RUN: not llvm-mc -triple x86_64-unknown-unknown %s 2> %t.err
-// RUN: FileCheck < %t.err %s
+// RUN: FileCheck --check-prefix=64 < %t.err %s
-// CHECK: error: ambiguous instructions require an explicit suffix (could be 'cmpb', 'cmpw', 'cmpl', or 'cmpq')
+// RUN: not llvm-mc -triple i386-unknown-unknown %s 2> %t.err
+// RUN: FileCheck --check-prefix=32 < %t.err %s
+// rdar://8204588
+
+// 64: error: ambiguous instructions require an explicit suffix (could be 'cmpb', 'cmpw', 'cmpl', or 'cmpq')
cmp $0, 0(%eax)
+
+// 32: error: register %rax is only available in 64-bit mode
+addl $0, 0(%rax)
Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=136292&r1=136291&r2=136292&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Wed Jul 27 18:22:03 2011
@@ -40,6 +40,9 @@
OS << "namespace llvm {\n\n";
+ OS << "class MCRegisterClass;\n"
+ << "extern MCRegisterClass " << Namespace << "MCRegisterClasses[];\n\n";
+
if (!Namespace.empty())
OS << "namespace " << Namespace << " {\n";
OS << "enum {\n NoRegister,\n";
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