[llvm-commits] [llvm] r136285 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td test/MC/ARM/basic-arm-instructions.s

[Jim Grosbach]

Author: grosbach
Date: Wed Jul 27 17:34:17 2011
New Revision: 136285

URL: http://llvm.org/viewvc/llvm-project?rev=136285&view=rev
Log:
ARM assembly parsing and encoding support for USAT and USAT16.

Use range checked immediate operands for instructions. Add tests.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/test/MC/ARM/basic-arm-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=136285&r1=136284&r2=136285&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Jul 27 17:34:17 2011
@@ -2785,7 +2785,7 @@
   let Inst{3-0} = Rn;
 }
 
-def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn, shift_imm:$sh),
+def USAT : AI<(outs GPR:$Rd), (ins imm0_31:$sat_imm, GPR:$Rn, shift_imm:$sh),
               SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
   bits<4> Rd;
   bits<5> sat_imm;
@@ -2800,7 +2800,7 @@
   let Inst{3-0} = Rn;
 }
 
-def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
+def USAT16 : AI<(outs GPR:$Rd), (ins imm0_15:$sat_imm, GPR:$a), SatFrm,
                 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
                 [/* For disassembly only; pattern left blank */]> {
   bits<4> Rd;
@@ -4364,9 +4364,11 @@
                 (RSCrsr GPR:$Rdn, GPR:$Rdn, so_reg_reg:$shift, pred:$p,
                         cc_out:$s)>, Requires<[IsARM]>;
 
-// SSAT optional shift operand.
+// SSAT/USAT optional shift operand.
 def : InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
                 (SSAT GPR:$Rd, imm1_32:$sat_imm, GPR:$Rn, 0, pred:$p)>;
+def : InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
+                (USAT GPR:$Rd, imm0_31:$sat_imm, GPR:$Rn, 0, pred:$p)>;
 
 
 // Extend instruction optional rotate operand.

Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=136285&r1=136284&r2=136285&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Jul 27 17:34:17 2011
@@ -2158,3 +2158,29 @@
 @ CHECK: usad8le	r4, r6, r9      @ encoding: [0x16,0xf9,0x84,0xd7]
 @ CHECK: usada8	r1, r5, r3, r7          @ encoding: [0x15,0x73,0x81,0xe7]
 @ CHECK: usada8gt	r3, r2, r5, r1  @ encoding: [0x12,0x15,0x83,0xc7]
+
+
+ at ------------------------------------------------------------------------------
+@ USAT
+ at ------------------------------------------------------------------------------
+
+	usat	r8, #1, r10
+	usat	r8, #4, r10, lsl #0
+	usat	r8, #5, r10, lsl #31
+	usat	r8, #31, r10, asr #32
+	usat	r8, #16, r10, asr #1
+
+@ CHECK: usat	r8, #1, r10             @ encoding: [0x1a,0x80,0xe1,0xe6]
+@ CHECK: usat	r8, #4, r10             @ encoding: [0x1a,0x80,0xe4,0xe6]
+@ CHECK: usat	r8, #5, r10, lsl #31    @ encoding: [0x9a,0x8f,0xe5,0xe6]
+@ CHECK: usat	r8, #31, r10, asr #32   @ encoding: [0x5a,0x80,0xff,0xe6]
+@ CHECK: usat	r8, #16, r10, asr #1    @ encoding: [0xda,0x80,0xf0,0xe6]
+
+ at ------------------------------------------------------------------------------
+@ USAT16
+ at ------------------------------------------------------------------------------
+	usat16	r2, #2, r7
+	usat16	r3, #15, r5
+
+@ CHECK: usat16	r2, #2, r7              @ encoding: [0x32,0x2f,0xe2,0xe6]
+@ CHECK: usat16	r3, #15, r5             @ encoding: [0x33,0x3f,0xef,0xe6]