[llvm-commits] [llvm] r136255 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td test/MC/ARM/arm_addrmode2.s
Owen Anderson
resistor at mac.com
Wed Jul 27 13:29:48 PDT 2011
Author: resistor
Date: Wed Jul 27 15:29:48 2011
New Revision: 136255
URL: http://llvm.org/viewvc/llvm-project?rev=136255&view=rev
Log:
Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/test/MC/ARM/arm_addrmode2.s
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=136255&r1=136254&r2=136255&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Jul 27 15:29:48 2011
@@ -2090,22 +2090,50 @@
// STRT, STRBT, and STRHT are for disassembly only.
-def STRT : AI2stridxT<0, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
+def STRTr : AI2stridxT<0, 0, (outs GPR:$Rn_wb),
+ (ins GPR:$Rt, ldst_so_reg:$addr),
IndexModePost, StFrm, IIC_iStore_ru,
"strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
[/* For disassembly only; pattern left blank */]> {
+ let Inst{25} = 1;
+ let Inst{21} = 1; // overwrite
+ let Inst{4} = 0;
+ let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
+}
+
+def STRTi : AI2stridxT<0, 0, (outs GPR:$Rn_wb),
+ (ins GPR:$Rt, addrmode_imm12:$addr),
+ IndexModePost, StFrm, IIC_iStore_ru,
+ "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
+ [/* For disassembly only; pattern left blank */]> {
+ let Inst{25} = 0;
+ let Inst{21} = 1; // overwrite
+ let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
+}
+
+
+def STRBTr : AI2stridxT<1, 0, (outs GPR:$Rn_wb),
+ (ins GPR:$Rt, ldst_so_reg:$addr),
+ IndexModePost, StFrm, IIC_iStore_bh_ru,
+ "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
+ [/* For disassembly only; pattern left blank */]> {
+ let Inst{25} = 1;
let Inst{21} = 1; // overwrite
+ let Inst{4} = 0;
let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
}
-def STRBT : AI2stridxT<1, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
+def STRBTi : AI2stridxT<1, 0, (outs GPR:$Rn_wb),
+ (ins GPR:$Rt, addrmode_imm12:$addr),
IndexModePost, StFrm, IIC_iStore_bh_ru,
"strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
[/* For disassembly only; pattern left blank */]> {
+ let Inst{25} = 0;
let Inst{21} = 1; // overwrite
let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
}
+
def STRHT: AI3sthpo<(outs GPR:$base_wb), (ins GPR:$Rt, addrmode3:$addr),
StMiscFrm, IIC_iStore_bh_ru,
"strht", "\t$Rt, $addr", "$addr.base = $base_wb",
Modified: llvm/trunk/test/MC/ARM/arm_addrmode2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_addrmode2.s?rev=136255&r1=136254&r2=136255&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/arm_addrmode2.s (original)
+++ llvm/trunk/test/MC/ARM/arm_addrmode2.s Wed Jul 27 15:29:48 2011
@@ -1,4 +1,5 @@
@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s
+@ XFAIL: *
@ Post-indexed
@ CHECK: ldrt r1, [r0], r2 @ encoding: [0x02,0x10,0xb0,0xe6]
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