[llvm-commits] [llvm] r136013 - /llvm/trunk/test/MC/ARM/basic-arm-instructions.s

[Jim Grosbach]

Author: grosbach
Date: Mon Jul 25 18:32:14 2011
New Revision: 136013

URL: http://llvm.org/viewvc/llvm-project?rev=136013&view=rev
Log:
ARM assembly parsing and encoding for SSAX, SSUB16 and SSUB8.

Modified:
    llvm/trunk/test/MC/ARM/basic-arm-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=136013&r1=136012&r2=136013&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Mon Jul 25 18:32:14 2011
@@ -1643,6 +1643,29 @@
 
 
 @------------------------------------------------------------------------------
+@ SSAX
+ at ------------------------------------------------------------------------------
+        ssax r2, r3, r4
+        ssaxlt r2, r3, r4
+
+@ CHECK: ssax	r2, r3, r4              @ encoding: [0x54,0x2f,0x13,0xe6]
+@ CHECK: ssaxlt	r2, r3, r4              @ encoding: [0x54,0x2f,0x13,0xb6]
+
+ at ------------------------------------------------------------------------------
+@ SSUB16/SSUB8
+ at ------------------------------------------------------------------------------
+        ssub16 r1, r0, r6
+        ssub16ne r5, r3, r2
+        ssub8 r9, r2, r4
+        ssub8eq r5, r1, r2
+
+@ CHECK: ssub16	r1, r0, r6              @ encoding: [0x76,0x1f,0x10,0xe6]
+@ CHECK: ssub16ne	r5, r3, r2      @ encoding: [0x72,0x5f,0x13,0x16]
+@ CHECK: ssub8	r9, r2, r4              @ encoding: [0xf4,0x9f,0x12,0xe6]
+@ CHECK: ssub8eq	r5, r1, r2      @ encoding: [0xf2,0x5f,0x11,0x06]
+
+
+ at ------------------------------------------------------------------------------
 @ STM*
 @------------------------------------------------------------------------------
         stm       r2, {r1,r3-r6,sp}