[llvm-commits] [llvm] r135362 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

[Duncan Sands]

Hi Nadav,

> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Sun Jul 17 14:05:00 2011
> @@ -2775,7 +2775,6 @@
>
>
>   SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
> -
>     ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
>     EVT VT = N->getValueType(0);
>     DebugLoc dl = N->getDebugLoc();
> @@ -2838,13 +2837,12 @@
>     EVT NOutVTElem = NOutVT.getVectorElementType();
>
>     DebugLoc dl = N->getDebugLoc();
> -
> -  SDValue ConvertedVector = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
> -                                        N->getOperand(0));
> +  SDValue V0 = GetPromotedInteger(N->getOperand(0));
> +  SDValue ConvertedVector = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, V0);
>
>     SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
>       NOutVTElem, N->getOperand(1));
> -  return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,NOutVT,
> +  return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
>       ConvertedVector, ConvElem, N->getOperand(2));
>   }

since the input and output vector types are the same, as the output type is
promoted you know that the input type is promoted to the same type.  Thus the
ANY_EXTEND of V0 must be a no-op and can be removed.

Ciao, Duncan.