[llvm-commits] [llvm] r135797 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/basic-arm-instructions.s

[Jim Grosbach]

Author: grosbach
Date: Fri Jul 22 15:18:21 2011
New Revision: 135797

URL: http://llvm.org/viewvc/llvm-project?rev=135797&view=rev
Log:
ARM assembly parsing and encoding of SMLAL instruction.

Fix parsing of carry-setting variant SMLALS and add tests.

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/basic-arm-instructions.s

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=135797&r1=135796&r2=135797&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Jul 22 15:18:21 2011
@@ -2153,7 +2153,7 @@
   // First, split out any predication code. Ignore mnemonics we know aren't
   // predicated but do have a carry-set and so weren't caught above.
   if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
-      Mnemonic != "muls") {
+      Mnemonic != "muls" && Mnemonic != "smlals") {
     unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
       .Case("eq", ARMCC::EQ)
       .Case("ne", ARMCC::NE)

Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=135797&r1=135796&r2=135797&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Fri Jul 22 15:18:21 2011
@@ -1404,6 +1404,20 @@
 
 
 @------------------------------------------------------------------------------
+@ SMLAD/SMLADX
+ at ------------------------------------------------------------------------------
+        smlal r2, r3, r5, r8
+        smlals r2, r3, r5, r8
+        smlaleq r2, r3, r5, r8
+        smlalshi r2, r3, r5, r8
+
+@ CHECK: smlal	r2, r3, r5, r8          @ encoding: [0x95,0x28,0xe3,0xe0]
+@ CHECK: smlals	r2, r3, r5, r8          @ encoding: [0x95,0x28,0xf3,0xe0]
+@ CHECK: smlaleq	r2, r3, r5, r8  @ encoding: [0x95,0x28,0xe3,0x00]
+@ CHECK: smlalshi	r2, r3, r5, r8  @ encoding: [0x95,0x28,0xf3,0x80]
+
+
+ at ------------------------------------------------------------------------------
 @ STM*
 @------------------------------------------------------------------------------
         stm       r2, {r1,r3-r6,sp}