[llvm-commits] [llvm] r135780 - /llvm/trunk/test/MC/ARM/basic-arm-instructions.s
Jim Grosbach
grosbach at apple.com
Fri Jul 22 11:04:49 PDT 2011
Author: grosbach
Date: Fri Jul 22 13:04:48 2011
New Revision: 135780
URL: http://llvm.org/viewvc/llvm-project?rev=135780&view=rev
Log:
ARM encoding and assembly parsing tests.
Add tests for SHADD8, SHADD16, SHASX, SHSUB8, and SHSUB16.
Modified:
llvm/trunk/test/MC/ARM/basic-arm-instructions.s
Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=135780&r1=135779&r2=135780&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Fri Jul 22 13:04:48 2011
@@ -1314,6 +1314,53 @@
@------------------------------------------------------------------------------
+@ SEV
+ at ------------------------------------------------------------------------------
+ sev
+ seveq
+
+@ CHECK: sev @ encoding: [0x04,0xf0,0x20,0xe3]
+@ CHECK: seveq @ encoding: [0x04,0xf0,0x20,0x03]
+
+ at ------------------------------------------------------------------------------
+@ SHADD16/SHADD8
+ at ------------------------------------------------------------------------------
+ shadd16 r4, r8, r2
+ shadd16gt r4, r8, r2
+ shadd8 r4, r8, r2
+ shadd8gt r4, r8, r2
+
+@ CHECK: shadd16 r4, r8, r2 @ encoding: [0x12,0x4f,0x38,0xe6]
+@ CHECK: shadd16gt r4, r8, r2 @ encoding: [0x12,0x4f,0x38,0xc6]
+@ CHECK: shadd8 r4, r8, r2 @ encoding: [0x92,0x4f,0x38,0xe6]
+@ CHECK: shadd8gt r4, r8, r2 @ encoding: [0x92,0x4f,0x38,0xc6]
+
+
+ at ------------------------------------------------------------------------------
+@ SHASX
+ at ------------------------------------------------------------------------------
+ shasx r4, r8, r2
+ shasxgt r4, r8, r2
+
+@ CHECK: shasx r4, r8, r2 @ encoding: [0x32,0x4f,0x38,0xe6]
+@ CHECK: shasxgt r4, r8, r2 @ encoding: [0x32,0x4f,0x38,0xc6]
+
+
+ at ------------------------------------------------------------------------------
+@ SHSUB16/SHSUB8
+ at ------------------------------------------------------------------------------
+ shsub16 r4, r8, r2
+ shsub16gt r4, r8, r2
+ shsub8 r4, r8, r2
+ shsub8gt r4, r8, r2
+
+@ CHECK: shsub16 r4, r8, r2 @ encoding: [0x72,0x4f,0x38,0xe6]
+@ CHECK: shsub16gt r4, r8, r2 @ encoding: [0x72,0x4f,0x38,0xc6]
+@ CHECK: shsub8 r4, r8, r2 @ encoding: [0xf2,0x4f,0x38,0xe6]
+@ CHECK: shsub8gt r4, r8, r2 @ encoding: [0xf2,0x4f,0x38,0xc6]
+
+
+ at ------------------------------------------------------------------------------
@ STM*
@------------------------------------------------------------------------------
stm r2, {r1,r3-r6,sp}
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