[llvm-commits] [llvm] r135735 - in /llvm/trunk: include/llvm/MC/MCRegisterInfo.h include/llvm/Target/TargetRegisterInfo.h utils/TableGen/RegisterInfoEmitter.cpp utils/TableGen/RegisterInfoEmitter.h
Benjamin Kramer
benny.kra at googlemail.com
Thu Jul 21 17:44:39 PDT 2011
Author: d0k
Date: Thu Jul 21 19:44:39 2011
New Revision: 135735
URL: http://llvm.org/viewvc/llvm-project?rev=135735&view=rev
Log:
Teach tblgen to emit MCRegisterClasses.
- This currently introduces more instances of the static DenseSet dtor, but that should be fixable.
Modified:
llvm/trunk/include/llvm/MC/MCRegisterInfo.h
llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
llvm/trunk/utils/TableGen/RegisterInfoEmitter.h
Modified: llvm/trunk/include/llvm/MC/MCRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCRegisterInfo.h?rev=135735&r1=135734&r2=135735&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/MC/MCRegisterInfo.h Thu Jul 21 19:44:39 2011
@@ -40,10 +40,15 @@
unsigned RS, unsigned Al, int CC, bool Allocable,
iterator RB, iterator RE)
: ID(id), Name(name), RegSize(RS), Alignment(Al), CopyCost(CC),
- Allocatable(Allocable), RegsBegin(RB), RegsEnd(RE) {
- for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I)
- RegSet.insert(*I);
- }
+ Allocatable(Allocable), RegsBegin(RB), RegsEnd(RE) {}
+
+ /// initMCRegisterClass - Initialize initMCRegisterClass. *DO NOT USE*.
+ // FIXME: This could go away if RegSet would use a constant bit field.
+ void initMCRegisterClass() {
+ RegSet.resize(getNumRegs());
+ for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I)
+ RegSet.insert(*I);
+ }
/// getID() - Return the register class ID number.
///
@@ -128,10 +133,14 @@
/// virtual methods.
///
class MCRegisterInfo {
+public:
+ typedef const MCRegisterClass *regclass_iterator;
private:
const MCRegisterDesc *Desc; // Pointer to the descriptor array
unsigned NumRegs; // Number of entries in the array
unsigned RAReg; // Return address register
+ const MCRegisterClass *Classes; // Pointer to the regclass array
+ unsigned NumClasses; // Number of entries in the array
DenseMap<unsigned, int> L2DwarfRegs; // LLVM to Dwarf regs mapping
DenseMap<unsigned, int> EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
DenseMap<unsigned, unsigned> Dwarf2LRegs; // Dwarf to LLVM regs mapping
@@ -141,10 +150,16 @@
public:
/// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen
/// auto-generated routines. *DO NOT USE*.
- void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA) {
+ void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
+ MCRegisterClass *C, unsigned NC) {
Desc = D;
NumRegs = NR;
RAReg = RA;
+ Classes = C;
+ NumClasses = NC;
+ // FIXME: This should go away.
+ for (unsigned i = 0; i != NC; ++i)
+ C[i].initMCRegisterClass();
}
/// mapLLVMRegToDwarfReg - Used to initialize LLVM register to Dwarf
@@ -273,6 +288,20 @@
if (I == L2SEHRegs.end()) return (int)RegNum;
return I->second;
}
+
+ regclass_iterator regclass_begin() const { return Classes; }
+ regclass_iterator regclass_end() const { return Classes+NumClasses; }
+
+ unsigned getNumRegClasses() const {
+ return (unsigned)(regclass_end()-regclass_begin());
+ }
+
+ /// getRegClass - Returns the register class associated with the enumeration
+ /// value. See class MCOperandInfo.
+ const MCRegisterClass getRegClass(unsigned i) const {
+ assert(i < getNumRegClasses() && "Register Class ID out of range");
+ return Classes[i];
+ }
};
} // End llvm namespace
Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=135735&r1=135734&r2=135735&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Thu Jul 21 19:44:39 2011
@@ -52,7 +52,9 @@
iterator RB, iterator RE)
: MCRegisterClass(id, name, RS, Al, CC, Allocable, RB, RE),
VTs(vts), SubClasses(subcs), SuperClasses(supcs), SubRegClasses(subregcs),
- SuperRegClasses(superregcs) {}
+ SuperRegClasses(superregcs) {
+ initMCRegisterClass();
+ }
virtual ~TargetRegisterClass() {} // Allow subclasses
Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=135735&r1=135734&r2=135735&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Thu Jul 21 19:44:39 2011
@@ -297,12 +297,62 @@
}
OS << "};\n\n"; // End of register descriptors...
+ // FIXME: This code is duplicated in the TargetRegisterClass emitter.
+ const std::vector<CodeGenRegisterClass> &RegisterClasses =
+ Target.getRegisterClasses();
+
+ // Loop over all of the register classes... emitting each one.
+ OS << "namespace { // Register classes...\n";
+
+ // Emit the register enum value arrays for each RegisterClass
+ for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
+ const CodeGenRegisterClass &RC = RegisterClasses[rc];
+ ArrayRef<Record*> Order = RC.getOrder();
+
+ // Give the register class a legal C name if it's anonymous.
+ std::string Name = RC.getName();
+
+ // Emit the register list now.
+ OS << " // " << Name << " Register Class...\n"
+ << " static const unsigned " << Name
+ << "[] = {\n ";
+ for (unsigned i = 0, e = Order.size(); i != e; ++i) {
+ Record *Reg = Order[i];
+ OS << getQualifiedName(Reg) << ", ";
+ }
+ OS << "\n };\n\n";
+ }
+ OS << "}\n\n";
+
+ OS << "MCRegisterClass " << TargetName << "MCRegisterClasses[] = {\n";
+
+ for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
+ const CodeGenRegisterClass &RC = RegisterClasses[rc];
+ ArrayRef<Record*> Order = RC.getOrder();
+
+ std::string Name = RC.getName();
+
+ OS << " MCRegisterClass("
+ << rc << ", "
+ << '\"' << RC.getName() << "\", "
+ << RC.SpillSize/8 << ", "
+ << RC.SpillAlignment/8 << ", "
+ << RC.CopyCost << ", "
+ << RC.Allocatable << ", "
+ << RC.getName() << ", " << RC.getName() << " + "
+ << RC.getOrder().size()
+ << "),\n";
+ }
+
+ OS << "};\n\n";
+
// MCRegisterInfo initialization routine.
OS << "static inline void Init" << TargetName
<< "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
<< "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n";
OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
- << Regs.size()+1 << ", RA);\n\n";
+ << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
+ << RegisterClasses.size() << ");\n\n";
EmitRegMapping(OS, Regs, false);
@@ -773,6 +823,7 @@
// Emit the constructor of the class...
OS << "extern MCRegisterDesc " << TargetName << "RegDesc[];\n";
+ OS << "extern MCRegisterClass " << TargetName << "MCRegisterClasses[];\n";
OS << ClassName << "::" << ClassName
<< "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n"
@@ -780,7 +831,8 @@
<< ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
<< " " << TargetName << "SubRegIndexTable) {\n"
<< " InitMCRegisterInfo(" << TargetName << "RegDesc, "
- << Regs.size()+1 << ", RA);\n\n";
+ << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
+ << RegisterClasses.size() << ");\n\n";
EmitRegMapping(OS, Regs, true);
Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.h?rev=135735&r1=135734&r2=135735&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.h (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.h Thu Jul 21 19:44:39 2011
@@ -50,6 +50,7 @@
private:
void EmitRegMapping(raw_ostream &o,
const std::vector<CodeGenRegister*> &Regs, bool isCtor);
+ void EmitRegClasses(raw_ostream &OS, CodeGenTarget &Target);
};
} // End llvm namespace
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