[llvm-commits] [llvm] r135718 - in /llvm/trunk/test/MC/ARM: arm_instructions.s basic-arm-instructions.s

[Jim Grosbach]

Author: grosbach
Date: Thu Jul 21 18:03:59 2011
New Revision: 135718

URL: http://llvm.org/viewvc/llvm-project?rev=135718&view=rev
Log:
ARM parsing and encoding tests for SBC instruction.

Modified:
    llvm/trunk/test/MC/ARM/arm_instructions.s
    llvm/trunk/test/MC/ARM/basic-arm-instructions.s

Modified: llvm/trunk/test/MC/ARM/arm_instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_instructions.s?rev=135718&r1=135717&r2=135718&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/arm_instructions.s (original)
+++ llvm/trunk/test/MC/ARM/arm_instructions.s Thu Jul 21 18:03:59 2011
@@ -39,9 +39,6 @@
 @ CHECK: adc	r1, r2, r3 @ encoding: [0x03,0x10,0xa2,0xe0]
         adc r1,r2,r3
 
-@ CHECK: sbc	r1, r2, r3 @ encoding: [0x03,0x10,0xc2,0xe0]
-        sbc r1,r2,r3
-
 @ CHECK: bic	r1, r2, r3 @ encoding: [0x03,0x10,0xc2,0xe1]
         bic r1,r2,r3
 

Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=135718&r1=135717&r2=135718&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Thu Jul 21 18:03:59 2011
@@ -1241,6 +1241,59 @@
 
 
 @------------------------------------------------------------------------------
+@ SBC
+ at ------------------------------------------------------------------------------
+        sbc r4, r5, #0xf000
+        sbc r4, r5, r6
+        sbc r4, r5, r6, lsl #5
+        sbc r4, r5, r6, lsr #5
+        sbc r4, r5, r6, lsr #5
+        sbc r4, r5, r6, asr #5
+        sbc r4, r5, r6, ror #5
+        sbc r6, r7, r8, lsl r9
+        sbc r6, r7, r8, lsr r9
+        sbc r6, r7, r8, asr r9
+        sbc r6, r7, r8, ror r9
+
+        @ destination register is optional
+        sbc r5, #0xf000
+        sbc r4, r5
+        sbc r4, r5, lsl #5
+        sbc r4, r5, lsr #5
+        sbc r4, r5, lsr #5
+        sbc r4, r5, asr #5
+        sbc r4, r5, ror #5
+        sbc r6, r7, lsl r9
+        sbc r6, r7, lsr r9
+        sbc r6, r7, asr r9
+        sbc r6, r7, ror r9
+
+@ CHECK: sbc	r4, r5, #61440          @ encoding: [0x0f,0x4a,0xc5,0xe2]
+@ CHECK: sbc	r4, r5, r6              @ encoding: [0x06,0x40,0xc5,0xe0]
+@ CHECK: sbc	r4, r5, r6, lsl #5      @ encoding: [0x86,0x42,0xc5,0xe0]
+@ CHECK: sbc	r4, r5, r6, lsr #5      @ encoding: [0xa6,0x42,0xc5,0xe0]
+@ CHECK: sbc	r4, r5, r6, lsr #5      @ encoding: [0xa6,0x42,0xc5,0xe0]
+@ CHECK: sbc	r4, r5, r6, asr #5      @ encoding: [0xc6,0x42,0xc5,0xe0]
+@ CHECK: sbc	r4, r5, r6, ror #5      @ encoding: [0xe6,0x42,0xc5,0xe0]
+@ CHECK: sbc	r6, r7, r8, lsl r9      @ encoding: [0x18,0x69,0xc7,0xe0]
+@ CHECK: sbc	r6, r7, r8, lsr r9      @ encoding: [0x38,0x69,0xc7,0xe0]
+@ CHECK: sbc	r6, r7, r8, asr r9      @ encoding: [0x58,0x69,0xc7,0xe0]
+@ CHECK: sbc	r6, r7, r8, ror r9      @ encoding: [0x78,0x69,0xc7,0xe0]
+
+@ CHECK: sbc	r5, r5, #61440          @ encoding: [0x0f,0x5a,0xc5,0xe2]
+@ CHECK: sbc	r4, r4, r5              @ encoding: [0x05,0x40,0xc4,0xe0]
+@ CHECK: sbc	r4, r4, r5, lsl #5      @ encoding: [0x85,0x42,0xc4,0xe0]
+@ CHECK: sbc	r4, r4, r5, lsr #5      @ encoding: [0xa5,0x42,0xc4,0xe0]
+@ CHECK: sbc	r4, r4, r5, lsr #5      @ encoding: [0xa5,0x42,0xc4,0xe0]
+@ CHECK: sbc	r4, r4, r5, asr #5      @ encoding: [0xc5,0x42,0xc4,0xe0]
+@ CHECK: sbc	r4, r4, r5, ror #5      @ encoding: [0xe5,0x42,0xc4,0xe0]
+@ CHECK: sbc	r6, r6, r7, lsl r9      @ encoding: [0x17,0x69,0xc6,0xe0]
+@ CHECK: sbc	r6, r6, r7, lsr r9      @ encoding: [0x37,0x69,0xc6,0xe0]
+@ CHECK: sbc	r6, r6, r7, asr r9      @ encoding: [0x57,0x69,0xc6,0xe0]
+@ CHECK: sbc	r6, r6, r7, ror r9      @ encoding: [0x77,0x69,0xc6,0xe0]
+
+
+ at ------------------------------------------------------------------------------
 @ STM*
 @------------------------------------------------------------------------------
         stm       r2, {r1,r3-r6,sp}