[llvm-commits] [llvm] r135626 - in /llvm/trunk: lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.h utils/TableGen/EDEmitter.cpp
Jim Grosbach
grosbach at apple.com
Wed Jul 20 14:40:26 PDT 2011
Author: grosbach
Date: Wed Jul 20 16:40:26 2011
New Revision: 135626
URL: http://llvm.org/viewvc/llvm-project?rev=135626&view=rev
Log:
ARM PKH shift ammount operand printing tweaks.
Move the shift operator and special value (32 encoded as 0 for PKHTB) handling
into the instruction printer. This cleans up a bit of the disassembler
special casing for these instructions, more easily handles not printing the
operand at all for "lsl #0" and prepares for correct asm parsing of these
operands.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
llvm/trunk/utils/TableGen/EDEmitter.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=135626&r1=135625&r2=135626&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Jul 20 16:40:26 2011
@@ -847,8 +847,12 @@
}
// PKH instructions
-def pkh_lsl_amt : ImmLeaf<i32, [{ return Imm >= 0 && Imm < 32; }]>;
-def pkh_asr_amt : ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]>;
+def pkh_lsl_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 32; }]>{
+ let PrintMethod = "printPKHLSLShiftImm";
+}
+def pkh_asr_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]>{
+ let PrintMethod = "printPKHASRShiftImm";
+}
class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=135626&r1=135625&r2=135626&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Jul 20 16:40:26 2011
@@ -3112,8 +3112,8 @@
(REVSH GPR:$Rm)>;
def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
- (ins GPR:$Rn, GPR:$Rm, i32imm:$sh),
- IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm, lsl $sh",
+ (ins GPR:$Rn, GPR:$Rm, pkh_lsl_amt:$sh),
+ IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
[(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
(and (shl GPR:$Rm, pkh_lsl_amt:$sh),
0xFFFF0000)))]>,
@@ -3128,8 +3128,8 @@
// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
// will match the pattern below.
def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
- (ins GPR:$Rn, GPR:$Rm, i32imm:$sh),
- IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm, asr $sh",
+ (ins GPR:$Rn, GPR:$Rm, pkh_asr_amt:$sh),
+ IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
[(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
(and (sra GPR:$Rm, pkh_asr_amt:$sh),
0xFFFF)))]>,
Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=135626&r1=135625&r2=135626&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Wed Jul 20 16:40:26 2011
@@ -1632,16 +1632,11 @@
&& !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
// Extract the 5-bit immediate field Inst{11-7}.
unsigned ShiftAmt = (insn >> ARMII::ShiftShift) & 0x1F;
- ARM_AM::ShiftOpc Opc = ARM_AM::no_shift;
- if (Opcode == ARM::PKHBT)
- Opc = ARM_AM::lsl;
- else if (Opcode == ARM::PKHTB)
- Opc = ARM_AM::asr;
- getImmShiftSE(Opc, ShiftAmt);
if (Opcode == ARM::PKHBT || Opcode == ARM::PKHTB)
MI.addOperand(MCOperand::CreateImm(ShiftAmt));
else
- MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShiftAmt)));
+ MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(ARM_AM::no_shift,
+ ShiftAmt)));
++OpIdx;
}
Modified: llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h?rev=135626&r1=135625&r2=135626&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h Wed Jul 20 16:40:26 2011
@@ -1498,16 +1498,17 @@
MI.addOperand(MCOperand::CreateImm(Imm));
} else {
// Build the constant shift specifier operand.
- unsigned bits2 = getShiftTypeBits(insn);
unsigned imm5 = getShiftAmtBits(insn);
- ARM_AM::ShiftOpc ShOp = ARM_AM::no_shift;
- unsigned ShAmt = decodeImmShift(bits2, imm5, ShOp);
// The PKHBT/PKHTB instructions have an implied shift type and so just
// use a plain immediate for the amount.
if (Opcode == ARM::t2PKHBT || Opcode == ARM::t2PKHTB)
- MI.addOperand(MCOperand::CreateImm(ShAmt));
- else
+ MI.addOperand(MCOperand::CreateImm(imm5));
+ else {
+ ARM_AM::ShiftOpc ShOp = ARM_AM::no_shift;
+ unsigned bits2 = getShiftTypeBits(insn);
+ unsigned ShAmt = decodeImmShift(bits2, imm5, ShOp);
MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(ShOp, ShAmt)));
+ }
}
++OpIdx;
}
Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=135626&r1=135625&r2=135626&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Wed Jul 20 16:40:26 2011
@@ -441,6 +441,25 @@
O << ARM_AM::getSORegOffset(ShiftOp);
}
+void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
+ raw_ostream &O) {
+ unsigned Imm = MI->getOperand(OpNum).getImm();
+ if (Imm == 0)
+ return;
+ assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
+ O << ", lsl #" << Imm;
+}
+
+void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
+ raw_ostream &O) {
+ unsigned Imm = MI->getOperand(OpNum).getImm();
+ // A shift amount of 32 is encoded as 0.
+ if (Imm == 0)
+ Imm = 32;
+ assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
+ O << ", asr #" << Imm;
+}
+
void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
O << "{";
Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=135626&r1=135625&r2=135626&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original)
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Wed Jul 20 16:40:26 2011
@@ -65,6 +65,8 @@
raw_ostream &O);
void printMemBOption(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printShiftImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
+ void printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, raw_ostream &O);
+ void printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printThumbITMask(const MCInst *MI, unsigned OpNum, raw_ostream &O);
Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=135626&r1=135625&r2=135626&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/EDEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/EDEmitter.cpp Wed Jul 20 16:40:26 2011
@@ -594,6 +594,8 @@
IMM("imm0_4095");
IMM("imm0_65535");
IMM("imm0_65535_expr");
+ IMM("pkh_lsl_amt");
+ IMM("pkh_asr_amt");
IMM("jt2block_operand");
IMM("t_imm_s4");
IMM("pclabel");
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