[llvm-commits] [llvm] r135476 - in /llvm/trunk: include/llvm/IntrinsicsXCore.td lib/Target/XCore/XCoreInstrInfo.td test/CodeGen/XCore/misc-intrinsics.ll

[Richard Osborne]

Author: friedgold
Date: Tue Jul 19 08:28:50 2011
New Revision: 135476

URL: http://llvm.org/viewvc/llvm-project?rev=135476&view=rev
Log:
Add intrinsics for the zext / sext instructions.

Modified:
    llvm/trunk/include/llvm/IntrinsicsXCore.td
    llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td
    llvm/trunk/test/CodeGen/XCore/misc-intrinsics.ll

Modified: llvm/trunk/include/llvm/IntrinsicsXCore.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsXCore.td?rev=135476&r1=135475&r2=135476&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IntrinsicsXCore.td (original)
+++ llvm/trunk/include/llvm/IntrinsicsXCore.td Tue Jul 19 08:28:50 2011
@@ -17,6 +17,10 @@
   def int_xcore_crc32 : Intrinsic<[llvm_i32_ty],
                                   [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],
                                   [IntrNoMem]>;
+  def int_xcore_sext : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
+                                 [IntrNoMem]>;
+  def int_xcore_zext : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
+                                 [IntrNoMem]>;
   def int_xcore_getid : Intrinsic<[llvm_i32_ty],[],[IntrNoMem]>;
   def int_xcore_getps : Intrinsic<[llvm_i32_ty],[llvm_i32_ty]>;
   def int_xcore_setps : Intrinsic<[],[llvm_i32_ty, llvm_i32_ty]>;

Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td?rev=135476&r1=135475&r2=135476&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td (original)
+++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td Tue Jul 19 08:28:50 2011
@@ -754,7 +754,7 @@
 }
 
 // Two operand short
-// TODO eet, eef, tsetmr, sext (reg), zext (reg)
+// TODO eet, eef, tsetmr
 def NOT : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b),
                  "not $dst, $b",
                  [(set GRRegs:$dst, (not GRRegs:$b))]>;
@@ -764,15 +764,21 @@
                  [(set GRRegs:$dst, (ineg GRRegs:$b))]>;
 
 let Constraints = "$src1 = $dst" in {
-let neverHasSideEffects = 1 in
 def SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
-                 "sext $dst, $src2",
-                 []>;
+                      "sext $dst, $src2",
+                      [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, immBitp:$src2))]>;
+
+def SEXT_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
+                     "sext $dst, $src2",
+                     [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, GRRegs:$src2))]>;
 
-let neverHasSideEffects = 1 in
 def ZEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
-                 "zext $dst, $src2",
-                 []>;
+                      "zext $dst, $src2",
+                      [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, immBitp:$src2))]>;
+
+def ZEXT_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
+                     "zext $dst, $src2",
+                     [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, GRRegs:$src2))]>;
 
 def ANDNOT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
                  "andnot $dst, $src2",

Modified: llvm/trunk/test/CodeGen/XCore/misc-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/XCore/misc-intrinsics.ll?rev=135476&r1=135475&r2=135476&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/XCore/misc-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/XCore/misc-intrinsics.ll Tue Jul 19 08:28:50 2011
@@ -4,6 +4,8 @@
 declare i32 @llvm.xcore.bitrev(i32)
 declare i32 @llvm.xcore.crc32(i32, i32, i32)
 declare %0 @llvm.xcore.crc8(i32, i32, i32)
+declare i32 @llvm.xcore.zext(i32, i32)
+declare i32 @llvm.xcore.sext(i32, i32)
 
 define i32 @bitrev(i32 %val) {
 ; CHECK: bitrev:
@@ -25,3 +27,31 @@
 	%result = call %0 @llvm.xcore.crc8(i32 %crc, i32 %data, i32 %poly)
 	ret %0 %result
 }
+
+define i32 @zext(i32 %a, i32 %b) {
+; CHECK: zext:
+; CHECK: zext r0, r1
+	%result = call i32 @llvm.xcore.zext(i32 %a, i32 %b)
+	ret i32 %result
+}
+
+define i32 @zexti(i32 %a) {
+; CHECK: zexti:
+; CHECK: zext r0, 4
+	%result = call i32 @llvm.xcore.zext(i32 %a, i32 4)
+	ret i32 %result
+}
+
+define i32 @sext(i32 %a, i32 %b) {
+; CHECK: sext:
+; CHECK: sext r0, r1
+	%result = call i32 @llvm.xcore.sext(i32 %a, i32 %b)
+	ret i32 %result
+}
+
+define i32 @sexti(i32 %a) {
+; CHECK: sexti:
+; CHECK: sext r0, 4
+	%result = call i32 @llvm.xcore.sext(i32 %a, i32 4)
+	ret i32 %result
+}