[llvm-commits] [llvm] r135418 - in /llvm/trunk: lib/Target/Mips/MipsISelLowering.cpp test/CodeGen/Mips/atomic.ll

[Akira Hatanaka]

Author: ahatanak
Date: Mon Jul 18 14:58:59 2011
New Revision: 135418

URL: http://llvm.org/viewvc/llvm-project?rev=135418&view=rev
Log:
Do not treat atomic.load.sub differently than other atomic binary intrinsics.

Modified:
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
    llvm/trunk/test/CodeGen/Mips/atomic.ll

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=135418&r1=135417&r2=135418&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon Jul 18 14:58:59 2011
@@ -819,7 +819,6 @@
   unsigned Tmp2 = RegInfo.createVirtualRegister(RC);
   unsigned Tmp3 = RegInfo.createVirtualRegister(RC);
   unsigned Tmp4 = RegInfo.createVirtualRegister(RC);
-  unsigned Tmp5 = RegInfo.createVirtualRegister(RC);
   unsigned Tmp6 = RegInfo.createVirtualRegister(RC);
   unsigned Tmp7 = RegInfo.createVirtualRegister(RC);
   unsigned Tmp8 = RegInfo.createVirtualRegister(RC);
@@ -863,14 +862,8 @@
   BuildMI(BB, dl, TII->get(Mips::ORi), Tmp3).addReg(Mips::ZERO).addImm(MaskImm);
   BuildMI(BB, dl, TII->get(Mips::SLL), Mask).addReg(Tmp3).addReg(Shift);
   BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
-  if (BinOpcode != Mips::SUBu) {
-    BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp4).addReg(Incr).addImm(MaskImm);
-    BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Tmp4).addReg(Shift);
-  } else {
-    BuildMI(BB, dl, TII->get(Mips::SUBu), Tmp4).addReg(Mips::ZERO).addReg(Incr);
-    BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp5).addReg(Tmp4).addImm(MaskImm);
-    BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Tmp5).addReg(Shift);
-  }
+  BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp4).addReg(Incr).addImm(MaskImm);
+  BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Tmp4).addReg(Shift);
 
   BB->addSuccessor(loopMBB);
 
@@ -899,9 +892,6 @@
     //  nor tmp7, $0, tmp6
     BuildMI(BB, dl, TII->get(Mips::AND), Tmp6).addReg(Oldval).addReg(Incr2);
     BuildMI(BB, dl, TII->get(Mips::NOR), Tmp7).addReg(Mips::ZERO).addReg(Tmp6);
-  } else if (BinOpcode == Mips::SUBu) {
-    //  addu tmp7, oldval, incr2
-    BuildMI(BB, dl, TII->get(Mips::ADDu), Tmp7).addReg(Oldval).addReg(Incr2);
   } else if (BinOpcode) {
     //  <binop> tmp7, oldval, incr2
     BuildMI(BB, dl, TII->get(BinOpcode), Tmp7).addReg(Oldval).addReg(Incr2);

Modified: llvm/trunk/test/CodeGen/Mips/atomic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/atomic.ll?rev=135418&r1=135417&r2=135418&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/atomic.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/atomic.ll Mon Jul 18 14:58:59 2011
@@ -129,13 +129,12 @@
 ; CHECK:   ori     $[[R5:[0-9]+]], $zero, 255
 ; CHECK:   sll     $[[R6:[0-9]+]], $[[R5]], $[[R4]]
 ; CHECK:   nor     $[[R7:[0-9]+]], $zero, $[[R6]]
-; CHECK:   subu    $[[R18:[0-9]+]], $zero, $4
-; CHECK:   andi    $[[R8:[0-9]+]], $[[R18]], 255
+; CHECK:   andi    $[[R8:[0-9]+]], $4, 255
 ; CHECK:   sll     $[[R9:[0-9]+]], $[[R8]], $[[R4]]
 
 ; CHECK:   $[[BB0:[A-Z_0-9]+]]:
 ; CHECK:   ll      $[[R10:[0-9]+]], 0($[[R2]])
-; CHECK:   addu    $[[R11:[0-9]+]], $[[R10]], $[[R9]]
+; CHECK:   subu    $[[R11:[0-9]+]], $[[R10]], $[[R9]]
 ; CHECK:   and     $[[R12:[0-9]+]], $[[R11]], $[[R6]]
 ; CHECK:   and     $[[R13:[0-9]+]], $[[R10]], $[[R7]]
 ; CHECK:   or      $[[R14:[0-9]+]], $[[R13]], $[[R12]]