[llvm-commits] [llvm] r135156 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp test/MC/ARM/arm_instructions.s

[Jim Grosbach]

Author: grosbach
Date: Thu Jul 14 13:00:31 2011
New Revision: 135156

URL: http://llvm.org/viewvc/llvm-project?rev=135156&view=rev
Log:
ARM ISB instruction assembly parsing.

The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.


Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
    llvm/trunk/test/MC/ARM/arm_instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=135156&r1=135155&r2=135156&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Jul 14 13:00:31 2011
@@ -3317,12 +3317,16 @@
 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
 
 // ISB has only full system option
-def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
+def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
+                "isb", "\t$opt", []>,
                 Requires<[IsARM, HasDB]> {
+  bits<4> opt;
   let Inst{31-4} = 0xf57ff06;
-  let Inst{3-0} = 0b1111;
+  let Inst{3-0} = opt;
 }
 
+def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
+
 let usesCustomInserter = 1 in {
   let Uses = [CPSR] in {
     def ATOMIC_LOAD_ADD_I8 : PseudoInst<

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=135156&r1=135155&r2=135156&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Thu Jul 14 13:00:31 2011
@@ -3380,7 +3380,7 @@
 static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
     unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
 
-  if (Opcode == ARM::DMB || Opcode == ARM::DSB) {
+  if (Opcode == ARM::DMB || Opcode == ARM::DSB || Opcode == ARM::ISB) {
     // Inst{3-0} encodes the memory barrier option for the variants.
     unsigned opt = slice(insn, 3, 0);
     switch (opt) {

Modified: llvm/trunk/test/MC/ARM/arm_instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_instructions.s?rev=135156&r1=135155&r2=135156&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/arm_instructions.s (original)
+++ llvm/trunk/test/MC/ARM/arm_instructions.s Thu Jul 14 13:00:31 2011
@@ -139,7 +139,7 @@
 @ CHECK: bkpt  #10 @ encoding: [0x7a,0x00,0x20,0xe1]
         bkpt  #10
 
-@ CHECK: isb @ encoding: [0x6f,0xf0,0x7f,0xf5]
+@ CHECK: isb sy @ encoding: [0x6f,0xf0,0x7f,0xf5]
         isb
 @ CHECK: mrs  r8, cpsr @ encoding: [0x00,0x80,0x0f,0xe1]
         mrs  r8, cpsr