[llvm-commits] [llvm] r135102 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td test/MC/ARM/basic-arm-instructions.s test/MC/ARM/diagnostics.s
Jim Grosbach
grosbach at apple.com
Wed Jul 13 15:59:38 PDT 2011
Author: grosbach
Date: Wed Jul 13 17:59:38 2011
New Revision: 135102
URL: http://llvm.org/viewvc/llvm-project?rev=135102&view=rev
Log:
ARM Assembler support for DBG instruction.
Add range checking and testing for parsing and encoding of DBG instruction.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
llvm/trunk/test/MC/ARM/basic-arm-instructions.s
llvm/trunk/test/MC/ARM/diagnostics.s
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=135102&r1=135101&r2=135102&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Jul 13 17:59:38 2011
@@ -1283,9 +1283,8 @@
let Inst{8-0} = 0;
}
-def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
- [/* For disassembly only; pattern left blank */]>,
- Requires<[IsARM, HasV7]> {
+def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
+ []>, Requires<[IsARM, HasV7]> {
bits<4> opt;
let Inst{27-4} = 0b001100100000111100001111;
let Inst{3-0} = opt;
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=135102&r1=135101&r2=135102&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Jul 13 17:59:38 2011
@@ -3157,8 +3157,7 @@
def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
-def t2DBG : T2I<(outs),(ins i32imm:$opt), NoItinerary, "dbg", "\t$opt",
- [/* For disassembly only; pattern left blank */]> {
+def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
let Inst{31-20} = 0xf3a;
let Inst{15-14} = 0b10;
let Inst{12} = 0;
Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=135102&r1=135101&r2=135102&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Jul 13 17:59:38 2011
@@ -448,3 +448,13 @@
@ CHECK: cmp r7, r8, ror r2 @ encoding: [0x78,0x02,0x57,0xe1]
@ CHECK: cmp r1, r6, rrx @ encoding: [0x66,0x00,0x51,0xe1]
+ at ------------------------------------------------------------------------------
+@ DBG
+ at ------------------------------------------------------------------------------
+ dbg #0
+ dbg #5
+ dbg #15
+
+@ CHECK: dbg #0 @ encoding: [0xf0,0xf0,0x20,0xe3]
+@ CHECK: dbg #5 @ encoding: [0xf5,0xf0,0x20,0xe3]
+@ CHECK: dbg #15 @ encoding: [0xff,0xf0,0x20,0xe3]
Modified: llvm/trunk/test/MC/ARM/diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/diagnostics.s?rev=135102&r1=135101&r2=135102&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/diagnostics.s (original)
+++ llvm/trunk/test/MC/ARM/diagnostics.s Wed Jul 13 17:59:38 2011
@@ -59,3 +59,12 @@
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: error: invalid operand for instruction
+
+ @ Out of range immediates for DBG
+ dbg #-1
+ dbg #16
+
+@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-ERRORS: error: invalid operand for instruction
+@ Double-check that we're synced up with the right diagnostics.
+@ CHECK-ERRORS: dbg #16
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