[llvm-commits] [llvm] r134746 - in /llvm/trunk: lib/Target/ARM/ARMConstantIslandPass.cpp lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/Thumb1FrameLowering.cpp test/CodeGen/Thumb2/machine-licm.ll test/CodeGen/Thumb2/thumb2-bcc.ll test/CodeGen/Thumb2/thumb2-branch.ll test/CodeGen/Thumb2/thumb2-ifcvt1.ll
Jim Grosbach
grosbach at apple.com
Tue Jul 12 09:07:41 PDT 2011
On Jul 11, 2011, at 9:07 AM, Evan Cheng wrote:
>
>
> On Jul 11, 2011, at 7:49 AM, Jim Grosbach <grosbach at apple.com> wrote:
>
>>
>> On Jul 9, 2011, at 4:47 PM, Evan Cheng wrote:
>>
>>> Hi Jim,
>>>
>>> It's generally a bad idea to use hidden options for these tests. Can you disable ifcvt another way? Have you tried specifying CPU name or adjust the tests?
>>>
>>
>> I agree it's suboptimal to reference those sorts of options. In this case I took it as the lesser of two evils, as adjusting the tests would either a) change them t no longer test what they are written to be testing, or b) obfuscate the test by enlarging them solely to defeat if-conversion. Neither of those options seems very appealing.
>>
>> I didn't see any other way to disable if conversion short of disabling optimization altogether. I don''t think a different CPU name would have any effect here. Did you have something specific in mind? If there's something along those lines that would work, that would be great.
>
> Yes, different cpu's have different misprediction costs which impact ifcvt. I don't know if it matters for these tests but it's worth trying.
>
No luck on cpu selection; however, I was able to prevent f-conversion via memory barrier intrinsics. They're non predicable and won't be moved around, so they do the job. r134986.
-Jim
>>
>>>
>>> On Jul 8, 2011, at 2:50 PM, Jim Grosbach <grosbach at apple.com> wrote:
>>>
>>>> Author: grosbach
>>>> Date: Fri Jul 8 16:50:04 2011
>>>> New Revision: 134746
>>>>
>>>> URL: http://llvm.org/viewvc/llvm-project?rev=134746&view=rev
>>>> Log:
>>>> Make tBX_RET and tBX_RET_vararg predicable.
>>>>
>>>> The normal tBX instruction is predicable, so there's no reason the
>>>> pseudos for using it as a return shouldn't be. Gives us some nice code-gen
>>>> improvements as can be seen by the test changes. In particular, several
>>>> tests now have to disable if-conversion because it works too well and defeats
>>>> the test.
>>>>
>>>> Modified:
>>>> llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
>>>> llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
>>>> llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp
>>>> llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll
>>>> llvm/trunk/test/CodeGen/Thumb2/thumb2-bcc.ll
>>>> llvm/trunk/test/CodeGen/Thumb2/thumb2-branch.ll
>>>> llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll
>>>>
>>>> Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=134746&r1=134745&r2=134746&view=diff
>>>> ==============================================================================
>>>> --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original)
>>>> +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Fri Jul 8 16:50:04 2011
>>>> @@ -1538,7 +1538,10 @@
>>>> if (MI->getOpcode() == ARM::tPOP_RET &&
>>>> MI->getOperand(2).getReg() == ARM::PC &&
>>>> MI->getNumExplicitOperands() == 3) {
>>>> - BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET));
>>>> + // Create the new insn and copy the predicate from the old.
>>>> + BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET))
>>>> + .addOperand(MI->getOperand(0))
>>>> + .addOperand(MI->getOperand(1));
>>>> MI->eraseFromParent();
>>>> MadeChange = true;
>>>> }
>>>>
>>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=134746&r1=134745&r2=134746&view=diff
>>>> ==============================================================================
>>>> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
>>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Jul 8 16:50:04 2011
>>>> @@ -385,13 +385,13 @@
>>>> }
>>>>
>>>> let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
>>>> - def tBX_RET : tPseudoExpand<(outs), (ins), Size2Bytes, IIC_Br,
>>>> - [(ARMretflag)], (tBX LR, (ops 14, zero_reg))>;
>>>> + def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), Size2Bytes, IIC_Br,
>>>> + [(ARMretflag)], (tBX LR, pred:$p)>;
>>>>
>>>> // Alternative return instruction used by vararg functions.
>>>> - def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm),
>>>> + def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
>>>> Size2Bytes, IIC_Br, [],
>>>> - (tBX GPR:$Rm, (ops 14, zero_reg))>;
>>>> + (tBX GPR:$Rm, pred:$p)>;
>>>> }
>>>>
>>>> // All calls clobber the non-callee saved registers. SP is marked as a use to
>>>>
>>>> Modified: llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp?rev=134746&r1=134745&r2=134746&view=diff
>>>> ==============================================================================
>>>> --- llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp (original)
>>>> +++ llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp Fri Jul 8 16:50:04 2011
>>>> @@ -273,8 +273,8 @@
>>>>
>>>> emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, VARegSaveSize);
>>>>
>>>> - BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
>>>> - .addReg(ARM::R3, RegState::Kill);
>>>> + AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
>>>> + .addReg(ARM::R3, RegState::Kill));
>>>> // erase the old tBX_RET instruction
>>>> MBB.erase(MBBI);
>>>> }
>>>>
>>>> Modified: llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll?rev=134746&r1=134745&r2=134746&view=diff
>>>> ==============================================================================
>>>> --- llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll (original)
>>>> +++ llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll Fri Jul 8 16:50:04 2011
>>>> @@ -8,26 +8,25 @@
>>>> define void @t1(i32* nocapture %vals, i32 %c) nounwind {
>>>> entry:
>>>> ; CHECK: t1:
>>>> -; CHECK: cbz
>>>> +; CHECK: bxeq lr
>>>> +
>>>> %0 = icmp eq i32 %c, 0 ; <i1> [#uses=1]
>>>> br i1 %0, label %return, label %bb.nph
>>>>
>>>> bb.nph: ; preds = %entry
>>>> -; CHECK: BB#1
>>>> ; CHECK: movw r[[R2:[0-9]+]], :lower16:L_GV$non_lazy_ptr
>>>> ; CHECK: movt r[[R2]], :upper16:L_GV$non_lazy_ptr
>>>> ; CHECK: ldr{{(.w)?}} r[[R2b:[0-9]+]], [r[[R2]]
>>>> ; CHECK: ldr{{.*}}, [r[[R2b]]
>>>> -; CHECK: LBB0_2
>>>> +; CHECK: LBB0_
>>>> ; CHECK-NOT: LCPI0_0:
>>>>
>>>> -; PIC: BB#1
>>>> ; PIC: movw r[[R2:[0-9]+]], :lower16:(L_GV$non_lazy_ptr-(LPC0_0+4))
>>>> ; PIC: movt r[[R2]], :upper16:(L_GV$non_lazy_ptr-(LPC0_0+4))
>>>> ; PIC: add r[[R2]], pc
>>>> ; PIC: ldr{{(.w)?}} r[[R2b:[0-9]+]], [r[[R2]]
>>>> ; PIC: ldr{{.*}}, [r[[R2b]]
>>>> -; PIC: LBB0_2
>>>> +; PIC: LBB0_
>>>> ; PIC-NOT: LCPI0_0:
>>>> ; PIC: .section
>>>> %.pre = load i32* @GV, align 4 ; <i32> [#uses=1]
>>>>
>>>> Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-bcc.ll
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-bcc.ll?rev=134746&r1=134745&r2=134746&view=diff
>>>> ==============================================================================
>>>> --- llvm/trunk/test/CodeGen/Thumb2/thumb2-bcc.ll (original)
>>>> +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-bcc.ll Fri Jul 8 16:50:04 2011
>>>> @@ -1,5 +1,7 @@
>>>> -; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
>>>> -; RUN: llc < %s -march=thumb -mattr=+thumb2 | not grep it
>>>> +; RUN: llc < %s -ifcvt-limit=0 -march=thumb -mattr=+thumb2 | FileCheck %s
>>>> +; RUN: llc < %s -ifcvt-limit=0 -march=thumb -mattr=+thumb2 | not grep it
>>>> +; If-conversion defeats the purpose of this test, which is to check CBZ
>>>> +; generation, so turn it off.
>>>>
>>>> define i32 @t1(i32 %a, i32 %b, i32 %c) {
>>>> ; CHECK: t1:
>>>>
>>>> Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-branch.ll
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-branch.ll?rev=134746&r1=134745&r2=134746&view=diff
>>>> ==============================================================================
>>>> --- llvm/trunk/test/CodeGen/Thumb2/thumb2-branch.ll (original)
>>>> +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-branch.ll Fri Jul 8 16:50:04 2011
>>>> @@ -1,4 +1,6 @@
>>>> -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s
>>>> +; RUN: llc < %s -ifcvt-limit=0 -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s
>>>> +; If-conversion defeats the purpose of this test, which is to check conditional
>>>> +; branch generation, so turn it off.
>>>>
>>>> define i32 @f1(i32 %a, i32 %b, i32* %v) {
>>>> entry:
>>>>
>>>> Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll?rev=134746&r1=134745&r2=134746&view=diff
>>>> ==============================================================================
>>>> --- llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll (original)
>>>> +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll Fri Jul 8 16:50:04 2011
>>>> @@ -2,8 +2,10 @@
>>>>
>>>> define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
>>>> ; CHECK: t1:
>>>> -; CHECK: it ne
>>>> +; CHECK: ittt ne
>>>> ; CHECK: cmpne
>>>> +; CHECK: addne
>>>> +; CHECK: bxne lr
>>>> switch i32 %c, label %cond_next [
>>>> i32 1, label %cond_true
>>>> i32 7, label %cond_true
>>>>
>>>>
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>>
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