[llvm-commits] [llvm] r134665 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/inline-asm-q-regs.ll

[Nick Lewycky]

Author: nicholas
Date: Thu Jul  7 19:19:27 2011
New Revision: 134665

URL: http://llvm.org/viewvc/llvm-project?rev=134665&view=rev
Log:
Let the inline asm 'q' constraint match float, and on 64-bit double too.
Fixes PR9602!

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/CodeGen/X86/inline-asm-q-regs.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=134665&r1=134664&r2=134665&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Jul  7 19:19:27 2011
@@ -12891,19 +12891,19 @@
       // in the normal allocation?
     case 'q':   // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
       if (Subtarget->is64Bit()) {
-	if (VT == MVT::i32)
+	if (VT == MVT::i32 || VT == MVT::f32)
 	  return std::make_pair(0U, X86::GR32RegisterClass);
 	else if (VT == MVT::i16)
 	  return std::make_pair(0U, X86::GR16RegisterClass);
 	else if (VT == MVT::i8)
 	  return std::make_pair(0U, X86::GR8RegisterClass);
-	else if (VT == MVT::i64)
+	else if (VT == MVT::i64 || VT == MVT::f64)
 	  return std::make_pair(0U, X86::GR64RegisterClass);
 	break;
       }
       // 32-bit fallthrough
     case 'Q':   // Q_REGS
-      if (VT == MVT::i32)
+      if (VT == MVT::i32 || VT == MVT::f32)
 	return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
       else if (VT == MVT::i16)
 	return std::make_pair(0U, X86::GR16_ABCDRegisterClass);

Modified: llvm/trunk/test/CodeGen/X86/inline-asm-q-regs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm-q-regs.ll?rev=134665&r1=134664&r2=134665&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/inline-asm-q-regs.ll (original)
+++ llvm/trunk/test/CodeGen/X86/inline-asm-q-regs.ll Thu Jul  7 19:19:27 2011
@@ -3,8 +3,20 @@
 
 	%0 = type { i64, i64, i64, i64, i64 }		; type %0
 
-define void @t() nounwind {
+define void @test1() nounwind {
 entry:
 	%asmtmp = call %0 asm sideeffect "mov    %cr0, $0       \0Amov    %cr2, $1       \0Amov    %cr3, $2       \0Amov    %cr4, $3       \0Amov    %cr8, $0       \0A", "=q,=q,=q,=q,=q,~{dirflag},~{fpsr},~{flags}"() nounwind		; <%0> [#uses=0]
 	ret void
 }
+
+; PR9602
+define void @test2(float %tmp) nounwind {
+  call void asm sideeffect "$0", "q"(float %tmp) nounwind
+  call void asm sideeffect "$0", "Q"(float %tmp) nounwind
+  ret void
+}
+
+define void @test3(double %tmp) nounwind {
+  call void asm sideeffect "$0", "q"(double %tmp) nounwind
+  ret void
+}