[llvm-commits] patch: support float/double in 'q'/'Q' constraint on x86

[Nick Lewycky]

Faced with an inline asm 'q' constraint, GCC appears to put floats in 32-bit
ABCD registers and on x86_64 puts doubles in 64-bit ABCD registers. This
patch replicates that behaviour. GCC also puts 64-bit doubles into 32-bit
ABCD registers in 32-bit mode. This patch does not replicate that behaviour,
preferring the current technique of issuing a backend error.

Please review!

Nick
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