[llvm-commits] [llvm] r134268 - in /llvm/trunk: lib/Analysis/IVUsers.cpp test/CodeGen/X86/lsr-nonaffine.ll

[Francois Pichet]

On Fri, Jul 1, 2011 at 11:52 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:
>
> On Jul 1, 2011, at 8:17 PM, Francois Pichet wrote:
>
> +; CHECK:        xorl %eax, %eax
>
> +; CHECK-NEXT:   align
>
> +; CHECK-NEXT: BB0_1:
>
> +; CHECK-NEXT:   movq  %rax, (%rdx)
>
> +; CHECK-NEXT:   addq  %rsi, %rax
>
> +; CHECK-NEXT:   cmpq  %rdi, %rax
>
> +; CHECK-NEXT:   jl
>
> +; CHECK-NEXT:   imulq %rax, %rax
>
> +; CHECK-NEXT:   ret
>
> This fails under MSVC:
> The output is instead:
> foo:
>        xorl    %eax, %eax
>        .align  16, 0x90
> .LBB0_1:
>        movq    %rax, (%r8)
>        addq    %rdx, %rax
>        cmpq    %rcx, %rax
>        jl      .LBB0_1
>        imulq   %rax, %rax
>        ret
>
> Any idea?
>
> Unit tests should only mention explicit registers when a specific register
> is required for correctness.
> Otherwise, use FileCheck variables.
> One of these days, I am going to add -regalloc=random…
> /jakob
>

Interesting! I know close to nothing about register allocation
algorithms but I am curious to know where does that nondeterminism
comes from?