[llvm-commits] [llvm] r134220 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/inlineasm3.ll

[Eric Christopher]

Author: echristo
Date: Thu Jun 30 19:30:46 2011
New Revision: 134220

URL: http://llvm.org/viewvc/llvm-project?rev=134220&view=rev
Log:
Add support for the ARM 't' register constraint. And another testcase
for the 'x' register constraint.

Part of rdar://9119939

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/test/CodeGen/ARM/inlineasm3.ll

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=134220&r1=134219&r2=134220&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Jun 30 19:30:46 2011
@@ -7484,6 +7484,7 @@
     case 'w': return C_RegisterClass;
     case 'h': return C_RegisterClass;
     case 'x': return C_RegisterClass;
+    case 't': return C_RegisterClass;
     }
   } else if (Constraint.size() == 2) {
     switch (Constraint[0]) {
@@ -7563,6 +7564,10 @@
       if (VT.getSizeInBits() == 128)
 	return RCPair(0U, ARM::QPR_8RegisterClass);
       break;
+    case 't':
+      if (VT == MVT::f32)
+	return RCPair(0U, ARM::SPRRegisterClass);
+      break;
     }
   }
   if (StringRef("{cc}").equals_lower(Constraint))

Modified: llvm/trunk/test/CodeGen/ARM/inlineasm3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/inlineasm3.ll?rev=134220&r1=134219&r2=134220&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/inlineasm3.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/inlineasm3.ll Thu Jun 30 19:30:46 2011
@@ -68,3 +68,23 @@
   %0 = tail call float asm "flds s15, $0", "=x"() nounwind
   ret float %0
 }
+
+; Radar 9307836 & 9119939
+
+define double @t7(double %y) nounwind ssp {
+entry:
+; CHECK: t7
+; CHECK: flds s15, d0
+  %0 = tail call double asm "flds s15, $0", "=x"() nounwind
+  ret double %0
+}
+
+; Radar 9307836 & 9119939
+
+define float @t8(float %y) nounwind ssp {
+entry:
+; CHECK: t8
+; CHECK: flds s15, s0
+  %0 = tail call float asm "flds s15, $0", "=t"() nounwind
+  ret float %0
+}