[llvm-commits] [llvm] r134215 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/inlineasm3.ll

[Eric Christopher]

Author: echristo
Date: Thu Jun 30 19:14:47 2011
New Revision: 134215

URL: http://llvm.org/viewvc/llvm-project?rev=134215&view=rev
Log:
Add support for the 'x' constraint.

Part of rdar://9307836 and rdar://9119939

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/test/CodeGen/ARM/inlineasm3.ll

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=134215&r1=134214&r2=134215&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Jun 30 19:14:47 2011
@@ -7483,6 +7483,7 @@
     case 'l': return C_RegisterClass;
     case 'w': return C_RegisterClass;
     case 'h': return C_RegisterClass;
+    case 'x': return C_RegisterClass;
     }
   } else if (Constraint.size() == 2) {
     switch (Constraint[0]) {
@@ -7555,6 +7556,14 @@
       if (VT.getSizeInBits() == 128)
         return RCPair(0U, ARM::QPRRegisterClass);
       break;
+    case 'x':
+      if (VT == MVT::f32)
+	return RCPair(0U, ARM::SPR_8RegisterClass);
+      if (VT.getSizeInBits() == 64)
+	return RCPair(0U, ARM::DPR_8RegisterClass);
+      if (VT.getSizeInBits() == 128)
+	return RCPair(0U, ARM::QPR_8RegisterClass);
+      break;
     }
   }
   if (StringRef("{cc}").equals_lower(Constraint))

Modified: llvm/trunk/test/CodeGen/ARM/inlineasm3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/inlineasm3.ll?rev=134215&r1=134214&r2=134215&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/inlineasm3.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/inlineasm3.ll Thu Jun 30 19:14:47 2011
@@ -58,3 +58,13 @@
 call void asm sideeffect "flds s15, $0 \0A", "*^Uvm,~{s15}"(float* @k.2126) nounwind
 ret i32 0
 }
+
+; Radar 9307836 & 9119939
+
+define float @t6(float %y) nounwind {
+entry:
+; CHECK: t6
+; CHECK: flds s15, s0
+  %0 = tail call float asm "flds s15, $0", "=x"() nounwind
+  ret float %0
+}