[llvm-commits] [llvm] r134210 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

[Eric Christopher]

Author: echristo
Date: Thu Jun 30 18:50:52 2011
New Revision: 134210

URL: http://llvm.org/viewvc/llvm-project?rev=134210&view=rev
Log:
Rename Pair to RCPair lacking any better naming ideas.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=134210&r1=134209&r2=134210&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Jun 30 18:50:52 2011
@@ -7528,8 +7528,8 @@
   return weight;
 }
 
-typedef std::pair<unsigned, const TargetRegisterClass*> Pair;
-Pair
+typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
+RCPair
 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
                                                 EVT VT) const {
   if (Constraint.size() == 1) {
@@ -7537,23 +7537,23 @@
     switch (Constraint[0]) {
     case 'l': // Low regs or general regs.
       if (Subtarget->isThumb())
-        return Pair(0U, ARM::tGPRRegisterClass);
+        return RCPair(0U, ARM::tGPRRegisterClass);
       else
-        return Pair(0U, ARM::GPRRegisterClass);
+        return RCPair(0U, ARM::GPRRegisterClass);
     case 'h': // High regs or no regs.
       if (Subtarget->isThumb())
-	return Pair(0U, ARM::hGPRRegisterClass);
+	return RCPair(0U, ARM::hGPRRegisterClass);
       else
-	return Pair(0u, static_cast<const TargetRegisterClass*>(0));
+	return RCPair(0u, static_cast<const TargetRegisterClass*>(0));
     case 'r':
-      return Pair(0U, ARM::GPRRegisterClass);
+      return RCPair(0U, ARM::GPRRegisterClass);
     case 'w':
       if (VT == MVT::f32)
-        return Pair(0U, ARM::SPRRegisterClass);
+        return RCPair(0U, ARM::SPRRegisterClass);
       if (VT.getSizeInBits() == 64)
-        return Pair(0U, ARM::DPRRegisterClass);
+        return RCPair(0U, ARM::DPRRegisterClass);
       if (VT.getSizeInBits() == 128)
-        return Pair(0U, ARM::QPRRegisterClass);
+        return RCPair(0U, ARM::QPRRegisterClass);
       break;
     }
   }