[llvm-commits] [llvm] r134203 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMRegisterInfo.td test/CodeGen/Thumb/inlineasm-thumb.ll

[Eric Christopher]

Author: echristo
Date: Thu Jun 30 18:23:01 2011
New Revision: 134203

URL: http://llvm.org/viewvc/llvm-project?rev=134203&view=rev
Log:
Add support for the 'h' constraint.

Part of rdar://9119939

Added:
    llvm/trunk/test/CodeGen/Thumb/inlineasm-thumb.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=134203&r1=134202&r2=134203&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Jun 30 18:23:01 2011
@@ -7482,6 +7482,7 @@
     default:  break;
     case 'l': return C_RegisterClass;
     case 'w': return C_RegisterClass;
+    case 'h': return C_RegisterClass;
     }
   } else if (Constraint.size() == 2) {
     switch (Constraint[0]) {
@@ -7534,11 +7535,16 @@
   if (Constraint.size() == 1) {
     // GCC ARM Constraint Letters
     switch (Constraint[0]) {
-    case 'l':
+    case 'l': // Low regs or general regs.
       if (Subtarget->isThumb())
         return Pair(0U, ARM::tGPRRegisterClass);
       else
         return Pair(0U, ARM::GPRRegisterClass);
+    case 'h': // High regs or no regs.
+      if (Subtarget->isThumb())
+	return Pair(0U, ARM::hGPRRegisterClass);
+      else
+	return Pair(0u, static_cast<const TargetRegisterClass*>(0));
     case 'r':
       return Pair(0U, ARM::GPRRegisterClass);
     case 'w':

Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=134203&r1=134202&r2=134203&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Thu Jun 30 18:23:01 2011
@@ -228,6 +228,9 @@
 // the general GPR register class above (MOV, e.g.)
 def tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)>;
 
+// The high registers in thumb mode, R8-R15.
+def hGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, tGPR)>;
+
 // For tail calls, we can't use callee-saved registers, as they are restored
 // to the saved value before the tail call, which would clobber a call address.
 // Note, getMinimalPhysRegClass(R0) returns tGPR because of the names of

Added: llvm/trunk/test/CodeGen/Thumb/inlineasm-thumb.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/inlineasm-thumb.ll?rev=134203&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb/inlineasm-thumb.ll (added)
+++ llvm/trunk/test/CodeGen/Thumb/inlineasm-thumb.ll Thu Jun 30 18:23:01 2011
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=thumb | FileCheck %s
+define i32 @t1(i32 %x, i32 %y) nounwind {
+entry:
+  ; CHECK: mov r0, r12
+  %0 = tail call i32 asm "mov $0, $1", "=l,h"(i32 %y) nounwind
+  ret i32 %0
+}