[llvm-commits] [llvm] r134130 - /llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp

[Jim Grosbach]

Author: grosbach
Date: Wed Jun 29 21:22:49 2011
New Revision: 134130

URL: http://llvm.org/viewvc/llvm-project?rev=134130&view=rev
Log:
Size reducing SP adjusting t2ADDri needs to check predication.

tADDrSPi is not predicable, so we can't size-reduce a t2ADDri to it if the
predicate is anything other than "always."


Modified:
    llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp

Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=134130&r1=134129&r2=134130&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Wed Jun 29 21:22:49 2011
@@ -491,11 +491,14 @@
     // Try to reduce to tADDrSPi.
     unsigned Imm = MI->getOperand(2).getImm();
     // The immediate must be in range, the destination register must be a low
-    // reg, and the condition flags must not be being set.
+    // reg, the predicate must be "always" and the condition flags must not
+    // be being set.
     if (Imm & 3 || Imm > 1024)
       return false;
     if (!isARMLowRegister(MI->getOperand(0).getReg()))
       return false;
+    if (MI->getOperand(3).getImm() != ARMCC::AL)
+      return false;
     const MCInstrDesc &MCID = MI->getDesc();
     if (MCID.hasOptionalDef() &&
         MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR)