[llvm-commits] [llvm] r134089 - /llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp

[Jakob Stoklund Olesen]

On Jun 29, 2011, at 12:41 PM, Eric Christopher wrote:

> Author: echristo
> Date: Wed Jun 29 14:41:27 2011
> New Revision: 134089
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=134089&view=rev
> Log:
> Add a TODO for the Alpha port inline asm constraints.
> 
> Modified:
>    llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
> 
> Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=134089&r1=134088&r2=134089&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Wed Jun 29 14:41:27 2011
> @@ -835,6 +835,8 @@
>     case 'r':
>       return std::make_pair(0U, Alpha::GPRCRegisterClass);
>     case 'f':
> +      // TODO: Do we need to add the 64-bit register class here when
> +      // it contains the same registers?
>       return std::make_pair(0U, Alpha::F4RCRegisterClass);
>     }
>   }

Probably, since the register class also determines the spill size.

However, the coalescer is very likely to fix this for you. A copy between F4RC and F8RC will be widened to F8RC.

/jakob