[llvm-commits] [llvm] r134101 - /llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp

[Jim Grosbach]

Author: grosbach
Date: Wed Jun 29 17:01:15 2011
New Revision: 134101

URL: http://llvm.org/viewvc/llvm-project?rev=134101&view=rev
Log:
ARM RSCS* don't need explicit TableGen decoder checks.

They've been pseudos for a while now, so the decoder will never see
them in the first place.

Modified:
    llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp

Modified: llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp?rev=134101&r1=134100&r2=134101&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp Wed Jun 29 17:01:15 2011
@@ -1592,10 +1592,6 @@
     // The following special cases are for conflict resolutions.
     //
 
-    // RSCSri and RSCSrs set the 's' bit, but are not predicated.  We are
-    // better off using the generic RSCri and RSCrs instructions.
-    if (Name == "RSCSri" || Name == "RSCSrs") return false;
-
     // A8-598: VEXT
     // Vector Extract extracts elements from the bottom end of the second
     // operand vector and the top end of the first, concatenates them and