[llvm-commits] [llvm] r133922 - in /llvm/trunk: lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/ lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ lib/Target/X86/Disassembler/ lib/Target/X86/InstPrinter/ lib/Target/X86/MCTargetDesc/ lib/Target/XCore/ utils/TableGen/
Evan Cheng
evan.cheng at apple.com
Mon Jun 27 11:32:37 PDT 2011
Author: evancheng
Date: Mon Jun 27 13:32:37 2011
New Revision: 133922
URL: http://llvm.org/viewvc/llvm-project?rev=133922&view=rev
Log:
Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc
into XXXGenRegisterInfo.inc.
Modified:
llvm/trunk/lib/Target/ARM/ARMBaseInfo.h
llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h
llvm/trunk/lib/Target/ARM/CMakeLists.txt
llvm/trunk/lib/Target/ARM/Makefile
llvm/trunk/lib/Target/Alpha/Alpha.h
llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp
llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h
llvm/trunk/lib/Target/Alpha/CMakeLists.txt
llvm/trunk/lib/Target/Alpha/Makefile
llvm/trunk/lib/Target/Blackfin/Blackfin.h
llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp
llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h
llvm/trunk/lib/Target/Blackfin/CMakeLists.txt
llvm/trunk/lib/Target/Blackfin/Makefile
llvm/trunk/lib/Target/CellSPU/CMakeLists.txt
llvm/trunk/lib/Target/CellSPU/Makefile
llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp
llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h
llvm/trunk/lib/Target/CellSPU/SPURegisterNames.h
llvm/trunk/lib/Target/MBlaze/CMakeLists.txt
llvm/trunk/lib/Target/MBlaze/MBlaze.h
llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp
llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h
llvm/trunk/lib/Target/MBlaze/Makefile
llvm/trunk/lib/Target/MSP430/CMakeLists.txt
llvm/trunk/lib/Target/MSP430/MSP430.h
llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp
llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h
llvm/trunk/lib/Target/MSP430/Makefile
llvm/trunk/lib/Target/Mips/CMakeLists.txt
llvm/trunk/lib/Target/Mips/Makefile
llvm/trunk/lib/Target/Mips/Mips.h
llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h
llvm/trunk/lib/Target/PTX/CMakeLists.txt
llvm/trunk/lib/Target/PTX/Makefile
llvm/trunk/lib/Target/PTX/PTX.h
llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp
llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h
llvm/trunk/lib/Target/PowerPC/CMakeLists.txt
llvm/trunk/lib/Target/PowerPC/Makefile
llvm/trunk/lib/Target/PowerPC/PPC.h
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h
llvm/trunk/lib/Target/Sparc/CMakeLists.txt
llvm/trunk/lib/Target/Sparc/Makefile
llvm/trunk/lib/Target/Sparc/Sparc.h
llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp
llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h
llvm/trunk/lib/Target/SystemZ/CMakeLists.txt
llvm/trunk/lib/Target/SystemZ/Makefile
llvm/trunk/lib/Target/SystemZ/SystemZ.h
llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp
llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h
llvm/trunk/lib/Target/X86/CMakeLists.txt
llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp
llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp
llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h
llvm/trunk/lib/Target/X86/Makefile
llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
llvm/trunk/lib/Target/X86/X86RegisterInfo.h
llvm/trunk/lib/Target/XCore/CMakeLists.txt
llvm/trunk/lib/Target/XCore/Makefile
llvm/trunk/lib/Target/XCore/XCore.h
llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp
llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h
llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
llvm/trunk/utils/TableGen/RegisterInfoEmitter.h
llvm/trunk/utils/TableGen/TableGen.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMBaseInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInfo.h?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInfo.h Mon Jun 27 13:32:37 2011
@@ -25,7 +25,8 @@
// Defines symbolic names for ARM registers. This defines a mapping from
// register name to register number.
//
-#include "ARMGenRegisterNames.inc"
+#define GET_REGINFO_ENUM
+#include "ARMGenRegisterInfo.inc"
// Defines symbolic names for the ARM instructions.
//
Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Mon Jun 27 13:32:37 2011
@@ -39,7 +39,9 @@
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/Support/CommandLine.h"
-#include "ARMGenRegisterDesc.inc"
+
+#define GET_REGINFO_MC_DESC
+#define GET_REGINFO_TARGET_DESC
#include "ARMGenRegisterInfo.inc"
using namespace llvm;
Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Mon Jun 27 13:32:37 2011
@@ -16,7 +16,9 @@
#include "ARM.h"
#include "llvm/Target/TargetRegisterInfo.h"
-#include "ARMGenRegisterInfo.h.inc"
+
+#define GET_REGINFO_HEADER
+#include "ARMGenRegisterInfo.inc"
namespace llvm {
class ARMSubtarget;
Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Mon Jun 27 13:32:37 2011
@@ -1,8 +1,5 @@
set(LLVM_TARGET_DEFINITIONS ARM.td)
-tablegen(ARMGenRegisterNames.inc -gen-register-enums)
-tablegen(ARMGenRegisterDesc.inc -gen-register-desc)
-tablegen(ARMGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(ARMGenRegisterInfo.inc -gen-register-info)
tablegen(ARMGenInstrNames.inc -gen-instr-enums)
tablegen(ARMGenInstrInfo.inc -gen-instr-desc)
Modified: llvm/trunk/lib/Target/ARM/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Makefile?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Makefile (original)
+++ llvm/trunk/lib/Target/ARM/Makefile Mon Jun 27 13:32:37 2011
@@ -12,8 +12,7 @@
TARGET = ARM
# Make sure that tblgen is run, first thing.
-BUILT_SOURCES = ARMGenRegisterNames.inc ARMGenRegisterDesc.inc \
- ARMGenRegisterInfo.h.inc ARMGenRegisterInfo.inc \
+BUILT_SOURCES = ARMGenRegisterInfo.inc \
ARMGenInstrNames.inc ARMGenInstrInfo.inc \
ARMGenAsmWriter.inc ARMGenAsmMatcher.inc \
ARMGenDAGISel.inc ARMGenSubtarget.inc \
Modified: llvm/trunk/lib/Target/Alpha/Alpha.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/Alpha.h?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/Alpha.h (original)
+++ llvm/trunk/lib/Target/Alpha/Alpha.h Mon Jun 27 13:32:37 2011
@@ -44,7 +44,9 @@
// Defines symbolic names for Alpha registers. This defines a mapping from
// register name to register number.
//
-#include "AlphaGenRegisterNames.inc"
+
+#define GET_REGINFO_ENUM
+#include "AlphaGenRegisterInfo.inc"
// Defines symbolic names for the Alpha instructions.
//
Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp Mon Jun 27 13:32:37 2011
@@ -33,8 +33,11 @@
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
#include <cstdlib>
-#include "AlphaGenRegisterDesc.inc"
+
+#define GET_REGINFO_MC_DESC
+#define GET_REGINFO_TARGET_DESC
#include "AlphaGenRegisterInfo.inc"
+
using namespace llvm;
AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h Mon Jun 27 13:32:37 2011
@@ -15,7 +15,9 @@
#define ALPHAREGISTERINFO_H
#include "llvm/Target/TargetRegisterInfo.h"
-#include "AlphaGenRegisterInfo.h.inc"
+
+#define GET_REGINFO_HEADER
+#include "AlphaGenRegisterInfo.inc"
namespace llvm {
Modified: llvm/trunk/lib/Target/Alpha/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/CMakeLists.txt?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/Alpha/CMakeLists.txt Mon Jun 27 13:32:37 2011
@@ -1,8 +1,5 @@
set(LLVM_TARGET_DEFINITIONS Alpha.td)
-tablegen(AlphaGenRegisterNames.inc -gen-register-enums)
-tablegen(AlphaGenRegisterDesc.inc -gen-register-desc)
-tablegen(AlphaGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(AlphaGenRegisterInfo.inc -gen-register-info)
tablegen(AlphaGenInstrNames.inc -gen-instr-enums)
tablegen(AlphaGenInstrInfo.inc -gen-instr-desc)
Modified: llvm/trunk/lib/Target/Alpha/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/Makefile?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/Makefile (original)
+++ llvm/trunk/lib/Target/Alpha/Makefile Mon Jun 27 13:32:37 2011
@@ -12,8 +12,7 @@
TARGET = Alpha
# Make sure that tblgen is run, first thing.
-BUILT_SOURCES = AlphaGenRegisterNames.inc AlphaGenRegisterDesc.inc \
- AlphaGenRegisterInfo.h.inc AlphaGenRegisterInfo.inc \
+BUILT_SOURCES = AlphaGenRegisterInfo.inc \
AlphaGenInstrNames.inc AlphaGenInstrInfo.inc \
AlphaGenAsmWriter.inc AlphaGenDAGISel.inc \
AlphaGenCallingConv.inc AlphaGenSubtarget.inc
Modified: llvm/trunk/lib/Target/Blackfin/Blackfin.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/Blackfin.h?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/Blackfin.h (original)
+++ llvm/trunk/lib/Target/Blackfin/Blackfin.h Mon Jun 27 13:32:37 2011
@@ -30,7 +30,8 @@
// Defines symbolic names for Blackfin registers. This defines a mapping from
// register name to register number.
-#include "BlackfinGenRegisterNames.inc"
+#define GET_REGINFO_ENUM
+#include "BlackfinGenRegisterInfo.inc"
// Defines symbolic names for the Blackfin instructions.
#include "BlackfinGenInstrNames.inc"
Modified: llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp Mon Jun 27 13:32:37 2011
@@ -29,8 +29,11 @@
#include "llvm/Type.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
-#include "BlackfinGenRegisterDesc.inc"
+
+#define GET_REGINFO_MC_DESC
+#define GET_REGINFO_TARGET_DESC
#include "BlackfinGenRegisterInfo.inc"
+
using namespace llvm;
BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st,
Modified: llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h Mon Jun 27 13:32:37 2011
@@ -16,7 +16,9 @@
#define BLACKFINREGISTERINFO_H
#include "llvm/Target/TargetRegisterInfo.h"
-#include "BlackfinGenRegisterInfo.h.inc"
+
+#define GET_REGINFO_HEADER
+#include "BlackfinGenRegisterInfo.inc"
namespace llvm {
Modified: llvm/trunk/lib/Target/Blackfin/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/CMakeLists.txt?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/Blackfin/CMakeLists.txt Mon Jun 27 13:32:37 2011
@@ -1,8 +1,5 @@
set(LLVM_TARGET_DEFINITIONS Blackfin.td)
-tablegen(BlackfinGenRegisterNames.inc -gen-register-enums)
-tablegen(BlackfinGenRegisterDesc.inc -gen-register-desc)
-tablegen(BlackfinGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(BlackfinGenRegisterInfo.inc -gen-register-info)
tablegen(BlackfinGenInstrNames.inc -gen-instr-enums)
tablegen(BlackfinGenInstrInfo.inc -gen-instr-desc)
Modified: llvm/trunk/lib/Target/Blackfin/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/Makefile?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/Makefile (original)
+++ llvm/trunk/lib/Target/Blackfin/Makefile Mon Jun 27 13:32:37 2011
@@ -12,9 +12,7 @@
TARGET = Blackfin
# Make sure that tblgen is run, first thing.
-BUILT_SOURCES = BlackfinGenRegisterNames.inc BlackfinGenRegisterDesc.inc \
- BlackfinGenRegisterInfo.h.inc BlackfinGenRegisterInfo.inc \
- BlackfinGenInstrNames.inc \
+BUILT_SOURCES = BlackfinGenRegisterInfo.inc BlackfinGenInstrNames.inc \
BlackfinGenInstrInfo.inc BlackfinGenAsmWriter.inc \
BlackfinGenDAGISel.inc BlackfinGenSubtarget.inc \
BlackfinGenCallingConv.inc BlackfinGenIntrinsics.inc
Modified: llvm/trunk/lib/Target/CellSPU/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/CMakeLists.txt?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/CellSPU/CMakeLists.txt Mon Jun 27 13:32:37 2011
@@ -1,11 +1,8 @@
set(LLVM_TARGET_DEFINITIONS SPU.td)
tablegen(SPUGenInstrNames.inc -gen-instr-enums)
-tablegen(SPUGenRegisterNames.inc -gen-register-enums)
tablegen(SPUGenAsmWriter.inc -gen-asm-writer)
tablegen(SPUGenCodeEmitter.inc -gen-emitter)
-tablegen(SPUGenRegisterDesc.inc -gen-register-desc)
-tablegen(SPUGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(SPUGenRegisterInfo.inc -gen-register-info)
tablegen(SPUGenInstrInfo.inc -gen-instr-desc)
tablegen(SPUGenDAGISel.inc -gen-dag-isel)
Modified: llvm/trunk/lib/Target/CellSPU/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/Makefile?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/Makefile (original)
+++ llvm/trunk/lib/Target/CellSPU/Makefile Mon Jun 27 13:32:37 2011
@@ -10,10 +10,8 @@
LEVEL = ../../..
LIBRARYNAME = LLVMCellSPUCodeGen
TARGET = SPU
-BUILT_SOURCES = SPUGenInstrNames.inc \
+BUILT_SOURCES = SPUGenInstrNames.inc SPUGenRegisterInfo.inc \
SPUGenAsmWriter.inc SPUGenCodeEmitter.inc \
- SPUGenRegisterNames.inc SPUGenRegisterDesc.inc \
- SPUGenRegisterInfo.h.inc SPUGenRegisterInfo.inc \
SPUGenInstrInfo.inc SPUGenDAGISel.inc \
SPUGenSubtarget.inc SPUGenCallingConv.inc
Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp Mon Jun 27 13:32:37 2011
@@ -42,7 +42,9 @@
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
#include <cstdlib>
-#include "SPUGenRegisterDesc.inc"
+
+#define GET_REGINFO_MC_DESC
+#define GET_REGINFO_TARGET_DESC
#include "SPUGenRegisterInfo.inc"
using namespace llvm;
Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h Mon Jun 27 13:32:37 2011
@@ -16,7 +16,9 @@
#define SPU_REGISTERINFO_H
#include "SPU.h"
-#include "SPUGenRegisterInfo.h.inc"
+
+#define GET_REGINFO_HEADER
+#include "SPUGenRegisterInfo.inc"
namespace llvm {
class SPUSubtarget;
Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterNames.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterNames.h?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPURegisterNames.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPURegisterNames.h Mon Jun 27 13:32:37 2011
@@ -13,6 +13,7 @@
// Define symbolic names for Cell registers. This defines a mapping from
// register name to register number.
//
-#include "SPUGenRegisterNames.inc"
+#define GET_REGINFO_ENUM
+#include "SPUGenRegisterInfo.inc"
#endif
Modified: llvm/trunk/lib/Target/MBlaze/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/CMakeLists.txt?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/MBlaze/CMakeLists.txt Mon Jun 27 13:32:37 2011
@@ -1,9 +1,6 @@
set(LLVM_TARGET_DEFINITIONS MBlaze.td)
-tablegen(MBlazeGenRegisterNames.inc -gen-register-enums)
-tablegen(MBlazeGenRegisterDesc.inc -gen-register-desc)
tablegen(MBlazeGenRegisterInfo.h.inc -gen-register-info-header)
-tablegen(MBlazeGenRegisterInfo.inc -gen-register-info)
tablegen(MBlazeGenInstrNames.inc -gen-instr-enums)
tablegen(MBlazeGenInstrInfo.inc -gen-instr-desc)
tablegen(MBlazeGenCodeEmitter.inc -gen-emitter)
Modified: llvm/trunk/lib/Target/MBlaze/MBlaze.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlaze.h?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlaze.h (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlaze.h Mon Jun 27 13:32:37 2011
@@ -39,7 +39,8 @@
// Defines symbolic names for MBlaze registers. This defines a mapping from
// register name to register number.
-#include "MBlazeGenRegisterNames.inc"
+#define GET_REGINFO_ENUM
+#include "MBlazeGenRegisterInfo.inc"
// Defines symbolic names for the MBlaze instructions.
#include "MBlazeGenInstrNames.inc"
Modified: llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp Mon Jun 27 13:32:37 2011
@@ -36,8 +36,11 @@
#include "llvm/Support/raw_ostream.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
-#include "MBlazeGenRegisterDesc.inc"
+
+#define GET_REGINFO_MC_DESC
+#define GET_REGINFO_TARGET_DESC
#include "MBlazeGenRegisterInfo.inc"
+
using namespace llvm;
MBlazeRegisterInfo::
Modified: llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h Mon Jun 27 13:32:37 2011
@@ -17,7 +17,9 @@
#include "MBlaze.h"
#include "llvm/Target/TargetRegisterInfo.h"
-#include "MBlazeGenRegisterInfo.h.inc"
+
+#define GET_REGINFO_HEADER
+#include "MBlazeGenRegisterInfo.inc"
namespace llvm {
class MBlazeSubtarget;
Modified: llvm/trunk/lib/Target/MBlaze/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/Makefile?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/Makefile (original)
+++ llvm/trunk/lib/Target/MBlaze/Makefile Mon Jun 27 13:32:37 2011
@@ -11,9 +11,7 @@
TARGET = MBlaze
# Make sure that tblgen is run, first thing.
-BUILT_SOURCES = MBlazeGenRegisterInfo.h.inc MBlazeGenRegisterNames.inc \
- MBlazeGenRegisterInfo.inc MBlazeGenRegisterDesc.inc \
- MBlazeGenInstrNames.inc \
+BUILT_SOURCES = MBlazeGenRegisterInfo.inc MBlazeGenInstrNames.inc \
MBlazeGenInstrInfo.inc MBlazeGenAsmWriter.inc \
MBlazeGenDAGISel.inc MBlazeGenAsmMatcher.inc \
MBlazeGenCodeEmitter.inc MBlazeGenCallingConv.inc \
Modified: llvm/trunk/lib/Target/MSP430/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/CMakeLists.txt?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/MSP430/CMakeLists.txt Mon Jun 27 13:32:37 2011
@@ -1,8 +1,5 @@
set(LLVM_TARGET_DEFINITIONS MSP430.td)
-tablegen(MSP430GenRegisterNames.inc -gen-register-enums)
-tablegen(MSP430GenRegisterDesc.inc -gen-register-desc)
-tablegen(MSP430GenRegisterInfo.h.inc -gen-register-info-header)
tablegen(MSP430GenRegisterInfo.inc -gen-register-info)
tablegen(MSP430GenInstrNames.inc -gen-instr-enums)
tablegen(MSP430GenInstrInfo.inc -gen-instr-desc)
Modified: llvm/trunk/lib/Target/MSP430/MSP430.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430.h?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430.h (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430.h Mon Jun 27 13:32:37 2011
@@ -47,7 +47,8 @@
// Defines symbolic names for MSP430 registers.
// This defines a mapping from register name to register number.
-#include "MSP430GenRegisterNames.inc"
+#define GET_REGINFO_ENUM
+#include "MSP430GenRegisterInfo.inc"
// Defines symbolic names for the MSP430 instructions.
#include "MSP430GenInstrNames.inc"
Modified: llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp Mon Jun 27 13:32:37 2011
@@ -25,7 +25,9 @@
#include "llvm/Target/TargetOptions.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/Support/ErrorHandling.h"
-#include "MSP430GenRegisterDesc.inc"
+
+#define GET_REGINFO_MC_DESC
+#define GET_REGINFO_TARGET_DESC
#include "MSP430GenRegisterInfo.inc"
using namespace llvm;
Modified: llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h Mon Jun 27 13:32:37 2011
@@ -15,7 +15,9 @@
#define LLVM_TARGET_MSP430REGISTERINFO_H
#include "llvm/Target/TargetRegisterInfo.h"
-#include "MSP430GenRegisterInfo.h.inc"
+
+#define GET_REGINFO_HEADER
+#include "MSP430GenRegisterInfo.inc"
namespace llvm {
Modified: llvm/trunk/lib/Target/MSP430/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/Makefile?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/Makefile (original)
+++ llvm/trunk/lib/Target/MSP430/Makefile Mon Jun 27 13:32:37 2011
@@ -12,9 +12,7 @@
TARGET = MSP430
# Make sure that tblgen is run, first thing.
-BUILT_SOURCES = MSP430GenRegisterInfo.h.inc MSP430GenRegisterNames.inc \
- MSP430GenRegisterInfo.inc MSP430GenRegisterDesc.inc \
- MSP430GenInstrNames.inc \
+BUILT_SOURCES = MSP430GenRegisterInfo.inc MSP430GenInstrNames.inc \
MSP430GenInstrInfo.inc MSP430GenAsmWriter.inc \
MSP430GenDAGISel.inc MSP430GenCallingConv.inc \
MSP430GenSubtarget.inc
Modified: llvm/trunk/lib/Target/Mips/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/CMakeLists.txt?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/Mips/CMakeLists.txt Mon Jun 27 13:32:37 2011
@@ -1,8 +1,5 @@
set(LLVM_TARGET_DEFINITIONS Mips.td)
-tablegen(MipsGenRegisterNames.inc -gen-register-enums)
-tablegen(MipsGenRegisterDesc.inc -gen-register-desc)
-tablegen(MipsGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(MipsGenRegisterInfo.inc -gen-register-info)
tablegen(MipsGenInstrNames.inc -gen-instr-enums)
tablegen(MipsGenInstrInfo.inc -gen-instr-desc)
Modified: llvm/trunk/lib/Target/Mips/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Makefile?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Makefile (original)
+++ llvm/trunk/lib/Target/Mips/Makefile Mon Jun 27 13:32:37 2011
@@ -12,9 +12,7 @@
TARGET = Mips
# Make sure that tblgen is run, first thing.
-BUILT_SOURCES = MipsGenRegisterInfo.h.inc MipsGenRegisterNames.inc \
- MipsGenRegisterInfo.inc MipsGenRegisterDesc.inc \
- MipsGenInstrNames.inc \
+BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrNames.inc \
MipsGenInstrInfo.inc MipsGenAsmWriter.inc \
MipsGenDAGISel.inc MipsGenCallingConv.inc \
MipsGenSubtarget.inc
Modified: llvm/trunk/lib/Target/Mips/Mips.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.h?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips.h (original)
+++ llvm/trunk/lib/Target/Mips/Mips.h Mon Jun 27 13:32:37 2011
@@ -35,7 +35,8 @@
// Defines symbolic names for Mips registers. This defines a mapping from
// register name to register number.
-#include "MipsGenRegisterNames.inc"
+#define GET_REGINFO_ENUM
+#include "MipsGenRegisterInfo.inc"
// Defines symbolic names for the Mips instructions.
#include "MipsGenInstrNames.inc"
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Mon Jun 27 13:32:37 2011
@@ -35,7 +35,9 @@
#include "llvm/Support/raw_ostream.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
-#include "MipsGenRegisterDesc.inc"
+
+#define GET_REGINFO_MC_DESC
+#define GET_REGINFO_TARGET_DESC
#include "MipsGenRegisterInfo.inc"
using namespace llvm;
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h Mon Jun 27 13:32:37 2011
@@ -16,7 +16,9 @@
#include "Mips.h"
#include "llvm/Target/TargetRegisterInfo.h"
-#include "MipsGenRegisterInfo.h.inc"
+
+#define GET_REGINFO_HEADER
+#include "MipsGenRegisterInfo.inc"
namespace llvm {
class MipsSubtarget;
Modified: llvm/trunk/lib/Target/PTX/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/CMakeLists.txt?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/PTX/CMakeLists.txt Mon Jun 27 13:32:37 2011
@@ -5,10 +5,7 @@
tablegen(PTXGenDAGISel.inc -gen-dag-isel)
tablegen(PTXGenInstrInfo.inc -gen-instr-desc)
tablegen(PTXGenInstrNames.inc -gen-instr-enums)
-tablegen(PTXGenRegisterDesc.inc -gen-register-desc)
tablegen(PTXGenRegisterInfo.inc -gen-register-info)
-tablegen(PTXGenRegisterInfo.h.inc -gen-register-info-header)
-tablegen(PTXGenRegisterNames.inc -gen-register-enums)
tablegen(PTXGenSubtarget.inc -gen-subtarget)
add_llvm_target(PTXCodeGen
Modified: llvm/trunk/lib/Target/PTX/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/Makefile?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/Makefile (original)
+++ llvm/trunk/lib/Target/PTX/Makefile Mon Jun 27 13:32:37 2011
@@ -17,10 +17,7 @@
PTXGenDAGISel.inc \
PTXGenInstrInfo.inc \
PTXGenInstrNames.inc \
- PTXGenRegisterDesc.inc \
PTXGenRegisterInfo.inc \
- PTXGenRegisterInfo.h.inc \
- PTXGenRegisterNames.inc \
PTXGenSubtarget.inc
DIRS = TargetInfo
Modified: llvm/trunk/lib/Target/PTX/PTX.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTX.h?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTX.h (original)
+++ llvm/trunk/lib/Target/PTX/PTX.h Mon Jun 27 13:32:37 2011
@@ -47,7 +47,8 @@
} // namespace llvm;
// Defines symbolic names for PTX registers.
-#include "PTXGenRegisterNames.inc"
+#define GET_REGINFO_ENUM
+#include "PTXGenRegisterInfo.inc"
// Defines symbolic names for the PTX instructions.
#include "PTXGenInstrNames.inc"
Modified: llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp Mon Jun 27 13:32:37 2011
@@ -17,11 +17,11 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-using namespace llvm;
-
-#include "PTXGenRegisterDesc.inc"
+#define GET_REGINFO_MC_DESC
+#define GET_REGINFO_TARGET_DESC
#include "PTXGenRegisterInfo.inc"
+using namespace llvm;
PTXRegisterInfo::PTXRegisterInfo(PTXTargetMachine &TM,
const TargetInstrInfo &TII)
Modified: llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h Mon Jun 27 13:32:37 2011
@@ -17,7 +17,8 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/ADT/BitVector.h"
-#include "PTXGenRegisterInfo.h.inc"
+#define GET_REGINFO_HEADER
+#include "PTXGenRegisterInfo.inc"
namespace llvm {
class PTXTargetMachine;
Modified: llvm/trunk/lib/Target/PowerPC/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/CMakeLists.txt?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/PowerPC/CMakeLists.txt Mon Jun 27 13:32:37 2011
@@ -1,12 +1,9 @@
set(LLVM_TARGET_DEFINITIONS PPC.td)
tablegen(PPCGenInstrNames.inc -gen-instr-enums)
-tablegen(PPCGenRegisterNames.inc -gen-register-enums)
tablegen(PPCGenAsmWriter.inc -gen-asm-writer)
tablegen(PPCGenCodeEmitter.inc -gen-emitter)
tablegen(PPCGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
-tablegen(PPCGenRegisterDesc.inc -gen-register-desc)
-tablegen(PPCGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(PPCGenRegisterInfo.inc -gen-register-info)
tablegen(PPCGenInstrInfo.inc -gen-instr-desc)
tablegen(PPCGenDAGISel.inc -gen-dag-isel)
Modified: llvm/trunk/lib/Target/PowerPC/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/Makefile?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/Makefile (original)
+++ llvm/trunk/lib/Target/PowerPC/Makefile Mon Jun 27 13:32:37 2011
@@ -12,10 +12,8 @@
TARGET = PPC
# Make sure that tblgen is run, first thing.
-BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterNames.inc \
+BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterInfo.inc \
PPCGenAsmWriter.inc PPCGenCodeEmitter.inc \
- PPCGenRegisterDesc.inc \
- PPCGenRegisterInfo.h.inc PPCGenRegisterInfo.inc \
PPCGenInstrInfo.inc PPCGenDAGISel.inc \
PPCGenSubtarget.inc PPCGenCallingConv.inc \
PPCGenMCCodeEmitter.inc
Modified: llvm/trunk/lib/Target/PowerPC/PPC.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPC.h?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPC.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPC.h Mon Jun 27 13:32:37 2011
@@ -84,7 +84,8 @@
// Defines symbolic names for PowerPC registers. This defines a mapping from
// register name to register number.
//
-#include "PPCGenRegisterNames.inc"
+#define GET_REGINFO_ENUM
+#include "PPCGenRegisterInfo.inc"
// Defines symbolic names for the PowerPC instructions.
//
Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Jun 27 13:32:37 2011
@@ -43,7 +43,9 @@
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
#include <cstdlib>
-#include "PPCGenRegisterDesc.inc"
+
+#define GET_REGINFO_MC_DESC
+#define GET_REGINFO_TARGET_DESC
#include "PPCGenRegisterInfo.inc"
// FIXME (64-bit): Eventually enable by default.
Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h Mon Jun 27 13:32:37 2011
@@ -16,9 +16,11 @@
#define POWERPC32_REGISTERINFO_H
#include "PPC.h"
-#include "PPCGenRegisterInfo.h.inc"
#include <map>
+#define GET_REGINFO_HEADER
+#include "PPCGenRegisterInfo.inc"
+
namespace llvm {
class PPCSubtarget;
class TargetInstrInfo;
Modified: llvm/trunk/lib/Target/Sparc/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/CMakeLists.txt?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/Sparc/CMakeLists.txt Mon Jun 27 13:32:37 2011
@@ -1,8 +1,5 @@
set(LLVM_TARGET_DEFINITIONS Sparc.td)
-tablegen(SparcGenRegisterNames.inc -gen-register-enums)
-tablegen(SparcGenRegisterDesc.inc -gen-register-desc)
-tablegen(SparcGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(SparcGenRegisterInfo.inc -gen-register-info)
tablegen(SparcGenInstrNames.inc -gen-instr-enums)
tablegen(SparcGenInstrInfo.inc -gen-instr-desc)
Modified: llvm/trunk/lib/Target/Sparc/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/Makefile?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/Makefile (original)
+++ llvm/trunk/lib/Target/Sparc/Makefile Mon Jun 27 13:32:37 2011
@@ -12,9 +12,7 @@
TARGET = Sparc
# Make sure that tblgen is run, first thing.
-BUILT_SOURCES = SparcGenRegisterInfo.h.inc SparcGenRegisterNames.inc \
- SparcGenRegisterInfo.inc SparcGenRegisterDesc.inc \
- SparcGenInstrNames.inc \
+BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrNames.inc \
SparcGenInstrInfo.inc SparcGenAsmWriter.inc \
SparcGenDAGISel.inc SparcGenSubtarget.inc SparcGenCallingConv.inc
Modified: llvm/trunk/lib/Target/Sparc/Sparc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/Sparc.h?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/Sparc.h (original)
+++ llvm/trunk/lib/Target/Sparc/Sparc.h Mon Jun 27 13:32:37 2011
@@ -36,7 +36,8 @@
// Defines symbolic names for Sparc registers. This defines a mapping from
// register name to register number.
//
-#include "SparcGenRegisterNames.inc"
+#define GET_REGINFO_ENUM
+#include "SparcGenRegisterInfo.inc"
// Defines symbolic names for the Sparc instructions.
//
Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp Mon Jun 27 13:32:37 2011
@@ -23,8 +23,11 @@
#include "llvm/Type.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
-#include "SparcGenRegisterDesc.inc"
+
+#define GET_REGINFO_MC_DESC
+#define GET_REGINFO_TARGET_DESC
#include "SparcGenRegisterInfo.inc"
+
using namespace llvm;
SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h Mon Jun 27 13:32:37 2011
@@ -15,7 +15,9 @@
#define SPARCREGISTERINFO_H
#include "llvm/Target/TargetRegisterInfo.h"
-#include "SparcGenRegisterInfo.h.inc"
+
+#define GET_REGINFO_HEADER
+#include "SparcGenRegisterInfo.inc"
namespace llvm {
Modified: llvm/trunk/lib/Target/SystemZ/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/CMakeLists.txt?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/SystemZ/CMakeLists.txt Mon Jun 27 13:32:37 2011
@@ -1,8 +1,5 @@
set(LLVM_TARGET_DEFINITIONS SystemZ.td)
-tablegen(SystemZGenRegisterNames.inc -gen-register-enums)
-tablegen(SystemZGenRegisterDesc.inc -gen-register-desc)
-tablegen(SystemZGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(SystemZGenRegisterInfo.inc -gen-register-info)
tablegen(SystemZGenInstrNames.inc -gen-instr-enums)
tablegen(SystemZGenInstrInfo.inc -gen-instr-desc)
Modified: llvm/trunk/lib/Target/SystemZ/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/Makefile?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/Makefile (original)
+++ llvm/trunk/lib/Target/SystemZ/Makefile Mon Jun 27 13:32:37 2011
@@ -12,9 +12,7 @@
TARGET = SystemZ
# Make sure that tblgen is run, first thing.
-BUILT_SOURCES = SystemZGenRegisterInfo.h.inc SystemZGenRegisterNames.inc \
- SystemZGenRegisterInfo.inc SystemZGenRegisterDesc.inc \
- SystemZGenInstrNames.inc \
+BUILT_SOURCES = SystemZGenRegisterInfo.inc SystemZGenInstrNames.inc \
SystemZGenInstrInfo.inc SystemZGenAsmWriter.inc \
SystemZGenDAGISel.inc SystemZGenSubtarget.inc SystemZGenCallingConv.inc
Modified: llvm/trunk/lib/Target/SystemZ/SystemZ.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZ.h?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZ.h (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZ.h Mon Jun 27 13:32:37 2011
@@ -53,7 +53,8 @@
// Defines symbolic names for SystemZ registers.
// This defines a mapping from register name to register number.
-#include "SystemZGenRegisterNames.inc"
+#define GET_REGINFO_ENUM
+#include "SystemZGenRegisterInfo.inc"
// Defines symbolic names for the SystemZ instructions.
#include "SystemZGenInstrNames.inc"
Modified: llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp Mon Jun 27 13:32:37 2011
@@ -25,8 +25,11 @@
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/ADT/BitVector.h"
-#include "SystemZGenRegisterDesc.inc"
+
+#define GET_REGINFO_MC_DESC
+#define GET_REGINFO_TARGET_DESC
#include "SystemZGenRegisterInfo.inc"
+
using namespace llvm;
SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm,
Modified: llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h Mon Jun 27 13:32:37 2011
@@ -15,7 +15,9 @@
#define SystemZREGISTERINFO_H
#include "llvm/Target/TargetRegisterInfo.h"
-#include "SystemZGenRegisterInfo.h.inc"
+
+#define GET_REGINFO_HEADER
+#include "SystemZGenRegisterInfo.inc"
namespace llvm {
Modified: llvm/trunk/lib/Target/X86/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/CMakeLists.txt?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/X86/CMakeLists.txt Mon Jun 27 13:32:37 2011
@@ -1,8 +1,5 @@
set(LLVM_TARGET_DEFINITIONS X86.td)
-tablegen(X86GenRegisterNames.inc -gen-register-enums)
-tablegen(X86GenRegisterDesc.inc -gen-register-desc)
-tablegen(X86GenRegisterInfo.h.inc -gen-register-info-header)
tablegen(X86GenRegisterInfo.inc -gen-register-info)
tablegen(X86GenDisassemblerTables.inc -gen-disassembler)
tablegen(X86GenInstrNames.inc -gen-instr-enums)
Modified: llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp (original)
+++ llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp Mon Jun 27 13:32:37 2011
@@ -26,7 +26,8 @@
#include "llvm/Support/MemoryObject.h"
#include "llvm/Support/raw_ostream.h"
-#include "X86GenRegisterNames.inc"
+#define GET_REGINFO_ENUM
+#include "X86GenRegisterInfo.inc"
#include "X86GenEDInfo.inc"
using namespace llvm;
Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp Mon Jun 27 13:32:37 2011
@@ -27,12 +27,11 @@
using namespace llvm;
// Include the auto-generated portion of the assembly writer.
+#define GET_REGINFO_ENUM
+#include "X86GenRegisterInfo.inc"
#define GET_INSTRUCTION_NAME
#define PRINT_ALIAS_INSTR
-#include "X86GenRegisterNames.inc"
#include "X86GenAsmWriter.inc"
-#undef PRINT_ALIAS_INSTR
-#undef GET_INSTRUCTION_NAME
X86ATTInstPrinter::X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI)
: MCInstPrinter(MAI) {
Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp Mon Jun 27 13:32:37 2011
@@ -14,7 +14,9 @@
#include "X86TargetDesc.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Target/TargetRegistry.h"
-#include "X86GenRegisterDesc.inc"
+
+#define GET_REGINFO_MC_DESC
+#include "X86GenRegisterInfo.inc"
using namespace llvm;
MCRegisterInfo *createX86MCRegisterInfo() {
Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h Mon Jun 27 13:32:37 2011
@@ -23,6 +23,7 @@
// Defines symbolic names for X86 registers. This defines a mapping from
// register name to register number.
//
-#include "X86GenRegisterNames.inc"
+#define GET_REGINFO_ENUM
+#include "X86GenRegisterInfo.inc"
#endif
Modified: llvm/trunk/lib/Target/X86/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Makefile?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Makefile (original)
+++ llvm/trunk/lib/Target/X86/Makefile Mon Jun 27 13:32:37 2011
@@ -12,8 +12,7 @@
TARGET = X86
# Make sure that tblgen is run, first thing.
-BUILT_SOURCES = X86GenRegisterNames.inc X86GenRegisterDesc.inc \
- X86GenRegisterInfo.h.inc X86GenRegisterInfo.inc \
+BUILT_SOURCES = X86GenRegisterInfo.inc \
X86GenInstrNames.inc X86GenInstrInfo.inc \
X86GenAsmWriter.inc X86GenAsmMatcher.inc \
X86GenAsmWriter1.inc X86GenDAGISel.inc \
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Mon Jun 27 13:32:37 2011
@@ -39,8 +39,11 @@
#include "llvm/ADT/STLExtras.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/CommandLine.h"
-#include "X86GenRegisterDesc.inc"
+
+#define GET_REGINFO_MC_DESC
+#define GET_REGINFO_TARGET_DESC
#include "X86GenRegisterInfo.inc"
+
using namespace llvm;
cl::opt<bool>
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.h?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.h Mon Jun 27 13:32:37 2011
@@ -15,7 +15,9 @@
#define X86REGISTERINFO_H
#include "llvm/Target/TargetRegisterInfo.h"
-#include "X86GenRegisterInfo.h.inc"
+
+#define GET_REGINFO_HEADER
+#include "X86GenRegisterInfo.inc"
namespace llvm {
class Type;
Modified: llvm/trunk/lib/Target/XCore/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/CMakeLists.txt?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/XCore/CMakeLists.txt Mon Jun 27 13:32:37 2011
@@ -1,8 +1,5 @@
set(LLVM_TARGET_DEFINITIONS XCore.td)
-tablegen(XCoreGenRegisterNames.inc -gen-register-enums)
-tablegen(XCoreGenRegisterDesc.inc -gen-register-desc)
-tablegen(XCoreGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(XCoreGenRegisterInfo.inc -gen-register-info)
tablegen(XCoreGenInstrNames.inc -gen-instr-enums)
tablegen(XCoreGenInstrInfo.inc -gen-instr-desc)
Modified: llvm/trunk/lib/Target/XCore/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/Makefile?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/Makefile (original)
+++ llvm/trunk/lib/Target/XCore/Makefile Mon Jun 27 13:32:37 2011
@@ -12,9 +12,7 @@
TARGET = XCore
# Make sure that tblgen is run, first thing.
-BUILT_SOURCES = XCoreGenRegisterInfo.h.inc XCoreGenRegisterNames.inc \
- XCoreGenRegisterInfo.inc XCoreGenRegisterDesc.inc \
- XCoreGenInstrNames.inc \
+BUILT_SOURCES = XCoreGenRegisterInfo.inc XCoreGenInstrNames.inc \
XCoreGenInstrInfo.inc XCoreGenAsmWriter.inc \
XCoreGenDAGISel.inc XCoreGenCallingConv.inc \
XCoreGenSubtarget.inc
Modified: llvm/trunk/lib/Target/XCore/XCore.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCore.h?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCore.h (original)
+++ llvm/trunk/lib/Target/XCore/XCore.h Mon Jun 27 13:32:37 2011
@@ -32,7 +32,8 @@
// Defines symbolic names for XCore registers. This defines a mapping from
// register name to register number.
//
-#include "XCoreGenRegisterNames.inc"
+#define GET_REGINFO_ENUM
+#include "XCoreGenRegisterInfo.inc"
// Defines symbolic names for the XCore instructions.
//
Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp Mon Jun 27 13:32:37 2011
@@ -32,8 +32,11 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "XCoreGenRegisterDesc.inc"
+
+#define GET_REGINFO_MC_DESC
+#define GET_REGINFO_TARGET_DESC
#include "XCoreGenRegisterInfo.inc"
+
using namespace llvm;
XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h Mon Jun 27 13:32:37 2011
@@ -15,7 +15,9 @@
#define XCOREREGISTERINFO_H
#include "llvm/Target/TargetRegisterInfo.h"
-#include "XCoreGenRegisterInfo.h.inc"
+
+#define GET_REGINFO_HEADER
+#include "XCoreGenRegisterInfo.inc"
namespace llvm {
Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Mon Jun 27 13:32:37 2011
@@ -25,14 +25,18 @@
using namespace llvm;
// runEnums - Print out enum values for all of the registers.
-void RegisterInfoEmitter::runEnums(raw_ostream &OS) {
- CodeGenTarget Target(Records);
- CodeGenRegBank &Bank = Target.getRegBank();
+void
+RegisterInfoEmitter::runEnums(raw_ostream &OS,
+ CodeGenTarget &Target, CodeGenRegBank &Bank) {
const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
EmitSourceFileHeader("Target Register Enum Values", OS);
+
+ OS << "\n#ifdef GET_REGINFO_ENUM\n";
+ OS << "#undef GET_REGINFO_ENUM\n";
+
OS << "namespace llvm {\n\n";
if (!Namespace.empty())
@@ -63,12 +67,33 @@
if (!Namespace.empty())
OS << "}\n";
}
+
+ const std::vector<CodeGenRegisterClass> &RegisterClasses =
+ Target.getRegisterClasses();
+
+ if (!RegisterClasses.empty()) {
+ OS << "\n// Register classes\n";
+ OS << "namespace " << RegisterClasses[0].Namespace << " {\n";
+ OS << "enum {\n";
+ for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
+ if (i) OS << ",\n";
+ OS << " " << RegisterClasses[i].getName() << "RegClassID";
+ OS << " = " << i;
+ }
+ OS << "\n };\n";
+ OS << "}\n";
+ }
+
OS << "} // End llvm namespace \n";
+ OS << "#endif // GET_REGINFO_ENUM\n\n";
}
-void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
+void RegisterInfoEmitter::runHeader(raw_ostream &OS, CodeGenTarget &Target) {
EmitSourceFileHeader("Register Information Header Fragment", OS);
- CodeGenTarget Target(Records);
+
+ OS << "\n#ifdef GET_REGINFO_HEADER\n";
+ OS << "#undef GET_REGINFO_HEADER\n";
+
const std::string &TargetName = Target.getName();
std::string ClassName = TargetName + "GenRegisterInfo";
@@ -100,14 +125,6 @@
OS << "namespace " << RegisterClasses[0].Namespace
<< " { // Register classes\n";
- OS << " enum {\n";
- for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
- if (i) OS << ",\n";
- OS << " " << RegisterClasses[i].getName() << "RegClassID";
- OS << " = " << i;
- }
- OS << "\n };\n\n";
-
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
const CodeGenRegisterClass &RC = RegisterClasses[i];
const std::string &Name = RC.getName();
@@ -129,17 +146,125 @@
OS << "} // end of namespace " << TargetName << "\n\n";
}
OS << "} // End llvm namespace \n";
+ OS << "#endif // GET_REGINFO_HEADER\n\n";
}
//
-// RegisterInfoEmitter::run - Main register file description emitter.
+// runMCDesc - Print out MC register descriptions.
//
-void RegisterInfoEmitter::run(raw_ostream &OS) {
- CodeGenTarget Target(Records);
- CodeGenRegBank &RegBank = Target.getRegBank();
- RegBank.computeDerivedInfo();
+void
+RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
+ CodeGenRegBank &RegBank) {
+ EmitSourceFileHeader("MC Register Information", OS);
+
+ OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
+ OS << "#undef GET_REGINFO_MC_DESC\n";
+
+ std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
+ RegBank.computeOverlaps(Overlaps);
+
+ OS << "namespace llvm {\n\n";
+
+ const std::string &TargetName = Target.getName();
+ std::string ClassName = TargetName + "GenMCRegisterInfo";
+ OS << "struct " << ClassName << " : public MCRegisterInfo {\n"
+ << " explicit " << ClassName << "(const MCRegisterDesc *D);\n";
+ OS << "};\n";
+
+ OS << "\nnamespace {\n";
+
+ const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
+
+ // Emit an overlap list for all registers.
+ for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+ const CodeGenRegister *Reg = Regs[i];
+ const CodeGenRegister::Set &O = Overlaps[Reg];
+ // Move Reg to the front so TRI::getAliasSet can share the list.
+ OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { "
+ << getQualifiedName(Reg->TheDef) << ", ";
+ for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
+ I != E; ++I)
+ if (*I != Reg)
+ OS << getQualifiedName((*I)->TheDef) << ", ";
+ OS << "0 };\n";
+ }
+
+ // Emit the empty sub-registers list
+ OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
+ // Loop over all of the registers which have sub-registers, emitting the
+ // sub-registers list to memory.
+ for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+ const CodeGenRegister &Reg = *Regs[i];
+ if (Reg.getSubRegs().empty())
+ continue;
+ // getSubRegs() orders by SubRegIndex. We want a topological order.
+ SetVector<CodeGenRegister*> SR;
+ Reg.addSubRegsPreOrder(SR);
+ OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
+ for (unsigned j = 0, je = SR.size(); j != je; ++j)
+ OS << getQualifiedName(SR[j]->TheDef) << ", ";
+ OS << "0 };\n";
+ }
+
+ // Emit the empty super-registers list
+ OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
+ // Loop over all of the registers which have super-registers, emitting the
+ // super-registers list to memory.
+ for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+ const CodeGenRegister &Reg = *Regs[i];
+ const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
+ if (SR.empty())
+ continue;
+ OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { ";
+ for (unsigned j = 0, je = SR.size(); j != je; ++j)
+ OS << getQualifiedName(SR[j]->TheDef) << ", ";
+ OS << "0 };\n";
+ }
+
+ OS << "\n const MCRegisterDesc " << TargetName
+ << "RegDesc[] = { // Descriptors\n";
+ OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
+
+ // Now that register alias and sub-registers sets have been emitted, emit the
+ // register descriptors now.
+ for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+ const CodeGenRegister &Reg = *Regs[i];
+ OS << " { \"";
+ OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
+ if (!Reg.getSubRegs().empty())
+ OS << Reg.getName() << "_SubRegsSet,\t";
+ else
+ OS << "Empty_SubRegsSet,\t";
+ if (!Reg.getSuperRegs().empty())
+ OS << Reg.getName() << "_SuperRegsSet";
+ else
+ OS << "Empty_SuperRegsSet";
+ OS << " },\n";
+ }
+ OS << " };\n"; // End of register descriptors...
+
+ OS << "}\n\n"; // End of anonymous namespace...
+
+ // MCRegisterInfo initialization routine.
+ OS << "static inline void Init" << TargetName
+ << "MCRegisterInfo(MCRegisterInfo *RI) {\n";
+ OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
+ << Regs.size()+1 << ");\n}\n\n";
+
+ OS << "} // End llvm namespace \n";
+ OS << "#endif // GET_REGINFO_MC_DESC\n\n";
+}
- EmitSourceFileHeader("Register Information Source Fragment", OS);
+//
+// runTargetDesc - Output the target register and register file descriptions.
+//
+void
+RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
+ CodeGenRegBank &RegBank){
+ EmitSourceFileHeader("Target Register and Register Classes Information", OS);
+
+ OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
+ OS << "#undef GET_REGINFO_TARGET_DESC\n";
OS << "namespace llvm {\n\n";
@@ -614,102 +739,16 @@
OS << " };\n}\n\n";
OS << "} // End llvm namespace \n";
+ OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
}
-void RegisterInfoEmitter::runDesc(raw_ostream &OS) {
+void RegisterInfoEmitter::run(raw_ostream &OS) {
CodeGenTarget Target(Records);
CodeGenRegBank &RegBank = Target.getRegBank();
RegBank.computeDerivedInfo();
- std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
- RegBank.computeOverlaps(Overlaps);
-
- OS << "namespace llvm {\n\n";
-
- const std::string &TargetName = Target.getName();
- std::string ClassName = TargetName + "GenMCRegisterInfo";
- OS << "struct " << ClassName << " : public MCRegisterInfo {\n"
- << " explicit " << ClassName << "(const MCRegisterDesc *D);\n";
- OS << "};\n";
- OS << "\nnamespace {\n";
-
- const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
-
- // Emit an overlap list for all registers.
- for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
- const CodeGenRegister *Reg = Regs[i];
- const CodeGenRegister::Set &O = Overlaps[Reg];
- // Move Reg to the front so TRI::getAliasSet can share the list.
- OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { "
- << getQualifiedName(Reg->TheDef) << ", ";
- for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
- I != E; ++I)
- if (*I != Reg)
- OS << getQualifiedName((*I)->TheDef) << ", ";
- OS << "0 };\n";
- }
-
- // Emit the empty sub-registers list
- OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
- // Loop over all of the registers which have sub-registers, emitting the
- // sub-registers list to memory.
- for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
- const CodeGenRegister &Reg = *Regs[i];
- if (Reg.getSubRegs().empty())
- continue;
- // getSubRegs() orders by SubRegIndex. We want a topological order.
- SetVector<CodeGenRegister*> SR;
- Reg.addSubRegsPreOrder(SR);
- OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
- for (unsigned j = 0, je = SR.size(); j != je; ++j)
- OS << getQualifiedName(SR[j]->TheDef) << ", ";
- OS << "0 };\n";
- }
-
- // Emit the empty super-registers list
- OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
- // Loop over all of the registers which have super-registers, emitting the
- // super-registers list to memory.
- for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
- const CodeGenRegister &Reg = *Regs[i];
- const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
- if (SR.empty())
- continue;
- OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { ";
- for (unsigned j = 0, je = SR.size(); j != je; ++j)
- OS << getQualifiedName(SR[j]->TheDef) << ", ";
- OS << "0 };\n";
- }
-
- OS << "\n const MCRegisterDesc " << TargetName
- << "RegDesc[] = { // Descriptors\n";
- OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
-
- // Now that register alias and sub-registers sets have been emitted, emit the
- // register descriptors now.
- for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
- const CodeGenRegister &Reg = *Regs[i];
- OS << " { \"";
- OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
- if (!Reg.getSubRegs().empty())
- OS << Reg.getName() << "_SubRegsSet,\t";
- else
- OS << "Empty_SubRegsSet,\t";
- if (!Reg.getSuperRegs().empty())
- OS << Reg.getName() << "_SuperRegsSet";
- else
- OS << "Empty_SuperRegsSet";
- OS << " },\n";
- }
- OS << " };\n"; // End of register descriptors...
-
- OS << "}\n\n"; // End of anonymous namespace...
-
- // MCRegisterInfo initialization routine.
- OS << "static inline void Init" << TargetName
- << "MCRegisterInfo(MCRegisterInfo *RI) {\n";
- OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
- << Regs.size()+1 << ");\n}\n\n";
-
- OS << "} // End llvm namespace \n";
+ runEnums(OS, Target, RegBank);
+ runHeader(OS, Target);
+ runMCDesc(OS, Target, RegBank);
+ runTargetDesc(OS, Target, RegBank);
}
Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.h?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.h (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.h Mon Jun 27 13:32:37 2011
@@ -20,22 +20,28 @@
namespace llvm {
+class CodeGenRegBank;
+class CodeGenTarget;
+
class RegisterInfoEmitter : public TableGenBackend {
RecordKeeper &Records;
public:
RegisterInfoEmitter(RecordKeeper &R) : Records(R) {}
- // run - Output the register file description, returning true on failure.
- void run(raw_ostream &o);
+ // runEnums - Print out enum values for all of the registers.
+ void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
// runHeader - Emit a header fragment for the register info emitter.
- void runHeader(raw_ostream &o);
+ void runHeader(raw_ostream &o, CodeGenTarget &Target);
- // runEnums - Print out enum values for all of the registers.
- void runEnums(raw_ostream &o);
+ // runMCDesc - Print out MC register descriptions.
+ void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
+
+ // runTargetDesc - Output the target register and register file descriptions.
+ void runTargetDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
- // runDesc - Print out register descriptions.
- void runDesc(raw_ostream &o);
+ // run - Output the register file description.
+ void run(raw_ostream &o);
};
} // End llvm namespace
Modified: llvm/trunk/utils/TableGen/TableGen.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGen.cpp?rev=133922&r1=133921&r2=133922&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/TableGen.cpp (original)
+++ llvm/trunk/utils/TableGen/TableGen.cpp Mon Jun 27 13:32:37 2011
@@ -54,7 +54,7 @@
enum ActionType {
PrintRecords,
GenEmitter,
- GenRegisterEnums, GenRegisterDesc, GenRegisterInfo, GenRegisterInfoHeader,
+ GenRegisterInfo,
GenInstrEnums, GenInstrs, GenAsmWriter, GenAsmMatcher,
GenARMDecoder,
GenDisassembler,
@@ -93,14 +93,8 @@
"Print all records to stdout (default)"),
clEnumValN(GenEmitter, "gen-emitter",
"Generate machine code emitter"),
- clEnumValN(GenRegisterEnums, "gen-register-enums",
- "Generate enum values for registers"),
- clEnumValN(GenRegisterDesc, "gen-register-desc",
- "Generate register descriptions"),
clEnumValN(GenRegisterInfo, "gen-register-info",
- "Generate registers & reg-classes info"),
- clEnumValN(GenRegisterInfoHeader, "gen-register-info-header",
- "Generate registers & reg-classes info header"),
+ "Generate registers and register classes info"),
clEnumValN(GenInstrEnums, "gen-instr-enums",
"Generate enum values for instructions"),
clEnumValN(GenInstrs, "gen-instr-desc",
@@ -263,18 +257,9 @@
case GenEmitter:
CodeEmitterGen(Records).run(Out.os());
break;
- case GenRegisterEnums:
- RegisterInfoEmitter(Records).runEnums(Out.os());
- break;
- case GenRegisterDesc:
- RegisterInfoEmitter(Records).runDesc(Out.os());
- break;
case GenRegisterInfo:
RegisterInfoEmitter(Records).run(Out.os());
break;
- case GenRegisterInfoHeader:
- RegisterInfoEmitter(Records).runHeader(Out.os());
- break;
case GenInstrEnums:
InstrEnumEmitter(Records).run(Out.os());
break;
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