[llvm-commits] [llvm] r133845 - in /llvm/trunk: include/llvm/MC/MCRegisterInfo.h include/llvm/Target/TargetRegisterInfo.h utils/TableGen/RegisterInfoEmitter.cpp

[Evan Cheng]

Author: evancheng
Date: Fri Jun 24 18:44:48 2011
New Revision: 133845

URL: http://llvm.org/viewvc/llvm-project?rev=133845&view=rev
Log:
Rename TargetRegisterDesc to MCRegisterDesc

Modified:
    llvm/trunk/include/llvm/MC/MCRegisterInfo.h
    llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
    llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp

Modified: llvm/trunk/include/llvm/MC/MCRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCRegisterInfo.h?rev=133845&r1=133844&r2=133845&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/MC/MCRegisterInfo.h Fri Jun 24 18:44:48 2011
@@ -20,7 +20,7 @@
 
 namespace llvm {
 
-/// TargetRegisterDesc - This record contains all of the information known about
+/// MCRegisterDesc - This record contains all of the information known about
 /// a particular register.  The Overlaps field contains a pointer to a zero
 /// terminated array of registers that this register aliases, starting with
 /// itself. This is needed for architectures like X86 which have AL alias AX
@@ -38,7 +38,7 @@
 };
 
 /// MCRegisterInfo base class - We assume that the target defines a static
-/// array of TargetRegisterDesc objects that represent all of the machine
+/// array of MCRegisterDesc objects that represent all of the machine
 /// registers that the target has.  As such, we simply have to track a pointer
 /// to this array so that we can turn register number into a register
 /// descriptor.

Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=133845&r1=133844&r2=133845&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Fri Jun 24 18:44:48 2011
@@ -256,9 +256,6 @@
   bool isAllocatable() const { return Allocatable; }
 };
 
-/// TargetRegisterDesc - It's just an alias of MCRegisterDesc.
-typedef MCRegisterDesc TargetRegisterDesc;
-
 /// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about
 /// registers. These are used by codegen, not by MC.
 struct TargetRegisterInfoDesc {

Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=133845&r1=133844&r2=133845&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Fri Jun 24 18:44:48 2011
@@ -79,7 +79,7 @@
 
   OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
      << "  explicit " << ClassName
-     << "(const TargetRegisterDesc *D, const TargetRegisterInfoDesc *ID, "
+     << "(const MCRegisterDesc *D, const TargetRegisterInfoDesc *ID, "
      << "int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
      << "  virtual int getDwarfRegNumFull(unsigned RegNum, "
      << "unsigned Flavour) const;\n"
@@ -518,7 +518,7 @@
 
   // Emit the constructor of the class...
   OS << ClassName << "::" << ClassName
-     << "(const TargetRegisterDesc *D, const TargetRegisterInfoDesc *ID, "
+     << "(const MCRegisterDesc *D, const TargetRegisterInfoDesc *ID, "
      << "int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
      << "  : TargetRegisterInfo(ID"
      << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"