[llvm-commits] [llvm] r133811 - in /llvm/trunk: lib/Target/Mips/MipsISelLowering.cpp test/CodeGen/Mips/alloca.ll test/CodeGen/Mips/i64arg.ll test/CodeGen/Mips/largeimmprinting.ll
Akira Hatanaka
ahatanak at gmail.com
Fri Jun 24 12:01:25 PDT 2011
Author: ahatanak
Date: Fri Jun 24 14:01:25 2011
New Revision: 133811
URL: http://llvm.org/viewvc/llvm-project?rev=133811&view=rev
Log:
Change the chain input of nodes that load the address of a function. This change
enables SelectionDAG::getLoad at MipsISelLowering.cpp:1914 to return a
pre-existing node instead of redundantly create a new node every time it is
called.
Modified:
llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
llvm/trunk/test/CodeGen/Mips/alloca.ll
llvm/trunk/test/CodeGen/Mips/i64arg.ll
llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=133811&r1=133810&r2=133811&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Fri Jun 24 14:01:25 2011
@@ -1911,7 +1911,7 @@
if (LoadSymAddr) {
// Load callee address
Callee = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, Callee);
- SDValue LoadValue = DAG.getLoad(MVT::i32, dl, Chain, Callee,
+ SDValue LoadValue = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), Callee,
MachinePointerInfo::getGOT(),
false, false, 0);
@@ -1921,9 +1921,6 @@
Callee = DAG.getNode(ISD::ADD, dl, MVT::i32, LoadValue, Lo);
} else
Callee = LoadValue;
-
- // Use chain output from LoadValue
- Chain = LoadValue.getValue(1);
}
// copy to T9
Modified: llvm/trunk/test/CodeGen/Mips/alloca.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/alloca.ll?rev=133811&r1=133810&r2=133811&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/alloca.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/alloca.ll Fri Jun 24 14:01:25 2011
@@ -8,11 +8,9 @@
; CHECK: subu $[[T2:[0-9]+]], $sp, $[[SZ]]
; CHECK: addu $sp, $zero, $[[T2]]
; CHECK: addiu $[[T3:[0-9]+]], $sp, [[OFF]]
-; CHECK: lw $25, %call16(foo)($gp)
-; CHECK: addu $4, $zero, $[[T1]]
-; CHECK: jalr $25
-; CHECK: lw $25, %call16(foo)($gp)
-; CHECK: addu $4, $zero, $[[T3]]
+; CHECK: lw $[[T4:[0-9]+]], %call16(foo)($gp)
+; CHECK: addu $25, $zero, $[[T4]]
+; CHECK: addu $4, $zero, $[[T1]]
; CHECK: jalr $25
%tmp1 = alloca i8, i32 %size, align 4
%add.ptr = getelementptr inbounds i8* %tmp1, i32 5
Modified: llvm/trunk/test/CodeGen/Mips/i64arg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/i64arg.ll?rev=133811&r1=133810&r2=133811&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/i64arg.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/i64arg.ll Fri Jun 24 14:01:25 2011
@@ -10,8 +10,8 @@
; CHECK: jalr
tail call void @ff1(i32 %i, i64 1085102592623924856) nounwind
; CHECK: lw $25, %call16(ff2)
-; CHECK: lw $[[R2:[0-9]+]], 80($sp)
-; CHECK: lw $[[R3:[0-9]+]], 84($sp)
+; CHECK: lw $[[R2:[0-9]+]], 88($sp)
+; CHECK: lw $[[R3:[0-9]+]], 92($sp)
; CHECK: addu $4, $zero, $[[R2]]
; CHECK: addu $5, $zero, $[[R3]]
; CHECK: jalr $25
Modified: llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll?rev=133811&r1=133810&r2=133811&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll Fri Jun 24 14:01:25 2011
@@ -8,7 +8,7 @@
entry:
; CHECK: lui $at, 65534
; CHECK: addu $at, $sp, $at
-; CHECK: addiu $sp, $at, -16
+; CHECK: addiu $sp, $at, -24
; CHECK: .cprestore 65536
%agg.tmp = alloca %struct.S1, align 1
More information about the llvm-commits
mailing list