[llvm-commits] [llvm] r133331 - /llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td

[Jakob Stoklund Olesen]

Author: stoklund
Date: Fri Jun 17 21:30:02 2011
New Revision: 133331

URL: http://llvm.org/viewvc/llvm-project?rev=133331&view=rev
Log:
Delete unneeded allocation order override.

Modified:
    llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td

Modified: llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td?rev=133331&r1=133330&r2=133331&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td Fri Jun 17 21:30:02 2011
@@ -254,17 +254,7 @@
 let CopyCost = -1, Size = 8 in {
 def JustCC  : RegisterClass<"BF", [i32], 8, (add CC)>;
 def NotCC   : RegisterClass<"BF", [i32], 8, (add NCC)>;
-def AnyCC   : RegisterClass<"BF", [i32], 8, (add CC, NCC)> {
-  let MethodProtos = [{
-    iterator allocation_order_end(const MachineFunction &MF) const;
-  }];
-  let MethodBodies = [{
-    AnyCCClass::iterator
-    AnyCCClass::allocation_order_end(const MachineFunction &MF) const {
-      return allocation_order_begin(MF)+1;
-    }
-  }];
-}
+def AnyCC   : RegisterClass<"BF", [i32], 8, (add CC, NCC)>;
 def StatBit : RegisterClass<"BF", [i1], 8,
     (add AZ, AN, CC, AQ, AC0, AC1, AV0, AV0S, AV1, AV1S, V, VS)>;
 }