[llvm-commits] [llvm] r133216 - in /llvm/trunk: include/llvm/Target/TargetRegisterInfo.h lib/CodeGen/AllocationOrder.cpp lib/CodeGen/RegAllocLinearScan.cpp lib/Target/ARM/ARMBaseRegisterInfo.cpp lib/Target/ARM/ARMBaseRegisterInfo.h
Chad Rosier
mcrosier at apple.com
Thu Jun 16 17:14:38 PDT 2011
Jakob,
Can you please double check that this is building correctly.
See: http://smooshlab.apple.com:8013/builders/clang-x86_64-darwin10-gcc42-RA
Chad
On Jun 16, 2011, at 4:31 PM, Jakob Stoklund Olesen wrote:
> Author: stoklund
> Date: Thu Jun 16 18:31:16 2011
> New Revision: 133216
>
> URL: http://llvm.org/viewvc/llvm-project?rev=133216&view=rev
> Log:
> Rename TRI::getAllocationOrder() to getRawAllocationOrder().
>
> Also switch the return type to ArrayRef<unsigned> which works out nicely
> for ARM's implementation of this function because of the clever ArrayRef
> constructors.
>
> The name change indicates that the returned allocation order may contain
> reserved registers as has been the case for a while.
>
> Modified:
> llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
> llvm/trunk/lib/CodeGen/AllocationOrder.cpp
> llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
> llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
> llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h
>
> Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=133216&r1=133215&r2=133216&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Thu Jun 16 18:31:16 2011
> @@ -634,14 +634,17 @@
> return 0;
> }
>
> - /// getAllocationOrder - Returns the register allocation order for a specified
> - /// register class in the form of a pair of TargetRegisterClass iterators.
> - virtual std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
> - getAllocationOrder(const TargetRegisterClass *RC,
> - unsigned HintType, unsigned HintReg,
> - const MachineFunction &MF) const {
> - return std::make_pair(RC->allocation_order_begin(MF),
> - RC->allocation_order_end(MF));
> + /// getRawAllocationOrder - Returns the register allocation order for a
> + /// specified register class with a target-dependent hint. The returned list
> + /// may contain reserved registers that cannot be allocated.
> + ///
> + /// Register allocators need only call this function to resolve
> + /// target-dependent hints, but it should work without hinting as well.
> + virtual ArrayRef<unsigned>
> + getRawAllocationOrder(const TargetRegisterClass *RC,
> + unsigned HintType, unsigned HintReg,
> + const MachineFunction &MF) const {
> + return RC->getRawAllocationOrder(MF);
> }
>
> /// ResolveRegAllocHint - Resolves the specified register allocation hint
>
> Modified: llvm/trunk/lib/CodeGen/AllocationOrder.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AllocationOrder.cpp?rev=133216&r1=133215&r2=133216&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/AllocationOrder.cpp (original)
> +++ llvm/trunk/lib/CodeGen/AllocationOrder.cpp Thu Jun 16 18:31:16 2011
> @@ -41,21 +41,19 @@
> if (HintPair.first) {
> const TargetRegisterInfo &TRI = VRM.getTargetRegInfo();
> // The remaining allocation order may depend on the hint.
> - const unsigned *B, *E;
> - tie(B, E) = TRI.getAllocationOrder(RC, HintPair.first, Hint,
> - VRM.getMachineFunction());
> -
> - // Empty allocation order?
> - if (B == E)
> + ArrayRef<unsigned> Order =
> + TRI.getRawAllocationOrder(RC, HintPair.first, Hint,
> + VRM.getMachineFunction());
> + if (Order.empty())
> return;
>
> // Copy the allocation order with reserved registers removed.
> OwnedBegin = true;
> - unsigned *P = new unsigned[E - B];
> + unsigned *P = new unsigned[Order.size()];
> Begin = P;
> - for (; B != E; ++B)
> - if (!RCI.isReserved(*B))
> - *P++ = *B;
> + for (unsigned i = 0; i != Order.size(); ++i)
> + if (!RCI.isReserved(Order[i]))
> + *P++ = Order[i];
> End = P;
>
> // Target-dependent hints require resolution.
>
> Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=133216&r1=133215&r2=133216&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original)
> +++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Thu Jun 16 18:31:16 2011
> @@ -1440,13 +1440,13 @@
> if (TargetRegisterInfo::isVirtualRegister(physReg) && vrm_->hasPhys(physReg))
> physReg = vrm_->getPhys(physReg);
>
> - TargetRegisterClass::iterator I, E;
> - tie(I, E) = tri_->getAllocationOrder(RC, Hint.first, physReg, *mf_);
> - assert(I != E && "No allocatable register in this register class!");
> + ArrayRef<unsigned> Order = tri_->getRawAllocationOrder(RC, Hint.first,
> + physReg, *mf_);
> + assert(!Order.empty() && "No allocatable register in this register class!");
>
> // Scan for the first available register.
> - for (; I != E; ++I) {
> - unsigned Reg = *I;
> + for (unsigned i = 0; i != Order.size(); ++i) {
> + unsigned Reg = Order[i];
> // Ignore "downgraded" registers.
> if (SkipDGRegs && DowngradedRegs.count(Reg))
> continue;
> @@ -1476,8 +1476,8 @@
> // inactive count. Alkis found that this reduced register pressure very
> // slightly on X86 (in rev 1.94 of this file), though this should probably be
> // reevaluated now.
> - for (; I != E; ++I) {
> - unsigned Reg = *I;
> + for (unsigned i = 0; i != Order.size(); ++i) {
> + unsigned Reg = Order[i];
> // Ignore "downgraded" registers.
> if (SkipDGRegs && DowngradedRegs.count(Reg))
> continue;
>
> Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=133216&r1=133215&r2=133216&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Thu Jun 16 18:31:16 2011
> @@ -387,12 +387,12 @@
> }
> }
>
> -/// getAllocationOrder - Returns the register allocation order for a specified
> -/// register class in the form of a pair of TargetRegisterClass iterators.
> -std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
> -ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
> - unsigned HintType, unsigned HintReg,
> - const MachineFunction &MF) const {
> +/// getRawAllocationOrder - Returns the register allocation order for a
> +/// specified register class with a target-dependent hint.
> +ArrayRef<unsigned>
> +ARMBaseRegisterInfo::getRawAllocationOrder(const TargetRegisterClass *RC,
> + unsigned HintType, unsigned HintReg,
> + const MachineFunction &MF) const {
> const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
> // Alternative register allocation orders when favoring even / odd registers
> // of register pairs.
> @@ -469,70 +469,54 @@
>
> // We only support even/odd hints for GPR and rGPR.
> if (RC != ARM::GPRRegisterClass && RC != ARM::rGPRRegisterClass)
> - return std::make_pair(RC->allocation_order_begin(MF),
> - RC->allocation_order_end(MF));
> + return RC->getRawAllocationOrder(MF);
>
> if (HintType == ARMRI::RegPairEven) {
> if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
> // It's no longer possible to fulfill this hint. Return the default
> // allocation order.
> - return std::make_pair(RC->allocation_order_begin(MF),
> - RC->allocation_order_end(MF));
> + return RC->getRawAllocationOrder(MF);
>
> if (!TFI->hasFP(MF)) {
> if (!STI.isR9Reserved())
> - return std::make_pair(GPREven1,
> - GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
> + return GPREven1;
> else
> - return std::make_pair(GPREven4,
> - GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
> + return GPREven4;
> } else if (FramePtr == ARM::R7) {
> if (!STI.isR9Reserved())
> - return std::make_pair(GPREven2,
> - GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
> + return GPREven2;
> else
> - return std::make_pair(GPREven5,
> - GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
> + return GPREven5;
> } else { // FramePtr == ARM::R11
> if (!STI.isR9Reserved())
> - return std::make_pair(GPREven3,
> - GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
> + return GPREven3;
> else
> - return std::make_pair(GPREven6,
> - GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
> + return GPREven6;
> }
> } else if (HintType == ARMRI::RegPairOdd) {
> if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
> // It's no longer possible to fulfill this hint. Return the default
> // allocation order.
> - return std::make_pair(RC->allocation_order_begin(MF),
> - RC->allocation_order_end(MF));
> + return RC->getRawAllocationOrder(MF);
>
> if (!TFI->hasFP(MF)) {
> if (!STI.isR9Reserved())
> - return std::make_pair(GPROdd1,
> - GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
> + return GPROdd1;
> else
> - return std::make_pair(GPROdd4,
> - GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
> + return GPROdd4;
> } else if (FramePtr == ARM::R7) {
> if (!STI.isR9Reserved())
> - return std::make_pair(GPROdd2,
> - GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
> + return GPROdd2;
> else
> - return std::make_pair(GPROdd5,
> - GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
> + return GPROdd5;
> } else { // FramePtr == ARM::R11
> if (!STI.isR9Reserved())
> - return std::make_pair(GPROdd3,
> - GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
> + return GPROdd3;
> else
> - return std::make_pair(GPROdd6,
> - GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
> + return GPROdd6;
> }
> }
> - return std::make_pair(RC->allocation_order_begin(MF),
> - RC->allocation_order_end(MF));
> + return RC->getRawAllocationOrder(MF);
> }
>
> /// ResolveRegAllocHint - Resolves the specified register allocation hint
>
> Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=133216&r1=133215&r2=133216&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Thu Jun 16 18:31:16 2011
> @@ -134,10 +134,9 @@
> unsigned getRegPressureLimit(const TargetRegisterClass *RC,
> MachineFunction &MF) const;
>
> - std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
> - getAllocationOrder(const TargetRegisterClass *RC,
> - unsigned HintType, unsigned HintReg,
> - const MachineFunction &MF) const;
> + ArrayRef<unsigned> getRawAllocationOrder(const TargetRegisterClass *RC,
> + unsigned HintType, unsigned HintReg,
> + const MachineFunction &MF) const;
>
> unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
> const MachineFunction &MF) const;
>
>
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