[llvm-commits] [llvm] r133171 - in /llvm/trunk/lib/Target/PTX: PTXAsmPrinter.cpp PTXISelLowering.cpp PTXInstrFormats.td PTXInstrInfo.cpp PTXInstrInfo.td PTXIntrinsicInstrInfo.td PTXRegisterInfo.td

[Justin Holewinski]

On Jun 16, 2011, at 2:27 PM, Jakob Stoklund Olesen wrote:

> 
> On Jun 16, 2011, at 10:49 AM, Justin Holewinski wrote:
> 
>> -def Preds : RegisterClass<"PTX", [i1], 8, (sequence "P%u", 0, 63)>;
>> -def RRegu16 : RegisterClass<"PTX", [i16], 16, (sequence "RH%u", 0, 63)>;
>> -def RRegu32 : RegisterClass<"PTX", [i32], 32, (sequence "R%u",  0, 63)>;
>> -def RRegu64 : RegisterClass<"PTX", [i64], 64, (sequence "RD%u", 0, 63)>;
>> -def RRegf32 : RegisterClass<"PTX", [f32], 32, (sequence "F%u",  0, 63)>;
>> -def RRegf64 : RegisterClass<"PTX", [f64], 64, (sequence "FD%u", 0, 63)>;
>> +def RegPred : RegisterClass<"PTX", [i1], 8, (sequence "P%u", 0, 7)>;
>> +def RegI16  : RegisterClass<"PTX", [i16], 16, (sequence "RH%u", 0, 7)>;
>> +def RegI32  : RegisterClass<"PTX", [i32], 32, (sequence "R%u",  0, 7)>;
>> +def RegI64  : RegisterClass<"PTX", [i64], 64, (sequence "RD%u", 0, 7)>;
>> +def RegF32  : RegisterClass<"PTX", [f32], 32, (sequence "R%u",  0, 7)>;
>> +def RegF64  : RegisterClass<"PTX", [f64], 64, (sequence "RD%u", 0, 7)>;
> 
> Did you mean to reduce the number of registers by 8x?

Yes, reducing the number of registers makes it a bit easier to test the spill code I'm writing for the next set of patches.  For PTX, it's arbitrary anyway.

> 
> /jakob
> 

Thanks,

Justin Holewinski

-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20110616/03aeb6bc/attachment.html>