[llvm-commits] [llvm] r133022 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/X86/shl_undef.ll

[Jay Foad]

> When pattern matching during instruction selection make sure shl x,1 is not
> converted to add x,x if x is a undef.  add undef, undef does not guarantee
> that the resulting low order bit is zero.

So according to the LLVM Language Reference Manual, "shl x, 1" and
"mul x, 2" are both guaranteed to have the bottom bit zero. This seems
like a horrible burden on the optimizers, if they are not allowed to
freely convert between "add x, x" and "mul x, 2".

IMO it would be better to change the Lang Ref so that the result of
"shl undef, 1" is undef.

Jay.