[llvm-commits] [llvm] r133029 - in /llvm/trunk/utils/TableGen: CodeGenRegisters.cpp CodeGenRegisters.h CodeGenTarget.cpp CodeGenTarget.h FastISelEmitter.cpp
Jakob Stoklund Olesen
stoklund at 2pi.dk
Tue Jun 14 17:20:40 PDT 2011
Author: stoklund
Date: Tue Jun 14 19:20:40 2011
New Revision: 133029
URL: http://llvm.org/viewvc/llvm-project?rev=133029&view=rev
Log:
Move the list of register classes into CodeGenRegBank as well.
No functional change intended.
Modified:
llvm/trunk/utils/TableGen/CodeGenRegisters.cpp
llvm/trunk/utils/TableGen/CodeGenRegisters.h
llvm/trunk/utils/TableGen/CodeGenTarget.cpp
llvm/trunk/utils/TableGen/CodeGenTarget.h
llvm/trunk/utils/TableGen/FastISelEmitter.cpp
Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.cpp?rev=133029&r1=133028&r2=133029&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenRegisters.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenRegisters.cpp Tue Jun 14 19:20:40 2011
@@ -237,6 +237,14 @@
// Assign the enumeration values.
for (unsigned i = 0, e = Regs.size(); i != e; ++i)
Registers.push_back(CodeGenRegister(Regs[i], i + 1));
+
+ // Read in register class definitions.
+ std::vector<Record*> RCs = Records.getAllDerivedDefinitions("RegisterClass");
+ if (RCs.empty())
+ throw std::string("No 'RegisterClass' subclasses defined!");
+
+ RegClasses.reserve(RCs.size());
+ RegClasses.assign(RCs.begin(), RCs.end());
}
CodeGenRegister *CodeGenRegBank::getReg(Record *Def) {
@@ -250,6 +258,17 @@
throw TGError(Def->getLoc(), "Not a known Register!");
}
+CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) {
+ if (Def2RC.empty())
+ for (unsigned i = 0, e = RegClasses.size(); i != e; ++i)
+ Def2RC[RegClasses[i].TheDef] = &RegClasses[i];
+
+ if (CodeGenRegisterClass *RC = Def2RC[Def])
+ return RC;
+
+ throw TGError(Def->getLoc(), "Not a known RegisterClass!");
+}
+
Record *CodeGenRegBank::getCompositeSubRegIndex(Record *A, Record *B,
bool create) {
// Look for an existing entry.
@@ -406,3 +425,55 @@
computeComposites();
}
+/// getRegisterClassForRegister - Find the register class that contains the
+/// specified physical register. If the register is not in a register class,
+/// return null. If the register is in multiple classes, and the classes have a
+/// superset-subset relationship and the same set of types, return the
+/// superclass. Otherwise return null.
+const CodeGenRegisterClass*
+CodeGenRegBank::getRegClassForRegister(Record *R) {
+ const std::vector<CodeGenRegisterClass> &RCs = getRegClasses();
+ const CodeGenRegisterClass *FoundRC = 0;
+ for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
+ const CodeGenRegisterClass &RC = RCs[i];
+ if (!RC.containsRegister(R))
+ continue;
+
+ // If this is the first class that contains the register,
+ // make a note of it and go on to the next class.
+ if (!FoundRC) {
+ FoundRC = &RC;
+ continue;
+ }
+
+ // If a register's classes have different types, return null.
+ if (RC.getValueTypes() != FoundRC->getValueTypes())
+ return 0;
+
+ std::vector<Record *> Elements(RC.Elements);
+ std::vector<Record *> FoundElements(FoundRC->Elements);
+ std::sort(Elements.begin(), Elements.end());
+ std::sort(FoundElements.begin(), FoundElements.end());
+
+ // Check to see if the previously found class that contains
+ // the register is a subclass of the current class. If so,
+ // prefer the superclass.
+ if (std::includes(Elements.begin(), Elements.end(),
+ FoundElements.begin(), FoundElements.end())) {
+ FoundRC = &RC;
+ continue;
+ }
+
+ // Check to see if the previously found class that contains
+ // the register is a superclass of the current class. If so,
+ // prefer the superclass.
+ if (std::includes(FoundElements.begin(), FoundElements.end(),
+ Elements.begin(), Elements.end()))
+ continue;
+
+ // Multiple classes, and neither is a superclass of the other.
+ // Return null.
+ return 0;
+ }
+ return FoundRC;
+}
Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.h?rev=133029&r1=133028&r2=133029&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenRegisters.h (original)
+++ llvm/trunk/utils/TableGen/CodeGenRegisters.h Tue Jun 14 19:20:40 2011
@@ -153,6 +153,9 @@
std::vector<CodeGenRegister> Registers;
DenseMap<Record*, CodeGenRegister*> Def2Reg;
+ std::vector<CodeGenRegisterClass> RegClasses;
+ DenseMap<Record*, CodeGenRegisterClass*> Def2RC;
+
// Composite SubRegIndex instances.
// Map (SubRegIndex, SubRegIndex) -> SubRegIndex.
typedef DenseMap<std::pair<Record*, Record*>, Record*> CompositeMap;
@@ -181,6 +184,20 @@
// Find a register from its Record def.
CodeGenRegister *getReg(Record*);
+ const std::vector<CodeGenRegisterClass> &getRegClasses() {
+ return RegClasses;
+ }
+
+ // Find a register class from its def.
+ CodeGenRegisterClass *getRegClass(Record*);
+
+ /// getRegisterClassForRegister - Find the register class that contains the
+ /// specified physical register. If the register is not in a register
+ /// class, return null. If the register is in multiple classes, and the
+ /// classes have a superset-subset relationship and the same set of types,
+ /// return the superclass. Otherwise return null.
+ const CodeGenRegisterClass* getRegClassForRegister(Record *R);
+
// Computed derived records such as missing sub-register indices.
void computeDerivedInfo();
Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=133029&r1=133028&r2=133029&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Tue Jun 14 19:20:40 2011
@@ -163,16 +163,6 @@
return *RegBank;
}
-void CodeGenTarget::ReadRegisterClasses() const {
- std::vector<Record*> RegClasses =
- Records.getAllDerivedDefinitions("RegisterClass");
- if (RegClasses.empty())
- throw std::string("No 'RegisterClass' subclasses defined!");
-
- RegisterClasses.reserve(RegClasses.size());
- RegisterClasses.assign(RegClasses.begin(), RegClasses.end());
-}
-
/// getRegisterByName - If there is a register with the specific AsmName,
/// return it.
const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const {
@@ -191,7 +181,7 @@
std::vector<MVT::SimpleValueType> Result;
const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
- const CodeGenRegisterClass &RC = RegisterClasses[i];
+ const CodeGenRegisterClass &RC = RCs[i];
for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) {
if (R == RC.Elements[ei]) {
const std::vector<MVT::SimpleValueType> &InVTs = RC.getValueTypes();
Modified: llvm/trunk/utils/TableGen/CodeGenTarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.h?rev=133029&r1=133028&r2=133029&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenTarget.h (original)
+++ llvm/trunk/utils/TableGen/CodeGenTarget.h Tue Jun 14 19:20:40 2011
@@ -66,9 +66,7 @@
mutable DenseMap<const Record*, CodeGenInstruction*> Instructions;
mutable CodeGenRegBank *RegBank;
- mutable std::vector<CodeGenRegisterClass> RegisterClasses;
mutable std::vector<MVT::SimpleValueType> LegalValueTypes;
- void ReadRegisterClasses() const;
void ReadInstructions() const;
void ReadLegalValueTypes() const;
@@ -107,71 +105,11 @@
const CodeGenRegister *getRegisterByName(StringRef Name) const;
const std::vector<CodeGenRegisterClass> &getRegisterClasses() const {
- if (RegisterClasses.empty()) ReadRegisterClasses();
- return RegisterClasses;
+ return getRegBank().getRegClasses();
}
const CodeGenRegisterClass &getRegisterClass(Record *R) const {
- const std::vector<CodeGenRegisterClass> &RC = getRegisterClasses();
- for (unsigned i = 0, e = RC.size(); i != e; ++i)
- if (RC[i].TheDef == R)
- return RC[i];
- assert(0 && "Didn't find the register class");
- abort();
- }
-
- /// getRegisterClassForRegister - Find the register class that contains the
- /// specified physical register. If the register is not in a register
- /// class, return null. If the register is in multiple classes, and the
- /// classes have a superset-subset relationship and the same set of
- /// types, return the superclass. Otherwise return null.
- const CodeGenRegisterClass *getRegisterClassForRegister(Record *R) const {
- const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
- const CodeGenRegisterClass *FoundRC = 0;
- for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
- const CodeGenRegisterClass &RC = RegisterClasses[i];
- for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) {
- if (R != RC.Elements[ei])
- continue;
-
- // If a register's classes have different types, return null.
- if (FoundRC && RC.getValueTypes() != FoundRC->getValueTypes())
- return 0;
-
- // If this is the first class that contains the register,
- // make a note of it and go on to the next class.
- if (!FoundRC) {
- FoundRC = &RC;
- break;
- }
-
- std::vector<Record *> Elements(RC.Elements);
- std::vector<Record *> FoundElements(FoundRC->Elements);
- std::sort(Elements.begin(), Elements.end());
- std::sort(FoundElements.begin(), FoundElements.end());
-
- // Check to see if the previously found class that contains
- // the register is a subclass of the current class. If so,
- // prefer the superclass.
- if (std::includes(Elements.begin(), Elements.end(),
- FoundElements.begin(), FoundElements.end())) {
- FoundRC = &RC;
- break;
- }
-
- // Check to see if the previously found class that contains
- // the register is a superclass of the current class. If so,
- // prefer the superclass.
- if (std::includes(FoundElements.begin(), FoundElements.end(),
- Elements.begin(), Elements.end()))
- break;
-
- // Multiple classes, and neither is a superclass of the other.
- // Return null.
- return 0;
- }
- }
- return FoundRC;
+ return *getRegBank().getRegClass(R);
}
/// getRegisterVTs - Find the union of all possible SimpleValueTypes for the
Modified: llvm/trunk/utils/TableGen/FastISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FastISelEmitter.cpp?rev=133029&r1=133028&r2=133029&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/FastISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/FastISelEmitter.cpp Tue Jun 14 19:20:40 2011
@@ -250,7 +250,7 @@
if (OpLeafRec->isSubClassOf("RegisterClass"))
RC = &Target.getRegisterClass(OpLeafRec);
else if (OpLeafRec->isSubClassOf("Register"))
- RC = Target.getRegisterClassForRegister(OpLeafRec);
+ RC = Target.getRegBank().getRegClassForRegister(OpLeafRec);
else
return false;
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