[llvm-commits] [dragonegg] r132742 - in /dragonegg/trunk: include/dragonegg/Internals.h src/Convert.cpp

[Duncan Sands]

Author: baldrick
Date: Wed Jun  8 03:06:59 2011
New Revision: 132742

URL: http://llvm.org/viewvc/llvm-project?rev=132742&view=rev
Log:
Add support for VEC_UNPACK_FLOAT_HI_EXPR/VEC_UNPACK_FLOAT_LO_EXPR.  It
turns out that the existing code for VEC_UNPACK_HI/LO_EXPR works fine
for this, so just reuse it.  This fixes PR10014.

Modified:
    dragonegg/trunk/include/dragonegg/Internals.h
    dragonegg/trunk/src/Convert.cpp

Modified: dragonegg/trunk/include/dragonegg/Internals.h
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/include/dragonegg/Internals.h?rev=132742&r1=132741&r2=132742&view=diff
==============================================================================
--- dragonegg/trunk/include/dragonegg/Internals.h (original)
+++ dragonegg/trunk/include/dragonegg/Internals.h Wed Jun  8 03:06:59 2011
@@ -701,6 +701,8 @@
   Value *EmitReg_VecShiftOp(tree_node *op0, tree_node *op1, bool isLeftShift);
   Value *EmitReg_TruthOp(tree_node *type, tree_node *op0, tree_node *op1,
                          unsigned Opc);
+  Value *EmitReg_VecUnpackHiExpr(tree_node *type, tree_node *op0);
+  Value *EmitReg_VecUnpackLoExpr(tree_node *type, tree_node *op0);
   Value *EmitReg_BIT_AND_EXPR(tree_node *op0, tree_node *op1);
   Value *EmitReg_BIT_IOR_EXPR(tree_node *op0, tree_node *op1);
   Value *EmitReg_BIT_XOR_EXPR(tree_node *op0, tree_node *op1);
@@ -723,8 +725,6 @@
   Value *EmitReg_VEC_INTERLEAVE_LOW_EXPR(tree_node *op0, tree_node *op1);
   Value *EmitReg_VEC_PACK_TRUNC_EXPR(tree_node *type, tree_node *op0,
                                      tree_node *op1);
-  Value *EmitReg_VEC_UNPACK_HI_EXPR(tree_node *type, tree_node *op0);
-  Value *EmitReg_VEC_UNPACK_LO_EXPR(tree_node *type, tree_node *op0);
 
   Value *EmitLoadOfLValue(tree_node *exp);
   Value *EmitOBJ_TYPE_REF(tree_node *exp);

Modified: dragonegg/trunk/src/Convert.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=132742&r1=132741&r2=132742&view=diff
==============================================================================
--- dragonegg/trunk/src/Convert.cpp (original)
+++ dragonegg/trunk/src/Convert.cpp Wed Jun  8 03:06:59 2011
@@ -7375,7 +7375,7 @@
   return Builder.CreateShuffleVector(LHS, RHS, ConstantVector::get(Mask));
 }
 
-Value *TreeToLLVM::EmitReg_VEC_UNPACK_HI_EXPR(tree type, tree op0) {
+Value *TreeToLLVM::EmitReg_VecUnpackHiExpr(tree type, tree op0) {
   // Eg: <2 x double> = VEC_UNPACK_HI_EXPR(<4 x float>)
   Value *Op = EmitRegister(op0);
 
@@ -7389,7 +7389,7 @@
                        !TYPE_UNSIGNED(TREE_TYPE(type)));
 }
 
-Value *TreeToLLVM::EmitReg_VEC_UNPACK_LO_EXPR(tree type, tree op0) {
+Value *TreeToLLVM::EmitReg_VecUnpackLoExpr(tree type, tree op0) {
   // Eg: <2 x double> = VEC_UNPACK_LO_EXPR(<4 x float>)
   Value *Op = EmitRegister(op0);
 
@@ -8390,10 +8390,12 @@
     RHS = EmitReg_VEC_PACK_TRUNC_EXPR(type, rhs1, rhs2); break;
   case VEC_RSHIFT_EXPR:
     RHS = EmitReg_VecShiftOp(rhs1, rhs2, /*isLeftShift*/false); break;
+  case VEC_UNPACK_FLOAT_HI_EXPR:
   case VEC_UNPACK_HI_EXPR:
-    RHS = EmitReg_VEC_UNPACK_HI_EXPR(type, rhs1); break;
+    RHS = EmitReg_VecUnpackHiExpr(type, rhs1); break;
+  case VEC_UNPACK_FLOAT_LO_EXPR:
   case VEC_UNPACK_LO_EXPR:
-    RHS = EmitReg_VEC_UNPACK_LO_EXPR(type, rhs1); break;
+    RHS = EmitReg_VecUnpackLoExpr(type, rhs1); break;
   }
 
   return TriviallyTypeConvert(RHS, getRegType(type));