From vanboxem.ruben at gmail.com Mon Jun 6 05:16:42 2011 From: vanboxem.ruben at gmail.com (Ruben Van Boxem) Date: Mon, 6 Jun 2011 14:16:42 +0200 Subject: [llvm-commits] [Patch] Trivial fix for build failure on MinGW Message-ID: Attached patch changes _MSC_VER to _WIN32 so that the correct version of the mkdir function is called with all Win32 platforms. -------------- next part -------------- A non-text attachment was scrubbed... Name: win32mingw.patch Type: application/octet-stream Size: 478 bytes Desc: not available URL: From rdivacky at freebsd.org Mon Jun 6 08:38:22 2011 From: rdivacky at freebsd.org (Roman Divacky) Date: Mon, 6 Jun 2011 17:38:22 +0200 Subject: [llvm-commits] [llvm] r132676 - in /llvm/trunk: lib/CodeGen/SelectionDAG/FastISel.cpp test/CodeGen/X86/fast-isel-agg-constant.ll Message-ID: <20110606153822.GA6591@freebsd.org> Hi there, MC currently hardcodes the raw text emission of VK_PPC_HA16/VK_PPC_LO16 symbols to the darwin format, ie: ha16(symbol) and lo16(symbol) Gnu as accepts this format: symbol at ha and symbol at l The attached patch splits VK_PPC_HA16/VK_PPC_LO16 into VK_PPC_DARWIN_HA16, VK_PPC_DARWIN_LO16, VK_PPC_GAS_HA16, VK_PPC_GAS_LO16 using each variant based on whether the target is darwin. This enables LLVM to be used on PowerPC64 on non-darwin platforms (tested on FreeBSD). OK to commit? Or is there a better way to distinguish those two asm dialects? roman -------------- next part -------------- A non-text attachment was scrubbed... Name: powerpc64.patch Type: text/x-diff Size: 5787 bytes Desc: not available URL: From rdivacky at freebsd.org Mon Jun 6 08:41:33 2011 From: rdivacky at freebsd.org (Roman Divacky) Date: Mon, 6 Jun 2011 17:41:33 +0200 Subject: [llvm-commits] [PATCH]: PPC64 emission of gnu as dialect asm fix In-Reply-To: <20110606153822.GA6591@freebsd.org> References: <20110606153822.GA6591@freebsd.org> Message-ID: <20110606154133.GA6958@freebsd.org> I forgot to reset the Subject, sorry On Mon, Jun 06, 2011 at 05:38:22PM +0200, Roman Divacky wrote: > Hi there, > > MC currently hardcodes the raw text emission of VK_PPC_HA16/VK_PPC_LO16 > symbols to the darwin format, ie: > > ha16(symbol) and lo16(symbol) > > Gnu as accepts this format: > > symbol at ha and symbol at l > > The attached patch splits VK_PPC_HA16/VK_PPC_LO16 into > > VK_PPC_DARWIN_HA16, > VK_PPC_DARWIN_LO16, > VK_PPC_GAS_HA16, > VK_PPC_GAS_LO16 > > using each variant based on whether the target is darwin. > > > This enables LLVM to be used on PowerPC64 on non-darwin platforms > (tested on FreeBSD). > > OK to commit? Or is there a better way to distinguish those two > asm dialects? > > roman > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From grosser at fim.uni-passau.de Mon Jun 6 08:50:09 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Mon, 06 Jun 2011 15:50:09 -0000 Subject: [llvm-commits] [polly] r132678 - in /polly/trunk/www: bugs.html menu.html.incl Message-ID: <20110606155010.053CF2A6C12C@llvm.org> Author: grosser Date: Mon Jun 6 10:50:09 2011 New Revision: 132678 URL: http://llvm.org/viewvc/llvm-project?rev=132678&view=rev Log: www: Add website for the LLVM bugtracker use Added: polly/trunk/www/bugs.html Modified: polly/trunk/www/menu.html.incl Added: polly/trunk/www/bugs.html URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/bugs.html?rev=132678&view=auto ============================================================================== --- polly/trunk/www/bugs.html (added) +++ polly/trunk/www/bugs.html Mon Jun 6 10:50:09 2011 @@ -0,0 +1,38 @@ + + + + + Polly - Bugs + + + + + + + +
+ +

Bugs in Polly

+ +Polly uses the LLVM bug tracking system. + +

File a Bug

+ +To report a bug go to the LLVM Bugzilla website +select "File a Bug", chose "Projects" and select the component "Polly". To go +directly to the corresponding page +follow this link. +New bug reports will automatically be sent to the Polly development mailing list. + + +

Open Bugs

+A list of the open +bugs in Polly is also available. + +
+ + Modified: polly/trunk/www/menu.html.incl URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/menu.html.incl?rev=132678&r1=132677&r2=132678&view=diff ============================================================================== --- polly/trunk/www/menu.html.incl (original) +++ polly/trunk/www/menu.html.incl Mon Jun 6 10:50:09 2011 @@ -20,7 +20,7 @@ llvm-commits List polly-dev List - Bug Reports + Bug Reports
From rdivacky at freebsd.org Mon Jun 6 09:04:24 2011 From: rdivacky at freebsd.org (Roman Divacky) Date: Mon, 6 Jun 2011 18:04:24 +0200 Subject: [llvm-commits] [PATCH]: make LLVM compilable on PPC64/non-darwin Message-ID: <20110606160424.GA9190@freebsd.org> Hi there, PPC64CompilationCallback in PPCJITInfo.cpp is written in darwin asm dialect. The attached patch makes it compilable with gnu as too. JIT does not work on PPC64/non-darwin.I think the problem is not related to this patch though. This patch at least enables us to compile LLVM on non-darwin PowerPC64. The patch was contributed by Nathan Whiterhorn. OK to commit? roman -------------- next part -------------- A non-text attachment was scrubbed... Name: PPCJITInfo.cpp.diff Type: text/x-diff Size: 4752 bytes Desc: not available URL: From stoklund at 2pi.dk Mon Jun 6 09:36:30 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 06 Jun 2011 16:36:30 -0000 Subject: [llvm-commits] [llvm] r132680 - /llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp Message-ID: <20110606163630.62B362A6C12C@llvm.org> Author: stoklund Date: Mon Jun 6 11:36:30 2011 New Revision: 132680 URL: http://llvm.org/viewvc/llvm-project?rev=132680&view=rev Log: Don't try to be clever, just preserve the target's allocation order. The order of registers returned by getCalleeSavedRegs is used to lay out the fixed stack slots for CSRs. Some targets like their CSRs used from one end, and some targets want them used from the other end. When computing an allocation order, simply preserve the relative ordering of CSRs that the target specifies in its allocation order. Reordering CSRs would break some targets, ARM in particular. We still place volatiles before the CSRs, providing slightly better results with different calling conventions. Modified: llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp Modified: llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp?rev=132680&r1=132679&r2=132680&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp Mon Jun 6 11:36:30 2011 @@ -77,7 +77,7 @@ RCI.Order.reset(new unsigned[NumRegs]); unsigned N = 0; - SmallVector, 8> CSRAlias; + SmallVector CSRAlias; // FIXME: Once targets reserve registers instead of removing them from the // allocation order, we can simply use begin/end here. @@ -89,22 +89,17 @@ // Remove reserved registers from the allocation order. if (Reserved.test(PhysReg)) continue; - if (unsigned CSR = CSRNum[PhysReg]) - // PhysReg aliases a CSR, save it for later. Provide a (CSR, N) sort key - // to preserve the original ordering of multiple aliases of the same CSR. - CSRAlias.push_back(std::make_pair((CSR << 16) + (I - AOB), PhysReg)); + if (CSRNum[PhysReg]) + // PhysReg aliases a CSR, save it for later. + CSRAlias.push_back(PhysReg); else RCI.Order[N++] = PhysReg; } RCI.NumRegs = N + CSRAlias.size(); assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); - // Sort CSR aliases acording to the CSR ordering. - if (CSRAlias.size() >= 2) - array_pod_sort(CSRAlias.begin(), CSRAlias.end()); - - for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i) - RCI.Order[N++] = CSRAlias[i].second; + // CSR aliases go after the volatile registers, preserve the target's order. + std::copy(CSRAlias.begin(), CSRAlias.end(), &RCI.Order[N]); DEBUG({ dbgs() << "AllocationOrder(" << RC->getName() << ") = ["; From stuart at apple.com Mon Jun 6 09:44:31 2011 From: stuart at apple.com (Stuart Hastings) Date: Mon, 06 Jun 2011 16:44:31 -0000 Subject: [llvm-commits] [llvm] r132681 - /llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Message-ID: <20110606164431.B28DD2A6C12C@llvm.org> Author: stuart Date: Mon Jun 6 11:44:31 2011 New Revision: 132681 URL: http://llvm.org/viewvc/llvm-project?rev=132681&view=rev Log: Avoid FGETSIGN of 80-bit types. Fixes PR10085. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=132681&r1=132680&r2=132681&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Mon Jun 6 11:44:31 2011 @@ -1760,18 +1760,20 @@ break; } case ISD::BITCAST: - // If this is an FP->Int bitcast and if the sign bit is the only thing that - // is demanded, turn this into a FGETSIGN. + // If this is an FP->Int bitcast and if the sign bit is the only + // thing demanded, turn this into a FGETSIGN. if (NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) && Op.getOperand(0).getValueType().isFloatingPoint() && !Op.getOperand(0).getValueType().isVector()) { - if (isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32)) { - EVT Ty = (isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType())) ? - Op.getValueType() : MVT::i32; + bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType()); + bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); + if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) { + EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32; // Make a FGETSIGN + SHL to move the sign bit into the appropriate // place. We expect the SHL to be eliminated by other optimizations. SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0)); - if (Ty != Op.getValueType()) + unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits(); + if (!OpVTLegal && OpVTSizeInBits > 32) Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign); unsigned ShVal = Op.getValueType().getSizeInBits()-1; SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType()); From respindola at mozilla.com Mon Jun 6 10:57:40 2011 From: respindola at mozilla.com (Rafael Avila de Espindola) Date: Mon, 06 Jun 2011 13:57:40 -0400 Subject: [llvm-commits] [patch] Change how clang produces computed gotos Message-ID: <4DED1514.3010000@mozilla.com> I tried compiling firefox with both clang and Apple's gcc. The performance was close. Running it on shark showed that the difference was that the clang compiled one was using 2x as much time in the js interpreter. There seems to be a register allocator problem that I hope to report shortly, but another problem is the way the computed gotos are produced. Currently clang produces a branch to a common bb that has the only inderctbr in the function. This is normally optimized away, but the optimizers are not kicking in jsinterp.o and it has a single 'jmp *%rax' in the generated binary. The main reason for the status quo I think is a gradual evolution from the days there was no indirectbr in llvm. Producing n indirectbr instructions does increase the size of the cfg, but I think the results are worth it: jsinterp.o goes from 1876288 to 1684448 bytes. The dromaeo score of firefox goes from 1628.59runs/s to 1674.68runs/s. For comparison, gcc is 1667.49runs/s. It is the first time I get firefox to go faster when compiled with clang :-) Build time on files that use computed goto does suffer. jsinterp.o with -O3 -g goes from 63s to 140s. Gives that this is one of the two files in all of mozilla that use it, and that it is really performance critical, I think it is worth it. A question about indirectbr: I has a list of every label it could branch to. It doesn't look like we optimize it and that we avoid inlining functions that use computed goto. Wouldn't it be better to make the list implicit: every label in this function that has its address taken? Cheers, Rafael -------------- next part -------------- A non-text attachment was scrubbed... Name: indirect.patch Type: text/x-patch Size: 6342 bytes Desc: not available URL: From baldrick at free.fr Mon Jun 6 12:11:16 2011 From: baldrick at free.fr (Duncan Sands) Date: Mon, 06 Jun 2011 21:11:16 +0200 Subject: [llvm-commits] [patch] Change how clang produces computed gotos In-Reply-To: <4DED1514.3010000@mozilla.com> References: <4DED1514.3010000@mozilla.com> Message-ID: <4DED2654.3040801@free.fr> Hi Rafael, ... > Currently clang produces a branch to a common bb that has the only inderctbr in > the function. This is normally optimized away, but the optimizers are not > kicking in jsinterp.o and it has a single 'jmp *%rax' in the generated binary. > > The main reason for the status quo I think is a gradual evolution from the days > there was no indirectbr in llvm. for what it's worth, GCC does this too (i.e. refactors all indirect branches to just one), so I don't think it is due to LLVM evolution. Ciao, Duncan. From stoklund at 2pi.dk Mon Jun 6 12:26:06 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 06 Jun 2011 12:26:06 -0700 Subject: [llvm-commits] [patch] Change how clang produces computed gotos In-Reply-To: <4DED1514.3010000@mozilla.com> References: <4DED1514.3010000@mozilla.com> Message-ID: <1BC4745F-C8F7-4CB7-A8A0-584132FA2786@2pi.dk> On Jun 6, 2011, at 10:57 AM, Rafael Avila de Espindola wrote: > I tried compiling firefox with both clang and Apple's gcc. The performance was close. Running it on shark showed that the difference was that the clang compiled one was using 2x as much time in the js interpreter. > > There seems to be a register allocator problem that I hope to report shortly, but another problem is the way the computed gotos are produced. > > Currently clang produces a branch to a common bb that has the only inderctbr in the function. This is normally optimized away, but the optimizers are not kicking in jsinterp.o and it has a single 'jmp *%rax' in the generated binary. > > The main reason for the status quo I think is a gradual evolution from the days there was no indirectbr in llvm. Producing n indirectbr instructions does increase the size of the cfg, but I think the results are worth it: It was designed this way to keep the mid-level optimizers relatively performant. Duplicating the indirectbr block creates a quadratic number of CFG edges, all critical. There is not much the optimizers can do with such a CFG anyway, other than being really slow. The backend will duplicate the indirectbr block in its early taildup pass to get the benefits of Markov chain branch prediction. I am not sure why it fails in this case. > jsinterp.o goes from 1876288 to 1684448 bytes. The dromaeo score of firefox goes from 1628.59runs/s to 1674.68runs/s. For comparison, gcc is 1667.49runs/s. It is the first time I get firefox to go faster when compiled with clang :-) > > Build time on files that use computed goto does suffer. jsinterp.o with -O3 -g goes from 63s to 140s. Gives that this is one of the two files in all of mozilla that use it, and that it is really performance critical, I think it is worth it. > > A question about indirectbr: I has a list of every label it could branch to. It doesn't look like we optimize it and that we avoid inlining functions that use computed goto. Wouldn't it be better to make the list implicit: every label in this function that has its address taken? You would have to modify every bit of code that thinks the CFG models control flow. /jakob From anton at korobeynikov.info Mon Jun 6 12:32:42 2011 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Mon, 6 Jun 2011 23:32:42 +0400 Subject: [llvm-commits] [Patch] Trivial fix for build failure on MinGW In-Reply-To: References: Message-ID: Hi Ruben, > Attached patch changes _MSC_VER to _WIN32 so that the correct version > of the mkdir function is called with all Win32 platforms. What was the problem with mkdir call on mingw/cygwin? -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From stuart at apple.com Mon Jun 6 13:03:22 2011 From: stuart at apple.com (Stuart Hastings) Date: Mon, 06 Jun 2011 20:03:22 -0000 Subject: [llvm-commits] [llvm] r132682 - /llvm/trunk/test/CodeGen/X86/2011-06-06-fgetsign80bit.ll Message-ID: <20110606200322.6EF742A6C12C@llvm.org> Author: stuart Date: Mon Jun 6 15:03:22 2011 New Revision: 132682 URL: http://llvm.org/viewvc/llvm-project?rev=132682&view=rev Log: Test case for PR10085. Added: llvm/trunk/test/CodeGen/X86/2011-06-06-fgetsign80bit.ll Added: llvm/trunk/test/CodeGen/X86/2011-06-06-fgetsign80bit.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-06-06-fgetsign80bit.ll?rev=132682&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2011-06-06-fgetsign80bit.ll (added) +++ llvm/trunk/test/CodeGen/X86/2011-06-06-fgetsign80bit.ll Mon Jun 6 15:03:22 2011 @@ -0,0 +1,8 @@ +; RUN: llc -march=x86-64 < %s +define i32 @signbitl(x86_fp80 %x) nounwind uwtable readnone { +entry: + %tmp4 = bitcast x86_fp80 %x to i80 + %tmp4.lobit = lshr i80 %tmp4, 79 + %tmp = trunc i80 %tmp4.lobit to i32 + ret i32 %tmp +} From aggarwa4 at illinois.edu Mon Jun 6 13:04:56 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Mon, 06 Jun 2011 20:04:56 -0000 Subject: [llvm-commits] [poolalloc] r132683 - /poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Message-ID: <20110606200456.8166E2A6C12C@llvm.org> Author: aggarwa4 Date: Mon Jun 6 15:04:56 2011 New Revision: 132683 URL: http://llvm.org/viewvc/llvm-project?rev=132683&view=rev Log: Improve formatting. Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=132683&r1=132682&r2=132683&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Mon Jun 6 15:04:56 2011 @@ -79,6 +79,11 @@ return UsedTypes[Ty]; } +unsigned int +TypeChecks::getTypeMarker(Value *V) { + return getTypeMarker(V->getType()); +} + bool TypeChecks::runOnModule(Module &M) { bool modified = false; // Flags whether we modified the module. @@ -94,15 +99,66 @@ Int64Ty = IntegerType::getInt64Ty(M.getContext()); VoidPtrTy = PointerType::getUnqual(Int8Ty); - RegisterArgv = M.getOrInsertFunction("trackArgvType", VoidTy, Int32Ty, VoidPtrTy->getPointerTo(), NULL); - trackGlobal = M.getOrInsertFunction("trackGlobal", VoidTy, VoidPtrTy, Int8Ty, Int64Ty, Int32Ty, NULL); - trackArray = M.getOrInsertFunction("trackArray", VoidTy, VoidPtrTy, Int64Ty, Int64Ty, Int32Ty, NULL); - trackInitInst = M.getOrInsertFunction("trackInitInst", VoidTy, VoidPtrTy, Int64Ty, Int32Ty, NULL); - trackUnInitInst = M.getOrInsertFunction("trackUnInitInst", VoidTy, VoidPtrTy, Int64Ty, Int32Ty, NULL); - trackStoreInst = M.getOrInsertFunction("trackStoreInst", VoidTy, VoidPtrTy, Int8Ty, Int64Ty, Int32Ty, NULL); - trackLoadInst = M.getOrInsertFunction("trackLoadInst", VoidTy, VoidPtrTy, Int8Ty, Int64Ty, Int32Ty, NULL); - copyTypeInfo = M.getOrInsertFunction("copyTypeInfo", VoidTy, VoidPtrTy, VoidPtrTy, Int64Ty, Int32Ty, NULL); - compareTypeAndNumber = M.getOrInsertFunction("compareTypeAndNumber", VoidTy, Int64Ty, Int64Ty, Int8Ty, VoidPtrTy, Int32Ty, NULL); + RegisterArgv = M.getOrInsertFunction("trackArgvType", + VoidTy, + Int32Ty, /*argc */ + VoidPtrTy->getPointerTo(),/*argv*/ + NULL); + trackGlobal = M.getOrInsertFunction("trackGlobal", + VoidTy, + VoidPtrTy,/*ptr*/ + Int8Ty,/*type*/ + Int64Ty,/*size*/ + Int32Ty,/*tag*/ + NULL); + trackArray = M.getOrInsertFunction("trackArray", + VoidTy, + VoidPtrTy,/*ptr*/ + Int64Ty,/*size*/ + Int64Ty,/*count*/ + Int32Ty,/*tag*/ + NULL); + trackInitInst = M.getOrInsertFunction("trackInitInst", + VoidTy, + VoidPtrTy,/*ptr*/ + Int64Ty,/*size*/ + Int32Ty,/*tag*/ + NULL); + trackUnInitInst = M.getOrInsertFunction("trackUnInitInst", + VoidTy, + VoidPtrTy,/*ptr*/ + Int64Ty,/*size*/ + Int32Ty,/*tag*/ + NULL); + trackStoreInst = M.getOrInsertFunction("trackStoreInst", + VoidTy, + VoidPtrTy,/*ptr*/ + Int8Ty,/*type*/ + Int64Ty,/*size*/ + Int32Ty,/*tag*/ + NULL); + trackLoadInst = M.getOrInsertFunction("trackLoadInst", + VoidTy, + VoidPtrTy,/*ptr*/ + Int8Ty,/*type*/ + Int64Ty,/*size*/ + Int32Ty,/*tag*/ + NULL); + copyTypeInfo = M.getOrInsertFunction("copyTypeInfo", + VoidTy, + VoidPtrTy,/*dest ptr*/ + VoidPtrTy,/*src ptr*/ + Int64Ty,/*size*/ + Int32Ty,/*tag*/ + NULL); + compareTypeAndNumber = M.getOrInsertFunction("compareTypeAndNumber", + VoidTy, + Int64Ty,/*Total Args*/ + Int64Ty,/*Arg accessed*/ + Int8Ty,/*type*/ + VoidPtrTy,/*metadata ptr*/ + Int32Ty,/*tag*/ + NULL); UsedTypes.clear(); // Reset if run multiple times. VAListFunctions.clear(); @@ -132,7 +188,7 @@ // Iterate and find all byval functions bool hasByValArg = false; - for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { + for (Function::arg_iterator I = F.arg_begin(); I != F.arg_end(); ++I) { if (I->hasByValAttr()) { hasByValArg = true; break; @@ -159,7 +215,7 @@ continue; const Type *ListPtrType = ListType->getPointerTo(); - for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { + for (Function::arg_iterator I = F.arg_begin(); I != F.arg_end(); ++I) { if(I->getType() == ListPtrType) { isVAListFunc = true; break; @@ -188,7 +244,8 @@ // iterate through all the VAList funtions and modify call sites // to call the new function - std::map::iterator FI = VAListFunctionsMap.begin(), FE = VAListFunctionsMap.end(); + std::map::iterator FI = VAListFunctionsMap.begin(), + FE = VAListFunctionsMap.end(); for(; FI != FE; FI++) { visitVAListCall(FI->second); } @@ -243,7 +300,8 @@ // visit all the uses of the address taken functions and modify if // visit all the indirect call sites - for(std::set::iterator II = IndCalls.begin(); II != IndCalls.end(); ) { + std::set::iterator II = IndCalls.begin(); + for(; II != IndCalls.end();) { Instruction *I = *II++; modified |= visitIndirectCallSite(M,I); } @@ -287,12 +345,15 @@ CA, ""); GV->setInitializer(CA); - Constant *C = ConstantExpr::getGetElementPtr(GV, &Indices[0], Indices.size()); + Constant *C = ConstantExpr::getGetElementPtr(GV, + &Indices[0], + Indices.size()); Values[0] = C; // For each used type, create a new entry. // Also add these strings to the Values list - std::map::iterator TI = UsedTypes.begin(), TE = UsedTypes.end(); + std::map::iterator TI = UsedTypes.begin(), + TE = UsedTypes.end(); for(;TI!=TE; ++TI) { std::string *type = new std::string(); llvm::raw_string_ostream *test = new llvm::raw_string_ostream(*type); @@ -306,7 +367,9 @@ CA, ""); GV->setInitializer(CA); - Constant *C = ConstantExpr::getGetElementPtr(GV, &Indices[0], Indices.size()); + Constant *C = ConstantExpr::getGetElementPtr(GV, + &Indices[0], + Indices.size()); Values[TI->second]= C; } @@ -314,7 +377,7 @@ AType, true, GlobalValue::ExternalLinkage, - ConstantArray::get(AType, &Values[0], UsedTypes.size() + 1), + ConstantArray::get(AType,&Values[0],UsedTypes.size()+1), "typeNames" ); } @@ -337,7 +400,10 @@ // Add the original argument Args.push_back(CI->getOperand(i)); } - CallInst *CINew = CallInst::Create(VAListFunctionsMap[CalledF], Args.begin(), Args.end(), "", CI); + CallInst *CINew = CallInst::Create(VAListFunctionsMap[CalledF], + Args.begin(), + Args.end(), + "", CI); CI->replaceAllUsesWith(CINew); CI->eraseFromParent(); } @@ -355,7 +421,8 @@ return false; const Type *ListPtrType = ListType->getPointerTo(); Argument *VAListArg = NULL; - for (Function::arg_iterator I = F_orig.arg_begin(), E = F_orig.arg_end(); I != E; ++I) { + for (Function::arg_iterator I = F_orig.arg_begin(); + I != F_orig.arg_end(); ++I) { VAListArgNum ++; if(I->getType() == ListPtrType) { VAListArg = I; @@ -370,11 +437,14 @@ TP.push_back(Int64Ty); // for count TP.push_back(Int64Ty); // for count TP.push_back(VoidPtrTy); // for MD - for (Function::arg_iterator I = F_orig.arg_begin(), E = F_orig.arg_end(); I != E; ++I) { + for (Function::arg_iterator I = F_orig.arg_begin(); + I != F_orig.arg_end(); ++I) { TP.push_back(I->getType()); } // 2. Create the new function prototype - const FunctionType *NewFTy = FunctionType::get(F_orig.getReturnType(), TP, false); + const FunctionType *NewFTy = FunctionType::get(F_orig.getReturnType(), + TP,/*argument types*/ + false);/*vararg*/ Function *F = Function::Create(NewFTy, GlobalValue::InternalLinkage, F_orig.getNameStr() + ".INT", @@ -389,18 +459,21 @@ NI++; NI->setName("MD"); NI++; - for (Function::arg_iterator II = F_orig.arg_begin(); NI != F->arg_end(); ++II, ++NI) { + for (Function::arg_iterator II = F_orig.arg_begin(); + NI != F->arg_end(); ++II, ++NI) { // Each new argument maps to the argument in the old function // For these arguments, also copy over the attributes ValueMap[II] = NI; NI->setName(II->getName()); - NI->addAttr(F_orig.getAttributes().getParamAttributes(II->getArgNo() + 1)); + NI->addAttr(F_orig.getAttributes() + .getParamAttributes(II->getArgNo() + 1)); } // 4. Copy over the attributes for the function. F->setAttributes(F->getAttributes() .addAttr(0, F_orig.getAttributes().getRetAttributes())); - F->setAttributes(F->getAttributes().addAttr(~0, F_orig.getAttributes().getFnAttributes())); + F->setAttributes(F->getAttributes() + .addAttr(~0, F_orig.getAttributes().getFnAttributes())); // 5. Perform the cloning. SmallVector Returns; @@ -439,10 +512,13 @@ Instruction *VAMetaData = new LoadInst(VAMDLoc, "", VI); Args.push_back(VASize); Args.push_back(OldValue); - Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(VI->getType()))); + Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(VI))); Args.push_back(VAMetaData); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - CallInst::Create(compareTypeAndNumber, Args.begin(), Args.end(), "", VI); + CallInst::Create(compareTypeAndNumber, + Args.begin(), + Args.end(), + "", VI); } } @@ -455,12 +531,14 @@ std::vector TP; TP.push_back(Int64Ty); // for count TP.push_back(VoidPtrTy); // for MD - for(Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I !=E; ++I) { + for(Function::arg_iterator I = F.arg_begin(); I !=F.arg_end(); ++I) { TP.push_back(I->getType()); } // 2. Create the new function prototype - const FunctionType *NewFTy = FunctionType::get(F.getReturnType(), TP, false); + const FunctionType *NewFTy = FunctionType::get(F.getReturnType(), + TP, + false); Function *NewF = Function::Create(NewFTy, GlobalValue::InternalLinkage, F.getNameStr() + ".mod", @@ -473,7 +551,8 @@ NI++; NI->setName("MD"); NI++; - for(Function::arg_iterator II = F.arg_begin(); NI!=NewF->arg_end(); ++II, ++NI) { + for(Function::arg_iterator II = F.arg_begin(); + NI!=NewF->arg_end(); ++II, ++NI) { // Each new argument maps to the argument in the old function // For each of these also copy attributes ValueMap[II] = NI; @@ -484,7 +563,8 @@ // 4. Copy over attributes for the function NewF->setAttributes(NewF->getAttributes() .addAttr(0, F.getAttributes().getRetAttributes())); - NewF->setAttributes(NewF->getAttributes().addAttr(~0, F.getAttributes().getFnAttributes())); + NewF->setAttributes(NewF->getAttributes() + .addAttr(~0, F.getAttributes().getFnAttributes())); // 5. Perform the cloning SmallVectorReturns; @@ -513,7 +593,7 @@ Idx + 1, "", CI); Constant *C = ConstantInt::get(Int8Ty, - getTypeMarker(CI->getOperand(i)->getType())); + getTypeMarker(CI->getOperand(i))); new StoreInst(C, GEP, CI); } @@ -577,12 +657,14 @@ std::vector TP; TP.push_back(Int64Ty); // for count TP.push_back(VoidPtrTy); // for MD - for(Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I !=E; ++I) { + for(Function::arg_iterator I = F.arg_begin(); I !=F.arg_end(); ++I) { TP.push_back(I->getType()); } // 2. Create the new function prototype - const FunctionType *NewFTy = FunctionType::get(F.getReturnType(), TP, true); + const FunctionType *NewFTy = FunctionType::get(F.getReturnType(), + TP, + true); Function *NewF = Function::Create(NewFTy, GlobalValue::InternalLinkage, F.getNameStr() + ".mod", @@ -595,7 +677,8 @@ NI++; NI->setName("MD"); NI++; - for(Function::arg_iterator II = F.arg_begin(); NI!=NewF->arg_end(); ++II, ++NI) { + for(Function::arg_iterator II = F.arg_begin(); + NI!=NewF->arg_end(); ++II, ++NI) { // Each new argument maps to the argument in the old function // For each of these also copy attributes ValueMap[II] = NI; @@ -606,7 +689,8 @@ // 4. Copy over attributes for the function NewF->setAttributes(NewF->getAttributes() .addAttr(0, F.getAttributes().getRetAttributes())); - NewF->setAttributes(NewF->getAttributes().addAttr(~0, F.getAttributes().getFnAttributes())); + NewF->setAttributes(NewF->getAttributes() + .addAttr(~0, F.getAttributes().getFnAttributes())); // 5. Perform the cloning SmallVectorReturns; @@ -664,10 +748,13 @@ Instruction *VAMetaData = new LoadInst(VAMDLoc, "", VI); Args.push_back(VASize); Args.push_back(OldValue); - Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(VI->getType()))); + Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(VI))); Args.push_back(VAMetaData); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - CallInst::Create(compareTypeAndNumber, Args.begin(), Args.end(), "", VI); + CallInst::Create(compareTypeAndNumber, + Args.begin(), + Args.end(), + "", VI); } } @@ -741,7 +828,7 @@ Idx + 1, "", CI); Constant *C = ConstantInt::get(Int8Ty, - getTypeMarker(CI->getOperand(i)->getType())); + getTypeMarker(CI->getOperand(i))); new StoreInst(C, GEP, CI); } @@ -796,7 +883,7 @@ // for every byval argument // add an alloca, a load, and a store inst Instruction * InsertBefore = &(F.getEntryBlock().front()); - for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { + for (Function::arg_iterator I = F.arg_begin(); I != F.arg_end(); ++I) { if (!I->hasByValAttr()) continue; if(EnableTypeSafeOpt) { @@ -839,7 +926,7 @@ if(EnableTypeSafeOpt) { if(TS->isTypeSafe(II, CI->getParent()->getParent())) { if (Attributes Attrs = CallPAL.getParamAttributes(j)) - AttributesVec.push_back(AttributeWithIndex::get(Args.size(), Attrs)); + AttributesVec.push_back(AttributeWithIndex::get(j, Attrs)); continue; } } @@ -847,7 +934,7 @@ if(II->hasByValAttr()) continue; if (Attributes Attrs = CallPAL.getParamAttributes(j)) { - AttributesVec.push_back(AttributeWithIndex::get(Args.size(), Attrs)); + AttributesVec.push_back(AttributeWithIndex::get(j, Attrs)); } } @@ -860,7 +947,11 @@ // Create the substitute call - CallInst *CallI = CallInst::Create(&F,Args.begin(), Args.end(),"", CI); + CallInst *CallI = CallInst::Create(&F, + Args.begin(), + Args.end(), + "", CI); + CallI->setCallingConv(CI->getCallingConv()); CallI->setAttributes(NewCallPAL); CI->replaceAllUsesWith(CallI); @@ -870,7 +961,7 @@ } // remove the byval attribute from the function - for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { + for (Function::arg_iterator I = F.arg_begin(); I != F.arg_end(); ++I) { if (!I->hasByValAttr()) continue; if(EnableTypeSafeOpt) { @@ -887,20 +978,20 @@ // A list of the byval arguments that we are setting metadata for typedef SmallVector RegisteredArgTy; RegisteredArgTy registeredArguments; - for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { + for (Function::arg_iterator I = F.arg_begin(); I != F.arg_end(); ++I) { if (I->hasByValAttr()) { assert (isa(I->getType())); const PointerType * PT = cast(I->getType()); const Type * ET = PT->getElementType(); Value * AllocSize = ConstantInt::get(Int64Ty, TD->getTypeAllocSize(ET)); - Instruction * InsertBefore = &(F.getEntryBlock().front()); - CastInst *BCI = BitCastInst::CreatePointerCast(I, VoidPtrTy, "", InsertBefore); + Instruction * InsertPt = &(F.getEntryBlock().front()); + CastInst *BCI = BitCastInst::CreatePointerCast(I, VoidPtrTy, "", InsertPt); std::vector Args; Args.push_back(BCI); Args.push_back(AllocSize); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); // Set the metadata for the byval argument to TOP/Initialized - CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", InsertBefore); + CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", InsertBePt); registeredArguments.push_back(&*I); } } @@ -941,7 +1032,9 @@ // symbol table from the module. void TypeChecks::print(raw_ostream &OS, const Module *M) const { OS << "Types in use by this module:\n"; - for (std::map::const_iterator I = UsedTypes.begin(), E = UsedTypes.end(); I != E; ++I) { + std::map::const_iterator I = UsedTypes.begin(), + E = UsedTypes.end(); + for (; I != E; ++I) { OS << " "; WriteTypeSymbolic(OS, I->first, M); OS << '\n'; @@ -1135,7 +1228,7 @@ std::vector Args; Args.push_back(GEP); - Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(CAZ->getType()))); + Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(CAZ))); Args.push_back(ConstantInt::get(Int64Ty, TD->getTypeStoreSize(CAZ->getType()))); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); CallInst::Create(trackGlobal, Args.begin(), Args.end(), "", &I); @@ -1151,7 +1244,7 @@ std::vector Args; Args.push_back(GEP); - Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(C->getType()))); + Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(C))); Args.push_back(ConstantInt::get(Int64Ty, TD->getTypeStoreSize(C->getType()))); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); CallInst::Create(trackGlobal, Args.begin(), Args.end(), "", &I); @@ -1467,7 +1560,7 @@ Idx + 1, "", I); Constant *C = ConstantInt::get(Int8Ty, - getTypeMarker(I->getOperand(i)->getType())); + getTypeMarker(I->getOperand(i))); new StoreInst(C, GEP, I); } std::vector Args; @@ -1532,7 +1625,7 @@ std::vector Args; Args.push_back(BCI); - Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(LI.getType()))); + Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(&LI))); Args.push_back(ConstantInt::get(Int64Ty, TD->getTypeStoreSize(LI.getType()))); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); @@ -1555,7 +1648,7 @@ std::vector Args; Args.push_back(BCI); Args.push_back(ConstantInt::get(Int8Ty, - getTypeMarker(SI.getOperand(0)->getType()))); // SI.getValueOperand() + getTypeMarker(SI.getOperand(0)))); // SI.getValueOperand() Args.push_back(ConstantInt::get(Int64Ty, TD->getTypeStoreSize(SI.getOperand(0)->getType()))); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); From aggarwa4 at illinois.edu Mon Jun 6 13:05:28 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Mon, 06 Jun 2011 20:05:28 -0000 Subject: [llvm-commits] [poolalloc] r132684 - /poolalloc/trunk/include/assistDS/TypeChecks.h Message-ID: <20110606200528.B9AF82A6C12C@llvm.org> Author: aggarwa4 Date: Mon Jun 6 15:05:28 2011 New Revision: 132684 URL: http://llvm.org/viewvc/llvm-project?rev=132684&view=rev Log: Forgot header file. Modified: poolalloc/trunk/include/assistDS/TypeChecks.h Modified: poolalloc/trunk/include/assistDS/TypeChecks.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/TypeChecks.h?rev=132684&r1=132683&r2=132684&view=diff ============================================================================== --- poolalloc/trunk/include/assistDS/TypeChecks.h (original) +++ poolalloc/trunk/include/assistDS/TypeChecks.h Mon Jun 6 15:05:28 2011 @@ -84,6 +84,7 @@ void visitVAListCall(Function *F); unsigned int getTypeMarker(const llvm::Type*); + unsigned int getTypeMarker(Value*); // Return the map containing all of the types used in the module. const std::map &getTypes() const { return UsedTypes; From aggarwa4 at illinois.edu Mon Jun 6 13:16:54 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Mon, 06 Jun 2011 20:16:54 -0000 Subject: [llvm-commits] [poolalloc] r132685 - /poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Message-ID: <20110606201654.71A782A6C12C@llvm.org> Author: aggarwa4 Date: Mon Jun 6 15:16:54 2011 New Revision: 132685 URL: http://llvm.org/viewvc/llvm-project?rev=132685&view=rev Log: 1. Handle some cases with invoke inst. 2. Hack to support string input using scanf family 3. Initial support for indirect calls. This version currently does not work well with DSA optimization. Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=132685&r1=132684&r2=132685&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Mon Jun 6 15:16:54 2011 @@ -57,6 +57,7 @@ static const Type *Int64Ty = 0; static const PointerType *VoidPtrTy = 0; static Constant *trackGlobal; +static Constant *trackStringInput; static Constant *trackArray; static Constant *trackInitInst; static Constant *trackUnInitInst; @@ -159,6 +160,11 @@ VoidPtrTy,/*metadata ptr*/ Int32Ty,/*tag*/ NULL); + trackStringInput = M.getOrInsertFunction("trackStringInput", + VoidTy, + VoidPtrTy, + Int32Ty, + NULL); UsedTypes.clear(); // Reset if run multiple times. VAListFunctions.clear(); @@ -249,6 +255,20 @@ for(; FI != FE; FI++) { visitVAListCall(FI->second); } + while(!VAArgFunctions.empty()) { + Function *F = VAArgFunctions.back(); + VAArgFunctions.pop_back(); + assert(F->isVarArg()); + modified |= visitVarArgFunction(M, *F); + } + + while(!AddressTakenFunctions.empty()) { + Function *F = AddressTakenFunctions.back(); + AddressTakenFunctions.pop_back(); + if(F->isVarArg()) + continue; + visitAddressTakenFunction(M, *F); + } for (Module::iterator MI = M.begin(), ME = M.end(); MI != ME; ++MI) { Function &F = *MI; @@ -282,21 +302,6 @@ } } - while(!VAArgFunctions.empty()) { - Function *F = VAArgFunctions.back(); - VAArgFunctions.pop_back(); - assert(F->isVarArg()); - modified |= visitVarArgFunction(M, *F); - } - - while(!AddressTakenFunctions.empty()) { - Function *F = AddressTakenFunctions.back(); - AddressTakenFunctions.pop_back(); - errs() << F->getNameStr()<<"\n"; - if(F->isVarArg()) - continue; - visitAddressTakenFunction(M, *F); - } // visit all the uses of the address taken functions and modify if // visit all the indirect call sites @@ -307,8 +312,37 @@ } FI = IndFunctionsMap.begin(), FE = IndFunctionsMap.end(); for(;FI!=FE;++FI) { - Constant *C = ConstantExpr::getBitCast(FI->second, FI->first->getType()); - FI->first->replaceAllUsesWith(C); + Function *F = FI->first; + std::vector toReplace; + for(Function::use_iterator User = F->use_begin(); + User != F->use_end();++User) { + toReplace.push_back(*User); + } + Constant *CNew = ConstantExpr::getBitCast(FI->second, F->getType()); + while (toReplace.size()) { + llvm::User * user = toReplace.back(); + toReplace.pop_back(); + if(Constant *C = dyn_cast(user)) { + if(!isa(C)) { + std::vector ReplaceWorklist; + for (User::op_iterator use = user->op_begin(); + use != user->op_end(); + ++use) { + if (use->get() == F) { + ReplaceWorklist.push_back (use); + } + } + + // + // Do replacements in the worklist. + // + for (unsigned index = 0; index < ReplaceWorklist.size(); ++index) + C->replaceUsesOfWithOnConstant(F, CNew, ReplaceWorklist[index]); + continue; + } + } + user->replaceUsesOfWith(F, CNew); + } } @@ -810,6 +844,10 @@ for(Value::use_iterator ui = F.use_begin(), ue = F.use_end(); ui != ue;) { // Check for call sites + if(isa(ui)) { + //FIXME + ui->dump(); + } CallInst *CI = dyn_cast(ui++); if(!CI) continue; @@ -903,6 +941,10 @@ // Update the call sites for(Value::use_iterator ui = F.use_begin(), ue = F.use_end(); ui != ue;) { + if(isa(ui)) { + //FIXME + ui->dump(); + } // Check that F is the called value if(CallInst *CI = dyn_cast(ui++)) { if(CI->getCalledFunction() == &F) { @@ -991,7 +1033,7 @@ Args.push_back(AllocSize); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); // Set the metadata for the byval argument to TOP/Initialized - CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", InsertBePt); + CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", InsertPt); registeredArguments.push_back(&*I); } } @@ -1582,12 +1624,38 @@ const FunctionType *FTy = FunctionType::get(FOldType->getReturnType(), TP, FOldType->isVarArg()); CastInst *Func = CastInst::CreatePointerCast(I->getOperand(0), FTy->getPointerTo(), "", I); - CallInst *CI_New = CallInst::Create(Func, - Args.begin(), - Args.end(), - "", I); - I->replaceAllUsesWith(CI_New); - I->eraseFromParent(); + if(isa(I)) { + std::vector Args; + Args.push_back(ConstantInt::get(Int64Ty, NumArgs)); + Args.push_back(AI); + + for(unsigned int i = 1; i < I->getNumOperands(); i++) + Args.push_back(I->getOperand(i)); + CallInst *CI_New = CallInst::Create(Func, + Args.begin(), + Args.end(), + "", I); + I->replaceAllUsesWith(CI_New); + I->eraseFromParent(); + } else if(InvokeInst *II = dyn_cast(I)) { + std::vector Args; + Args.push_back(ConstantInt::get(Int64Ty, NumArgs)); + Args.push_back(AI); + + for(unsigned int i = 3; i < I->getNumOperands(); i++) { + Args.push_back(I->getOperand(i)); + } + + InvokeInst *INew = InvokeInst::Create(Func, + II->getNormalDest(), + II->getUnwindDest(), + Args.begin(), + Args.end(), + "", I); + I->replaceAllUsesWith(INew); + I->eraseFromParent(); + + } // add they types of the argument as the second argument @@ -1610,6 +1678,16 @@ // Create the call to the runtime check and place it before the store instruction. CallInst::Create(trackStoreInst, Args.begin(), Args.end(), "", CI); + if(PTy == VoidPtrTy) { + // TODO: This is currently a heuristic for strings. If we see a i8* in a call to + // input functions, treat as string, and get length using strlen. + std::vector Args; + Args.push_back(BCI); + Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + CallInst *CINew = CallInst::Create(trackStringInput, Args.begin(), Args.end()); + CINew->insertAfter(CI); + } + return true; } From vanboxem.ruben at gmail.com Mon Jun 6 13:25:08 2011 From: vanboxem.ruben at gmail.com (Ruben Van Boxem) Date: Mon, 6 Jun 2011 22:25:08 +0200 Subject: [llvm-commits] [Patch] Trivial fix for build failure on MinGW In-Reply-To: References: Message-ID: 2011/6/6 Anton Korobeynikov : > Hi Ruben, > >> Attached patch changes _MSC_VER to _WIN32 so that the correct version >> of the mkdir function is called with all Win32 platforms. > What was the problem with mkdir call on mingw/cygwin? The used overload (with a second argument) doesn't exist for MinGW, because it doesn't exist for MSVC. MinGW is as close to MSVC as it can be API-wise, so what goes for MSVC should work for MinGW, or it's a bug or difficult to implement feature. Cygwin probably has the second overload, but shouldn't define _WIN32 AFAIK. Cygwin isn't Win32 as far as anything is concerned. It's __CYGWIN__, not _WIN32 For reference, the error message I got: > M:\Development\Source\LLVM\runtime\libprofile\GCDAProfiling.c: In function 'recursive_mkdir': > M:\Development\Source\LLVM\runtime\libprofile\GCDAProfiling.c:95:7: error: too many arguments to function 'mkdir' > m:\development\mingw64\bin\../lib/gcc/x86_64-w64-mingw32/4.6.1/../../../../x86_64-w64-mingw32/include/io.h:267:15: note: declared here > > -- > With best regards, Anton Korobeynikov > Faculty of Mathematics and Mechanics, Saint Petersburg State University > From nicholas at mxc.ca Mon Jun 6 13:23:00 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Mon, 06 Jun 2011 20:23:00 -0000 Subject: [llvm-commits] [llvm] r132686 - in /llvm/trunk/test/Transforms/PhaseOrdering: basic.ll dg.exp Message-ID: <20110606202301.0125B2A6C12C@llvm.org> Author: nicholas Date: Mon Jun 6 15:23:00 2011 New Revision: 132686 URL: http://llvm.org/viewvc/llvm-project?rev=132686&view=rev Log: This directory was missing the dg.exp to cause the tests to run. Some time since it was added, the test has regressed, so XFAIL it. Added: llvm/trunk/test/Transforms/PhaseOrdering/dg.exp Modified: llvm/trunk/test/Transforms/PhaseOrdering/basic.ll Modified: llvm/trunk/test/Transforms/PhaseOrdering/basic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/PhaseOrdering/basic.ll?rev=132686&r1=132685&r2=132686&view=diff ============================================================================== --- llvm/trunk/test/Transforms/PhaseOrdering/basic.ll (original) +++ llvm/trunk/test/Transforms/PhaseOrdering/basic.ll Mon Jun 6 15:23:00 2011 @@ -1,4 +1,5 @@ ; RUN: opt -O3 -S %s | FileCheck %s +; XFAIL: * target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-apple-macosx10.6.7" Added: llvm/trunk/test/Transforms/PhaseOrdering/dg.exp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/PhaseOrdering/dg.exp?rev=132686&view=auto ============================================================================== --- llvm/trunk/test/Transforms/PhaseOrdering/dg.exp (added) +++ llvm/trunk/test/Transforms/PhaseOrdering/dg.exp Mon Jun 6 15:23:00 2011 @@ -0,0 +1,3 @@ +load_lib llvm.exp + +RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]] From anton at korobeynikov.info Mon Jun 6 13:40:17 2011 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Tue, 7 Jun 2011 00:40:17 +0400 Subject: [llvm-commits] [Patch] Trivial fix for build failure on MinGW In-Reply-To: References: Message-ID: Hi Ruben, > For reference, the error message I got: >> M:\Development\Source\LLVM\runtime\libprofile\GCDAProfiling.c: In function 'recursive_mkdir': >> M:\Development\Source\LLVM\runtime\libprofile\GCDAProfiling.c:95:7: error: too many arguments to function 'mkdir' >> m:\development\mingw64\bin\../lib/gcc/x86_64-w64-mingw32/4.6.1/../../../../x86_64-w64-mingw32/include/io.h:267:15: note: declared here Ok, looks good to me then, please commit! -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From nadav.rotem at intel.com Mon Jun 6 13:55:56 2011 From: nadav.rotem at intel.com (Nadav Rotem) Date: Mon, 06 Jun 2011 20:55:56 -0000 Subject: [llvm-commits] [llvm] r132689 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp lib/CodeGen/SelectionDAG/LegalizeTypes.h lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp test/CodeGen/Generic/basic-promote-integers.ll Message-ID: <20110606205557.1172E2A6C12C@llvm.org> Author: nadav Date: Mon Jun 6 15:55:56 2011 New Revision: 132689 URL: http://llvm.org/viewvc/llvm-project?rev=132689&view=rev Log: Add methods to support the integer-promotion of vector types. Methods to legalize SDNodes such as BUILD_VECTOR, EXTRACT_VECTOR_ELT, etc. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp llvm/trunk/test/CodeGen/Generic/basic-promote-integers.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=132689&r1=132688&r2=132689&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Mon Jun 6 15:55:56 2011 @@ -73,6 +73,17 @@ case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break; case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break; + case ISD::EXTRACT_SUBVECTOR: + Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break; + case ISD::VECTOR_SHUFFLE: + Res = PromoteIntRes_VECTOR_SHUFFLE(N); break; + case ISD::INSERT_VECTOR_ELT: + Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break; + case ISD::BUILD_VECTOR: + Res = PromoteIntRes_BUILD_VECTOR(N); break; + case ISD::SCALAR_TO_VECTOR: + Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break; + case ISD::SIGN_EXTEND: case ISD::ZERO_EXTEND: case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break; @@ -180,6 +191,10 @@ if (NOutVT.bitsEq(NInVT)) // The input promotes to the same size. Convert the promoted value. return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); + if (NInVT.isVector()) + // Promote vector element via memory load/store. + return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, + CreateStackStoreLoad(InOp, OutVT)); break; case TargetLowering::TypeSoftenFloat: // Promote the integer operand by hand. @@ -673,6 +688,8 @@ case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break; case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break; + case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break; + case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break; case ISD::CONVERT_RNDSAT: Res = PromoteIntOp_CONVERT_RNDSAT(N); break; case ISD::INSERT_VECTOR_ELT: @@ -2617,3 +2634,159 @@ "Don't know how to expand this UINT_TO_FP!"); return MakeLibCall(LC, DstVT, &Op, 1, true, dl); } + +SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) { + SDValue InOp0 = N->getOperand(0); + EVT InVT = InOp0.getValueType(); + EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); + + EVT OutVT = N->getValueType(0); + EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); + assert(NOutVT.isVector() && "This type must be promoted to a vector type"); + unsigned OutNumElems = N->getValueType(0).getVectorNumElements(); + EVT NOutVTElem = NOutVT.getVectorElementType(); + + DebugLoc dl = N->getDebugLoc(); + SDValue BaseIdx = N->getOperand(1); + + SmallVector Ops; + for (unsigned i = 0; i != OutNumElems; ++i) { + + // Extract the element from the original vector. + SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(), + BaseIdx, DAG.getIntPtrConstant(i)); + SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, + InVT.getVectorElementType(), N->getOperand(0), Index); + + SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext); + // Insert the converted element to the new vector. + Ops.push_back(Op); + } + + return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size()); +} + + +SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) { + + ShuffleVectorSDNode *SV = cast(N); + EVT VT = N->getValueType(0); + DebugLoc dl = N->getDebugLoc(); + + unsigned NumElts = VT.getVectorNumElements(); + SmallVector NewMask; + for (unsigned i = 0; i != NumElts; ++i) { + NewMask.push_back(SV->getMaskElt(i)); + } + + SDValue V0 = GetPromotedInteger(N->getOperand(0)); + SDValue V1 = GetPromotedInteger(N->getOperand(1)); + EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); + + return DAG.getVectorShuffle(OutVT, dl, V0,V1, &NewMask[0]); +} + + +SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) { + + SDValue InOp0 = N->getOperand(0); + EVT InVT = InOp0.getValueType(); + EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); + + EVT OutVT = N->getValueType(0); + EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); + assert(NOutVT.isVector() && "This type must be promoted to a vector type"); + unsigned NumElems = N->getNumOperands(); + EVT NOutVTElem = NOutVT.getVectorElementType(); + + DebugLoc dl = N->getDebugLoc(); + + SmallVector Ops; + for (unsigned i = 0; i != NumElems; ++i) { + SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i)); + Ops.push_back(Op); + } + + return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size()); +} + +SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) { + + DebugLoc dl = N->getDebugLoc(); + + SDValue InOp0 = N->getOperand(0); + EVT InVT = InOp0.getValueType(); + EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); + assert(!InVT.isVector() && "Input must not be a scalar"); + + EVT OutVT = N->getValueType(0); + EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); + assert(NOutVT.isVector() && "This type must be promoted to a vector type"); + EVT NOutVTElem = NOutVT.getVectorElementType(); + + SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0)); + + return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op); +} + +SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) { + + SDValue InOp0 = N->getOperand(0); + EVT InVT = InOp0.getValueType(); + EVT InElVT = InVT.getVectorElementType(); + EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); + + EVT OutVT = N->getValueType(0); + EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); + assert(NOutVT.isVector() && "This type must be promoted to a vector type"); + + EVT NOutVTElem = NOutVT.getVectorElementType(); + + DebugLoc dl = N->getDebugLoc(); + + SDValue ConvertedVector = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, InOp0); + + SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl, + NOutVTElem, N->getOperand(1)); + return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,NOutVT, + ConvertedVector, ConvElem, N->getOperand(2)); +} + +SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) { + DebugLoc dl = N->getDebugLoc(); + SDValue V0 = GetPromotedInteger(N->getOperand(0)); + SDValue V1 = N->getOperand(1); + SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, + V0->getValueType(0).getScalarType(), V0, V1); + + return DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), Ext); + +} + +SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) { + + DebugLoc dl = N->getDebugLoc(); + + EVT RetSclrTy = N->getValueType(0).getVectorElementType(); + + SmallVector NewOps; + + // For each incoming vector + for (unsigned VecIdx = 0, E = N->getNumOperands(); VecIdx!= E; ++VecIdx) { + SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx)); + EVT SclrTy = Incoming->getValueType(0).getVectorElementType(); + unsigned NumElem = Incoming->getValueType(0).getVectorNumElements(); + + for (unsigned i=0; igetValueType(0), + &NewOps[0], NewOps.size()); + } + Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=132689&r1=132688&r2=132689&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Mon Jun 6 15:55:56 2011 @@ -210,6 +210,11 @@ SDValue PromoteIntRes_AssertZext(SDNode *N); SDValue PromoteIntRes_Atomic1(AtomicSDNode *N); SDValue PromoteIntRes_Atomic2(AtomicSDNode *N); + SDValue PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N); + SDValue PromoteIntRes_VECTOR_SHUFFLE(SDNode *N); + SDValue PromoteIntRes_BUILD_VECTOR(SDNode *N); + SDValue PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N); + SDValue PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N); SDValue PromoteIntRes_BITCAST(SDNode *N); SDValue PromoteIntRes_BSWAP(SDNode *N); SDValue PromoteIntRes_BUILD_PAIR(SDNode *N); @@ -251,6 +256,9 @@ SDValue PromoteIntOp_BUILD_VECTOR(SDNode *N); SDValue PromoteIntOp_CONVERT_RNDSAT(SDNode *N); SDValue PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, unsigned OpNo); + SDValue PromoteIntOp_EXTRACT_ELEMENT(SDNode *N); + SDValue PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N); + SDValue PromoteIntOp_CONCAT_VECTORS(SDNode *N); SDValue PromoteIntOp_MEMBARRIER(SDNode *N); SDValue PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N); SDValue PromoteIntOp_SELECT(SDNode *N, unsigned OpNo); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=132689&r1=132688&r2=132689&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Mon Jun 6 15:55:56 2011 @@ -783,6 +783,17 @@ DAG.getIntPtrConstant(InNVT.getVectorNumElements())); break; } + case TargetLowering::TypePromoteInteger: { + SDValue InOp = GetPromotedInteger(N->getOperand(0)); + EVT InNVT = EVT::getVectorVT(*DAG.getContext(), + InOp.getValueType().getVectorElementType(), + LoVT.getVectorNumElements()); + Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, + DAG.getIntPtrConstant(0)); + Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, + DAG.getIntPtrConstant(InNVT.getVectorNumElements())); + break; + } case TargetLowering::TypeSplitVector: GetSplitVector(N->getOperand(0), Lo, Hi); break; Modified: llvm/trunk/test/CodeGen/Generic/basic-promote-integers.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/basic-promote-integers.ll?rev=132689&r1=132688&r2=132689&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Generic/basic-promote-integers.ll (original) +++ llvm/trunk/test/CodeGen/Generic/basic-promote-integers.ll Mon Jun 6 15:55:56 2011 @@ -3,7 +3,7 @@ ; RUN: llc -march=x86 -promote-elements < %s ; RUN: llc -march=x86 < %s -; A simple test to check copyToParts and copyFromParts +; A simple test to check copyToParts and copyFromParts. define <4 x i64> @test_param_0(<4 x i64> %A, <2 x i32> %B, <4 x i8> %C) { ret <4 x i64> %A @@ -17,4 +17,75 @@ ret <4 x i8> %C } +; Simple tests to check arithmetic and vector operations on types which need to +; be legalized (no loads/stores to/from memory here). + +define <4 x i64> @test_arith_0(<4 x i64> %A, <2 x i32> %B, <4 x i8> %C) { + %K = add <4 x i64> %A, + ret <4 x i64> %K +} + +define <2 x i32> @test_arith_1(<4 x i64> %A, <2 x i32> %B, <4 x i8> %C) { + %K = add <2 x i32> %B, + ret <2 x i32> %K +} + +define <4 x i8> @test_arith_2(<4 x i64> %A, <2 x i32> %B, <4 x i8> %C) { + %K = add <4 x i8> %C, + ret <4 x i8> %K +} + +define i8 @test_arith_3(<4 x i64> %A, <2 x i32> %B, <4 x i8> %C) { + %K = add <4 x i8> %C, + %Y = extractelement <4 x i8> %K, i32 1 + ret i8 %Y +} + +define <4 x i8> @test_arith_4(<4 x i64> %A, <2 x i32> %B, <4 x i8> %C) { + %Y = insertelement <4 x i8> %C, i8 1, i32 0 + ret <4 x i8> %Y +} + +define <4 x i32> @test_arith_5(<4 x i64> %A, <2 x i32> %B, <4 x i32> %C) { + %Y = insertelement <4 x i32> %C, i32 1, i32 0 + ret <4 x i32> %Y +} + +define <4 x i32> @test_arith_6(<4 x i64> %A, <2 x i32> %B, <4 x i32> %C) { + %F = extractelement <2 x i32> %B, i32 1 + %Y = insertelement <4 x i32> %C, i32 %F, i32 0 + ret <4 x i32> %Y +} + +define <4 x i64> @test_arith_7(<4 x i64> %A, <2 x i32> %B, <4 x i32> %C) { + %F = extractelement <2 x i32> %B, i32 1 + %W = zext i32 %F to i64 + %Y = insertelement <4 x i64> %A, i64 %W, i32 0 + ret <4 x i64> %Y +} + +define i64 @test_arith_8(<4 x i64> %A, <2 x i32> %B, <4 x i32> %C) { + %F = extractelement <2 x i32> %B, i32 1 + %W = zext i32 %F to i64 + %T = add i64 %W , 11 + ret i64 %T +} + +define <4 x i64> @test_arith_9(<4 x i64> %A, <2 x i32> %B, <4 x i16> %C) { + %T = add <4 x i16> %C, %C + %F0 = extractelement <4 x i16> %T, i32 0 + %F1 = extractelement <4 x i16> %T, i32 1 + %W0 = zext i16 %F0 to i64 + %W1 = zext i16 %F1 to i64 + %Y0 = insertelement <4 x i64> %A, i64 %W0, i32 0 + %Y1 = insertelement <4 x i64> %Y0, i64 %W1, i32 2 + ret <4 x i64> %Y1 +} + + +define <4 x i16> @test_arith_10(<4 x i64> %A, <2 x i32> %B, <4 x i32> %C) { + %F = bitcast <2 x i32> %B to <4 x i16> + %T = add <4 x i16> %F , + ret <4 x i16> %T +} From stoklund at 2pi.dk Mon Jun 6 14:02:04 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 06 Jun 2011 21:02:04 -0000 Subject: [llvm-commits] [llvm] r132690 - in /llvm/trunk/lib/CodeGen: AllocationOrder.cpp AllocationOrder.h Message-ID: <20110606210204.395982A6C12C@llvm.org> Author: stoklund Date: Mon Jun 6 16:02:04 2011 New Revision: 132690 URL: http://llvm.org/viewvc/llvm-project?rev=132690&view=rev Log: Get allocation orders from RegisterClassInfo when possible. Only target-dependent hints require callbacks. The RCI allocation order has CSR aliases last according to their order of appearance in the getCalleeSavedRegs list. This can depend on the calling convention. This way, AllocationOrder::next doesn't have to check for reserved registers, and CSRs are always allocated last, even with weird calling conventions. Modified: llvm/trunk/lib/CodeGen/AllocationOrder.cpp llvm/trunk/lib/CodeGen/AllocationOrder.h Modified: llvm/trunk/lib/CodeGen/AllocationOrder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AllocationOrder.cpp?rev=132690&r1=132689&r2=132690&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AllocationOrder.cpp (original) +++ llvm/trunk/lib/CodeGen/AllocationOrder.cpp Mon Jun 6 16:02:04 2011 @@ -25,7 +25,7 @@ AllocationOrder::AllocationOrder(unsigned VirtReg, const VirtRegMap &VRM, const RegisterClassInfo &RegClassInfo) - : Pos(0), RCI(RegClassInfo) { + : Begin(0), End(0), Pos(0), RCI(RegClassInfo), OwnedBegin(false) { const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg); std::pair HintPair = VRM.getRegInfo().getRegAllocationHint(VirtReg); @@ -37,14 +37,37 @@ if (TargetRegisterInfo::isVirtualRegister(Hint)) Hint = VRM.getPhys(Hint); - // The remaining allocation order may depend on the hint. - tie(Begin, End) = VRM.getTargetRegInfo() - .getAllocationOrder(RC, HintPair.first, Hint, VRM.getMachineFunction()); - - // Target-dependent hints require resolution. - if (HintPair.first) - Hint = VRM.getTargetRegInfo().ResolveRegAllocHint(HintPair.first, Hint, - VRM.getMachineFunction()); + // The first hint pair component indicates a target-specific hint. + if (HintPair.first) { + const TargetRegisterInfo &TRI = VRM.getTargetRegInfo(); + // The remaining allocation order may depend on the hint. + const unsigned *B, *E; + tie(B, E) = TRI.getAllocationOrder(RC, HintPair.first, Hint, + VRM.getMachineFunction()); + + // Empty allocation order? + if (B == E) + return; + + // Copy the allocation order with reserved registers removed. + OwnedBegin = true; + unsigned *P = new unsigned[E - B]; + Begin = P; + for (; B != E; ++B) + if (!RCI.isReserved(*B)) + *P++ = *B; + End = P; + + // Target-dependent hints require resolution. + Hint = TRI.ResolveRegAllocHint(HintPair.first, Hint, + VRM.getMachineFunction()); + } else { + // If there is no hint or just a normal hint, use the cached allocation + // order from RegisterClassInfo. + ArrayRef O = RCI.getOrder(RC); + Begin = O.begin(); + End = O.end(); + } // The hint must be a valid physreg for allocation. if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) || @@ -52,18 +75,7 @@ Hint = 0; } -unsigned AllocationOrder::next() { - // First take the hint. - if (!Pos) { - Pos = Begin; - if (Hint) - return Hint; - } - // Then look at the order from TRI. - while(Pos != End) { - unsigned Reg = *Pos++; - if (Reg != Hint && !RCI.isReserved(Reg)) - return Reg; - } - return 0; +AllocationOrder::~AllocationOrder() { + if (OwnedBegin) + delete [] Begin; } Modified: llvm/trunk/lib/CodeGen/AllocationOrder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AllocationOrder.h?rev=132690&r1=132689&r2=132690&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AllocationOrder.h (original) +++ llvm/trunk/lib/CodeGen/AllocationOrder.h Mon Jun 6 16:02:04 2011 @@ -28,6 +28,7 @@ const unsigned *Pos; const RegisterClassInfo &RCI; unsigned Hint; + bool OwnedBegin; public: /// AllocationOrder - Create a new AllocationOrder for VirtReg. @@ -39,10 +40,26 @@ const VirtRegMap &VRM, const RegisterClassInfo &RegClassInfo); + ~AllocationOrder(); + /// next - Return the next physical register in the allocation order, or 0. /// It is safe to call next again after it returned 0. /// It will keep returning 0 until rewind() is called. - unsigned next(); + unsigned next() { + // First take the hint. + if (!Pos) { + Pos = Begin; + if (Hint) + return Hint; + } + // Then look at the order from TRI. + while (Pos != End) { + unsigned Reg = *Pos++; + if (Reg != Hint) + return Reg; + } + return 0; + } /// rewind - Start over from the beginning. void rewind() { Pos = 0; } From eli.friedman at gmail.com Mon Jun 6 15:13:27 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 06 Jun 2011 22:13:27 -0000 Subject: [llvm-commits] [llvm] r132693 - /llvm/trunk/tools/opt/opt.cpp Message-ID: <20110606221327.929222A6C12C@llvm.org> Author: efriedma Date: Mon Jun 6 17:13:27 2011 New Revision: 132693 URL: http://llvm.org/viewvc/llvm-project?rev=132693&view=rev Log: We only do always-inlining at -O1; make opt reflect that. Modified: llvm/trunk/tools/opt/opt.cpp Modified: llvm/trunk/tools/opt/opt.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/opt/opt.cpp?rev=132693&r1=132692&r2=132693&view=diff ============================================================================== --- llvm/trunk/tools/opt/opt.cpp (original) +++ llvm/trunk/tools/opt/opt.cpp Mon Jun 6 17:13:27 2011 @@ -412,7 +412,7 @@ if (DisableInline) { // No inlining pass - } else if (OptLevel) { + } else if (OptLevel > 1) { unsigned Threshold = 225; if (OptLevel > 2) Threshold = 275; From eli.friedman at gmail.com Mon Jun 6 15:29:28 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 6 Jun 2011 15:29:28 -0700 Subject: [llvm-commits] [llvm] r132686 - in /llvm/trunk/test/Transforms/PhaseOrdering: basic.ll dg.exp In-Reply-To: <20110606202301.0125B2A6C12C@llvm.org> References: <20110606202301.0125B2A6C12C@llvm.org> Message-ID: On Mon, Jun 6, 2011 at 1:23 PM, Nick Lewycky wrote: > Author: nicholas > Date: Mon Jun  6 15:23:00 2011 > New Revision: 132686 > > URL: http://llvm.org/viewvc/llvm-project?rev=132686&view=rev > Log: > This directory was missing the dg.exp to cause the tests to run. Some time since > it was added, the test has regressed, so XFAIL it. I think the failure is expected given r132631. -Eli > Added: >    llvm/trunk/test/Transforms/PhaseOrdering/dg.exp > Modified: >    llvm/trunk/test/Transforms/PhaseOrdering/basic.ll > > Modified: llvm/trunk/test/Transforms/PhaseOrdering/basic.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/PhaseOrdering/basic.ll?rev=132686&r1=132685&r2=132686&view=diff > ============================================================================== > --- llvm/trunk/test/Transforms/PhaseOrdering/basic.ll (original) > +++ llvm/trunk/test/Transforms/PhaseOrdering/basic.ll Mon Jun  6 15:23:00 2011 > @@ -1,4 +1,5 @@ >  ; RUN: opt -O3 -S %s | FileCheck %s > +; XFAIL: * > >  target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" >  target triple = "x86_64-apple-macosx10.6.7" > > Added: llvm/trunk/test/Transforms/PhaseOrdering/dg.exp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/PhaseOrdering/dg.exp?rev=132686&view=auto > ============================================================================== > --- llvm/trunk/test/Transforms/PhaseOrdering/dg.exp (added) > +++ llvm/trunk/test/Transforms/PhaseOrdering/dg.exp Mon Jun  6 15:23:00 2011 > @@ -0,0 +1,3 @@ > +load_lib llvm.exp > + > +RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]] > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From eli.friedman at gmail.com Mon Jun 6 15:45:46 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 06 Jun 2011 22:45:46 -0000 Subject: [llvm-commits] [llvm] r132695 - /llvm/trunk/tools/bugpoint/bugpoint.cpp Message-ID: <20110606224546.C2A312A6C12C@llvm.org> Author: efriedma Date: Mon Jun 6 17:45:46 2011 New Revision: 132695 URL: http://llvm.org/viewvc/llvm-project?rev=132695&view=rev Log: Add -O1/2/3 to bugpoint, so when you conclude opt -O2 reproduces an issue, you can just run bugpoint -O2. :) My implementation isn't precisely equivalent to what opt does, but as far as I can tell, it's close enough. Modified: llvm/trunk/tools/bugpoint/bugpoint.cpp Modified: llvm/trunk/tools/bugpoint/bugpoint.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/bugpoint.cpp?rev=132695&r1=132694&r2=132695&view=diff ============================================================================== --- llvm/trunk/tools/bugpoint/bugpoint.cpp (original) +++ llvm/trunk/tools/bugpoint/bugpoint.cpp Mon Jun 6 17:45:46 2011 @@ -69,6 +69,18 @@ StandardLinkOpts("std-link-opts", cl::desc("Include the standard link time optimizations")); +static cl::opt +OptLevelO1("O1", + cl::desc("Optimization level 1. Similar to llvm-gcc -O1")); + +static cl::opt +OptLevelO2("O2", + cl::desc("Optimization level 2. Similar to llvm-gcc -O2")); + +static cl::opt +OptLevelO3("O3", + cl::desc("Optimization level 3. Similar to llvm-gcc -O3")); + static cl::opt OverrideTriple("mtriple", cl::desc("Override target triple for module")); @@ -83,10 +95,10 @@ // Hack to capture a pass list. namespace { - class AddToDriver : public PassManager { + class AddToDriver : public FunctionPassManager { BugDriver &D; public: - AddToDriver(BugDriver &_D) : D(_D) {} + AddToDriver(BugDriver &_D) : FunctionPassManager(0), D(_D) {} virtual void add(Pass *P) { const void *ID = P->getPassID(); @@ -158,6 +170,20 @@ /*RunInliner=*/true); } + if (OptLevelO1 || OptLevelO2 || OptLevelO3) { + PassManagerBuilder Builder; + if (OptLevelO1) + Builder.Inliner = createAlwaysInlinerPass(); + else if (OptLevelO2) + Builder.Inliner = createFunctionInliningPass(225); + else + Builder.Inliner = createFunctionInliningPass(275); + + // Note that although clang/llvm-gcc use two separate passmanagers + // here, it shouldn't normally make a difference. + Builder.populateFunctionPassManager(PM); + Builder.populateModulePassManager(PM); + } for (std::vector::iterator I = PassList.begin(), E = PassList.end(); From stuart at apple.com Mon Jun 6 16:15:58 2011 From: stuart at apple.com (Stuart Hastings) Date: Mon, 06 Jun 2011 23:15:58 -0000 Subject: [llvm-commits] [llvm] r132696 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h test/CodeGen/X86/2011-06-03-x87chain.ll Message-ID: <20110606231558.AA18C2A6C12C@llvm.org> Author: stuart Date: Mon Jun 6 18:15:58 2011 New Revision: 132696 URL: http://llvm.org/viewvc/llvm-project?rev=132696&view=rev Log: Followup to 132458, omit unnecessary stack copy when x87 input is a load. rdar://problem/6373334 Added: llvm/trunk/test/CodeGen/X86/2011-06-03-x87chain.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=132696&r1=132695&r2=132696&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jun 6 18:15:58 2011 @@ -1097,6 +1097,7 @@ setTargetDAGCombine(ISD::SUB); setTargetDAGCombine(ISD::STORE); setTargetDAGCombine(ISD::ZERO_EXTEND); + setTargetDAGCombine(ISD::SINT_TO_FP); if (Subtarget->is64Bit()) setTargetDAGCombine(ISD::MUL); @@ -6700,11 +6701,6 @@ DebugLoc dl = Op.getDebugLoc(); unsigned Size = SrcVT.getSizeInBits()/8; MachineFunction &MF = DAG.getMachineFunction(); - - SDValue Addr = Op.getOperand(0); - if (Addr.getOpcode() == ISD::LOAD) - return BuildFILD(Op, SrcVT, DAG.getEntryNode(), Addr, DAG); - int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), @@ -12169,6 +12165,26 @@ return SDValue(); } +static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, const X86TargetLowering *XTLI) { + DebugLoc dl = N->getDebugLoc(); + SDValue Op0 = N->getOperand(0); + // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have + // a 32-bit target where SSE doesn't support i64->FP operations. + if (Op0.getOpcode() == ISD::LOAD) { + LoadSDNode *Ld = cast(Op0.getNode()); + EVT VT = Ld->getValueType(0); + if (!Ld->isVolatile() && !N->getValueType(0).isVector() && + ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() && + !XTLI->getSubtarget()->is64Bit() && + !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { + SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0), Ld->getChain(), Op0, DAG); + DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1)); + return FILDChain; + } + } + return SDValue(); +} + // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, X86TargetLowering::DAGCombinerInfo &DCI) { @@ -12253,6 +12269,7 @@ case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); + case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this); case X86ISD::FXOR: case X86ISD::FOR: return PerformFORCombine(N, DAG); case X86ISD::FAND: return PerformFANDCombine(N, DAG); Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=132696&r1=132695&r2=132696&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Mon Jun 6 18:15:58 2011 @@ -689,6 +689,9 @@ /// appropriate. virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const; + SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, + SelectionDAG &DAG) const; + protected: std::pair findRepresentativeClass(EVT VT) const; @@ -780,8 +783,6 @@ SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const; SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const; - SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, - SelectionDAG &DAG) const; SDValue LowerBITCAST(SDValue op, SelectionDAG &DAG) const; SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; Added: llvm/trunk/test/CodeGen/X86/2011-06-03-x87chain.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-06-03-x87chain.ll?rev=132696&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2011-06-03-x87chain.ll (added) +++ llvm/trunk/test/CodeGen/X86/2011-06-03-x87chain.ll Mon Jun 6 18:15:58 2011 @@ -0,0 +1,31 @@ +; RUN: llc < %s -march=x86 | FileCheck %s + +define float @chainfail1(i64* nocapture %a, i64* nocapture %b, i32 %x, i32 %y, float* nocapture %f) nounwind uwtable noinline ssp { +entry: + %tmp1 = load i64* %a, align 8 +; Insure x87 ops are properly chained, order preserved. +; CHECK: fildll + %conv = sitofp i64 %tmp1 to float +; CHECK: fstps + store float %conv, float* %f, align 4 +; CHECK: idivl + %div = sdiv i32 %x, %y + %conv5 = sext i32 %div to i64 + store i64 %conv5, i64* %b, align 8 + ret float %conv +} + +define float @chainfail2(i64* nocapture %a, i64* nocapture %b, i32 %x, i32 %y, float* nocapture %f) nounwind uwtable noinline ssp { +entry: +; CHECK: movl $0, + store i64 0, i64* %b, align 8 + %mul = mul nsw i32 %y, %x + %sub = add nsw i32 %mul, -1 + %idxprom = sext i32 %sub to i64 + %arrayidx = getelementptr inbounds i64* %a, i64 %idxprom + %tmp4 = load i64* %arrayidx, align 8 +; CHECK: fildll + %conv = sitofp i64 %tmp4 to float + store float %conv, float* %f, align 4 + ret float %conv +} From stoklund at 2pi.dk Mon Jun 6 16:55:20 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 06 Jun 2011 23:55:20 -0000 Subject: [llvm-commits] [llvm] r132697 - in /llvm/trunk: lib/CodeGen/RegAllocGreedy.cpp test/CodeGen/X86/sse_reload_fold.ll Message-ID: <20110606235520.7143C2A6C12C@llvm.org> Author: stoklund Date: Mon Jun 6 18:55:20 2011 New Revision: 132697 URL: http://llvm.org/viewvc/llvm-project?rev=132697&view=rev Log: Simplify local live range splitting's safeguard to fix PR10070. When local live range splitting creates a live range with the same number of instructions as the old range, mark it as RS_Local. When such a range is seen again, require that it be split in a way that reduces the number of instructions. That guarantees we are making progress while still being able to perform 3 -> 2+3 splits as required by PR10070. This also means that the PrevSlot map is no longer needed. This was also used to estimate new spill weights, but that is no longer necessary after slotIndexes::insertMachineInstrInMaps() got the extra Late insertion argument. Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp llvm/trunk/test/CodeGen/X86/sse_reload_fold.ll Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=132697&r1=132696&r2=132697&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Mon Jun 6 18:55:20 2011 @@ -154,10 +154,6 @@ /// class. SmallVector GlobalCand; - /// For every instruction in SA->UseSlots, store the previous non-copy - /// instruction. - SmallVector PrevSlot; - public: RAGreedy(); @@ -194,9 +190,6 @@ void splitAroundRegion(LiveInterval&, GlobalSplitCandidate&, SmallVectorImpl&); void calcGapWeights(unsigned, SmallVectorImpl&); - SlotIndex getPrevMappedIndex(const MachineInstr*); - void calcPrevSlots(); - unsigned nextSplitPoint(unsigned); CanEvict canEvict(LiveInterval &A, LiveInterval &B); bool canEvictInterference(LiveInterval&, unsigned, float&); @@ -1137,47 +1130,6 @@ } } -/// getPrevMappedIndex - Return the slot index of the last non-copy instruction -/// before MI that has a slot index. If MI is the first mapped instruction in -/// its block, return the block start index instead. -/// -SlotIndex RAGreedy::getPrevMappedIndex(const MachineInstr *MI) { - assert(MI && "Missing MachineInstr"); - const MachineBasicBlock *MBB = MI->getParent(); - MachineBasicBlock::const_iterator B = MBB->begin(), I = MI; - while (I != B) - if (!(--I)->isDebugValue() && !I->isCopy()) - return Indexes->getInstructionIndex(I); - return Indexes->getMBBStartIdx(MBB); -} - -/// calcPrevSlots - Fill in the PrevSlot array with the index of the previous -/// real non-copy instruction for each instruction in SA->UseSlots. -/// -void RAGreedy::calcPrevSlots() { - const SmallVectorImpl &Uses = SA->UseSlots; - PrevSlot.clear(); - PrevSlot.reserve(Uses.size()); - for (unsigned i = 0, e = Uses.size(); i != e; ++i) { - const MachineInstr *MI = Indexes->getInstructionFromIndex(Uses[i]); - PrevSlot.push_back(getPrevMappedIndex(MI).getDefIndex()); - } -} - -/// nextSplitPoint - Find the next index into SA->UseSlots > i such that it may -/// be beneficial to split before UseSlots[i]. -/// -/// 0 is always a valid split point -unsigned RAGreedy::nextSplitPoint(unsigned i) { - const SmallVectorImpl &Uses = SA->UseSlots; - const unsigned Size = Uses.size(); - assert(i != Size && "No split points after the end"); - // Allow split before i when Uses[i] is not adjacent to the previous use. - while (++i != Size && PrevSlot[i].getBaseIndex() <= Uses[i-1].getBaseIndex()) - ; - return i; -} - /// tryLocalSplit - Try to split VirtReg into smaller intervals inside its only /// basic block. /// @@ -1205,11 +1157,27 @@ dbgs() << '\n'; }); - // For every use, find the previous mapped non-copy instruction. - // We use this to detect valid split points, and to estimate new interval - // sizes. - calcPrevSlots(); + // Since we allow local split results to be split again, there is a risk of + // creating infinite loops. It is tempting to require that the new live + // ranges have less instructions than the original. That would guarantee + // convergence, but it is too strict. A live range with 3 instructions can be + // split 2+3 (including the COPY), and we want to allow that. + // + // Instead we use these rules: + // + // 1. Allow any split for ranges with getStage() < RS_Local. (Except for the + // noop split, of course). + // 2. Require progress be made for ranges with getStage() >= RS_Local. All + // the new ranges must have fewer instructions than before the split. + // 3. New ranges with the same number of instructions are marked RS_Local, + // smaller ranges are marked RS_New. + // + // These rules allow a 3 -> 2+3 split once, which we need. They also prevent + // excessive splitting and infinite loops. + // + bool ProgressRequired = getStage(VirtReg) >= RS_Local; + // Best split candidate. unsigned BestBefore = NumGaps; unsigned BestAfter = 0; float BestDiff = 0; @@ -1227,13 +1195,11 @@ // The new spill weight must be larger than any gap interference. // We will split before Uses[SplitBefore] and after Uses[SplitAfter]. - unsigned SplitBefore = 0, SplitAfter = nextSplitPoint(1) - 1; + unsigned SplitBefore = 0, SplitAfter = 1; // MaxGap should always be max(GapWeight[SplitBefore..SplitAfter-1]). // It is the spill weight that needs to be evicted. float MaxGap = GapWeight[0]; - for (unsigned i = 1; i != SplitAfter; ++i) - MaxGap = std::max(MaxGap, GapWeight[i]); for (;;) { // Live before/after split? @@ -1251,32 +1217,22 @@ } // Should the interval be extended or shrunk? bool Shrink = true; - if (MaxGap < HUGE_VALF) { - // Estimate the new spill weight. - // - // Each instruction reads and writes the register, except the first - // instr doesn't read when !FirstLive, and the last instr doesn't write - // when !LastLive. - // - // We will be inserting copies before and after, so the total number of - // reads and writes is 2 * EstUses. - // - const unsigned EstUses = 2*(SplitAfter - SplitBefore) + - 2*(LiveBefore + LiveAfter); - // Try to guess the size of the new interval. This should be trivial, - // but the slot index of an inserted copy can be a lot smaller than the - // instruction it is inserted before if there are many dead indexes - // between them. - // - // We measure the distance from the instruction before SplitBefore to - // get a conservative estimate. - // - // The final distance can still be different if inserting copies - // triggers a slot index renumbering. + // How many gaps would the new range have? + unsigned NewGaps = LiveBefore + SplitAfter - SplitBefore + LiveAfter; + + // Legally, without causing looping? + bool Legal = !ProgressRequired || NewGaps < NumGaps; + + if (Legal && MaxGap < HUGE_VALF) { + // Estimate the new spill weight. Each instruction reads or writes the + // register. Conservatively assume there are no read-modify-write + // instructions. // - const float EstWeight = normalizeSpillWeight(blockFreq * EstUses, - PrevSlot[SplitBefore].distance(Uses[SplitAfter])); + // Try to guess the size of the new interval. + const float EstWeight = normalizeSpillWeight(blockFreq * (NewGaps + 1), + Uses[SplitBefore].distance(Uses[SplitAfter]) + + (LiveBefore + LiveAfter)*SlotIndex::InstrDist); // Would this split be possible to allocate? // Never allocate all gaps, we wouldn't be making progress. DEBUG(dbgs() << " w=" << EstWeight); @@ -1294,8 +1250,7 @@ // Try to shrink. if (Shrink) { - SplitBefore = nextSplitPoint(SplitBefore); - if (SplitBefore < SplitAfter) { + if (++SplitBefore < SplitAfter) { DEBUG(dbgs() << " shrink\n"); // Recompute the max when necessary. if (GapWeight[SplitBefore - 1] >= MaxGap) { @@ -1315,10 +1270,7 @@ } DEBUG(dbgs() << " extend\n"); - for (unsigned e = nextSplitPoint(SplitAfter + 1) - 1; - SplitAfter != e; ++SplitAfter) - MaxGap = std::max(MaxGap, GapWeight[SplitAfter]); - continue; + MaxGap = std::max(MaxGap, GapWeight[SplitAfter++]); } } @@ -1337,9 +1289,27 @@ SlotIndex SegStart = SE->enterIntvBefore(Uses[BestBefore]); SlotIndex SegStop = SE->leaveIntvAfter(Uses[BestAfter]); SE->useIntv(SegStart, SegStop); - SE->finish(); + SmallVector IntvMap; + SE->finish(&IntvMap); DebugVars->splitRegister(VirtReg.reg, LREdit.regs()); - setStage(NewVRegs.begin(), NewVRegs.end(), RS_Local); + + // If the new range has the same number of instructions as before, mark it as + // RS_Local so the next split will be forced to make progress. Otherwise, + // leave the new intervals as RS_New so they can compete. + bool LiveBefore = BestBefore != 0 || BI.LiveIn; + bool LiveAfter = BestAfter != NumGaps || BI.LiveOut; + unsigned NewGaps = LiveBefore + BestAfter - BestBefore + LiveAfter; + if (NewGaps >= NumGaps) { + DEBUG(dbgs() << "Tagging non-progress ranges: "); + assert(!ProgressRequired && "Didn't make progress when it was required."); + LRStage.resize(MRI->getNumVirtRegs()); + for (unsigned i = 0, e = IntvMap.size(); i != e; ++i) + if (IntvMap[i] == 1) { + LRStage[LREdit.get(i)->reg] = RS_Local; + DEBUG(dbgs() << PrintReg(LREdit.get(i)->reg)); + } + DEBUG(dbgs() << '\n'); + } ++NumLocalSplits; return 0; Modified: llvm/trunk/test/CodeGen/X86/sse_reload_fold.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse_reload_fold.ll?rev=132697&r1=132696&r2=132697&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/sse_reload_fold.ll (original) +++ llvm/trunk/test/CodeGen/X86/sse_reload_fold.ll Mon Jun 6 18:55:20 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-linux -mattr=+64bit,+sse3 -print-failed-fuse-candidates |& FileCheck %s +; RUN: llc < %s -mtriple=x86_64-linux -mattr=+64bit,+sse3 -print-failed-fuse-candidates -regalloc=basic |& FileCheck %s ; CHECK: fail ; CHECK-NOT: fail @@ -117,7 +117,16 @@ ret <2 x double> %t } -; This one should fail to fuse. +; This one should fail to fuse, but -regalloc=greedy isn't even trying. Instead +; it produces: +; callq test_vd +; movapd (%rsp), %xmm1 # 16-byte Reload +; hsubpd %xmm0, %xmm1 +; movapd %xmm1, %xmm0 +; addq $24, %rsp +; ret +; RABasic still tries to fold this one. + define <2 x double> @z0(<2 x double> %f) { %y = call <2 x double> @test_vd(<2 x double> %f) %t = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %f, <2 x double> %y) From aggarwa4 at illinois.edu Mon Jun 6 17:08:40 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Tue, 07 Jun 2011 00:08:40 -0000 Subject: [llvm-commits] [poolalloc] r132698 - /poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Message-ID: <20110607000840.62FE22A6C12C@llvm.org> Author: aggarwa4 Date: Mon Jun 6 19:08:40 2011 New Revision: 132698 URL: http://llvm.org/viewvc/llvm-project?rev=132698&view=rev Log: 1. Add a few asserts. 2. __ctype_b_loc and related functions in LLVM seem to use int** instead of short **. Fixes 197.parser errors. 3. Also, array returned by __ctype_b_loc can be accessed with index -128 to 255. Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c?rev=132698&r1=132697&r2=132698&view=diff ============================================================================== --- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c (original) +++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Mon Jun 6 19:08:40 2011 @@ -36,9 +36,15 @@ fflush(stderr); assert(0 && "MAP_FAILED"); } + assert(res < SIZE && "wrong mapped address"); return res; } +void trackStringInput(void *ptr, uint32_t tag) { + trackInitInst(ptr, strlen(ptr) + 1, tag); +} + + /** * Initialize the shadow memory which records the 1:1 mapping of addresses to types. */ @@ -138,6 +144,7 @@ void trackLoadInst(void *ptr, uint8_t typeNumber, uint64_t size, uint32_t tag) { uint8_t i = 1; uintptr_t p = maskAddress(ptr); + assert(p + size < SIZE); /* Check if this an initialized but untyped memory.*/ if (typeNumber != shadow_begin[p]) { @@ -164,10 +171,10 @@ break; } } - #if DEBUG printf("Load: %p, %p = actual: %u, expect: %u | %lu bytes %d \n", ptr, (void *)p, typeNumber, shadow_begin[p], size, tag); #endif + } /** @@ -209,8 +216,11 @@ * Initialize metadata for the pointer returned by __ctype_b_loc */ void trackctype(void *ptr, uint32_t tag) { - trackInitInst(ptr, sizeof(short*), tag); - trackInitInst(*(short**)ptr, sizeof(short)*384, tag); + char *p, p1; + trackInitInst(ptr, sizeof(int*), tag); + p = *(int**)ptr; + p1 = p + (-128 * sizeof(int)); + trackInitInst(p1, sizeof(int)*384, tag); } /** From atrick at apple.com Mon Jun 6 17:08:49 2011 From: atrick at apple.com (Andrew Trick) Date: Tue, 07 Jun 2011 00:08:49 -0000 Subject: [llvm-commits] [llvm] r132699 - in /llvm/trunk/lib/Target/ARM: ARMInstrInfo.td ARMInstrThumb.td ARMInstrThumb2.td Message-ID: <20110607000849.94B202A6C12C@llvm.org> Author: atrick Date: Mon Jun 6 19:08:49 2011 New Revision: 132699 URL: http://llvm.org/viewvc/llvm-project?rev=132699&view=rev Log: Fix for setjmp/longjmp exception handling on ARM. setjmp clobbers CPSR. rdar://problem/9556069 Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=132699&r1=132698&r2=132699&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Jun 6 19:08:49 2011 @@ -3772,7 +3772,7 @@ // These are pseudo-instructions and are lowered to individual MC-insts, so // no encoding information is necessary. let Defs = - [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, + [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], hasSideEffects = 1, isBarrier = 1 in { def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), NoItinerary, @@ -3781,7 +3781,7 @@ } let Defs = - [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ], + [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], hasSideEffects = 1, isBarrier = 1 in { def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), NoItinerary, Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=132699&r1=132698&r2=132699&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Mon Jun 6 19:08:49 2011 @@ -1460,7 +1460,7 @@ // Defs. By doing so, we also cause the prologue/epilogue code to actively // preserve all of the callee-saved resgisters, which is exactly what we want. // $val is a scratch register for our use. -let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12 ], +let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ], hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val), AddrModeNone, SizeSpecial, NoItinerary, "","", Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=132699&r1=132698&r2=132699&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Jun 6 19:08:49 2011 @@ -2969,7 +2969,7 @@ // all of the callee-saved resgisters, which is exactly what we want. // $val is a scratch register for our use. let Defs = - [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, + [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in { def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val), @@ -2979,7 +2979,7 @@ } let Defs = - [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ], + [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in { def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val), AddrModeNone, SizeSpecial, NoItinerary, "", "", From atrick at apple.com Mon Jun 6 17:38:12 2011 From: atrick at apple.com (Andrew Trick) Date: Tue, 07 Jun 2011 00:38:12 -0000 Subject: [llvm-commits] [llvm] r132701 - /llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Message-ID: <20110607003813.04B372A6C12C@llvm.org> Author: atrick Date: Mon Jun 6 19:38:12 2011 New Revision: 132701 URL: http://llvm.org/viewvc/llvm-project?rev=132701&view=rev Log: Fix a merge bug in preRAsched for handling physreg aliases. I've been sitting on this long enough trying to find a test case. I think the fix should go in now, but I'll keep working on the test case. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=132701&r1=132700&r2=132701&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Mon Jun 6 19:38:12 2011 @@ -1008,14 +1008,16 @@ for (const unsigned *AliasI = TRI->getOverlaps(Reg); *AliasI; ++AliasI) { // Check if Ref is live. - if (!LiveRegDefs[Reg]) continue; + if (!LiveRegDefs[*AliasI]) continue; // Allow multiple uses of the same def. - if (LiveRegDefs[Reg] == SU) continue; + if (LiveRegDefs[*AliasI] == SU) continue; // Add Reg to the set of interfering live regs. - if (RegAdded.insert(Reg)) - LRegs.push_back(Reg); + if (RegAdded.insert(*AliasI)) { + assert(*AliasI == Reg && "alias clobber"); //!!! + LRegs.push_back(*AliasI); + } } } From aggarwa4 at illinois.edu Mon Jun 6 18:00:20 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Tue, 07 Jun 2011 01:00:20 -0000 Subject: [llvm-commits] [poolalloc] r132702 - in /poolalloc/trunk: include/assistDS/TypeChecks.h lib/AssistDS/TypeChecks.cpp runtime/DynamicTypeChecks/TypeRuntime.c Message-ID: <20110607010020.F25F32A6C12C@llvm.org> Author: aggarwa4 Date: Mon Jun 6 20:00:20 2011 New Revision: 132702 URL: http://llvm.org/viewvc/llvm-project?rev=132702&view=rev Log: 1. Remove DSA support. Add that as a later optimizing pass. 2. Different ctype functions are different. Handle separately. Modified: poolalloc/trunk/include/assistDS/TypeChecks.h poolalloc/trunk/lib/AssistDS/TypeChecks.cpp poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Modified: poolalloc/trunk/include/assistDS/TypeChecks.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/TypeChecks.h?rev=132702&r1=132701&r2=132702&view=diff ============================================================================== --- poolalloc/trunk/include/assistDS/TypeChecks.h (original) +++ poolalloc/trunk/include/assistDS/TypeChecks.h Mon Jun 6 20:00:20 2011 @@ -55,7 +55,6 @@ virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); - AU.addRequired >(); AU.addRequired(); AU.addRequired(); } Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=132702&r1=132701&r2=132702&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Mon Jun 6 20:00:20 2011 @@ -40,10 +40,6 @@ STATISTIC(numTypes, "Number of Types used in the module"); namespace { - static cl::opt EnableTypeSafeOpt("enable-type-safe-opt", - cl::desc("Use DSA pass"), - cl::Hidden, - cl::init(false)); static cl::opt DisablePointerTypeChecks("disable-ptr-type-checks", cl::desc("DONT Distinguish pointer types"), cl::Hidden, @@ -67,8 +63,7 @@ static Constant *RegisterArgv; static Constant *compareTypeAndNumber; -unsigned int -TypeChecks::getTypeMarker(const Type * Ty) { +unsigned int TypeChecks::getTypeMarker(const Type * Ty) { if(DisablePointerTypeChecks) { if(Ty->isPointerTy()) { Ty = VoidPtrTy; @@ -80,8 +75,7 @@ return UsedTypes[Ty]; } -unsigned int -TypeChecks::getTypeMarker(Value *V) { +unsigned int TypeChecks::getTypeMarker(Value *V) { return getTypeMarker(V->getType()); } @@ -91,9 +85,8 @@ TD = &getAnalysis(); TA = &getAnalysis(); addrAnalysis = &getAnalysis(); - if(EnableTypeSafeOpt) - TS = &getAnalysis >(); + // Create the necessary prototypes VoidTy = IntegerType::getVoidTy(M.getContext()); Int8Ty = IntegerType::getInt8Ty(M.getContext()); Int32Ty = IntegerType::getInt32Ty(M.getContext()); @@ -172,6 +165,7 @@ ByValFunctions.clear(); AddressTakenFunctions.clear(); + // Only works for whole program analysis Function *MainF = M.getFunction("main"); if (MainF == 0 || MainF->isDeclaration()) { assert(0 && "No main function found"); @@ -181,9 +175,10 @@ // Insert the shadow initialization function. modified |= initShadow(M); - // record argv + // Record argv modified |= visitMain(M, *MainF); + // Recognize special cases for (Module::iterator MI = M.begin(), ME = M.end(); MI != ME; ++MI) { Function &F = *MI; if(F.isDeclaration()) @@ -191,6 +186,7 @@ std::string name = F.getName(); if (strncmp(name.c_str(), "tc.", 3) == 0) continue; + if (strncmp(name.c_str(), "main", 4) == 0) continue; // Iterate and find all byval functions bool hasByValArg = false; @@ -233,7 +229,7 @@ } } - // modify all byval functions + // Modify all byval functions while(!ByValFunctions.empty()) { Function *F = ByValFunctions.back(); ByValFunctions.pop_back(); @@ -310,6 +306,7 @@ Instruction *I = *II++; modified |= visitIndirectCallSite(M,I); } + FI = IndFunctionsMap.begin(), FE = IndFunctionsMap.end(); for(;FI!=FE;++FI) { Function *F = FI->first; @@ -324,6 +321,15 @@ toReplace.pop_back(); if(Constant *C = dyn_cast(user)) { if(!isa(C)) { + bool changeUse = true; + for(Value::use_iterator II = user->use_begin(); + II != user->use_end(); II++) { + if(CallInst *CI = dyn_cast(II)) + if(CI->getCalledFunction()->isDeclaration()) + changeUse = false; + } + if(!changeUse) + continue; std::vector ReplaceWorklist; for (User::op_iterator use = user->op_begin(); use != user->op_end(); @@ -664,7 +670,6 @@ F.getParent()->getFunctionList().push_back(F_clone); F.replaceAllUsesWith(F_clone); return visitInternalVarArgFunction(M, *F_clone); - return true; } // each vararg function is modified so that the first @@ -924,11 +929,6 @@ for (Function::arg_iterator I = F.arg_begin(); I != F.arg_end(); ++I) { if (!I->hasByValAttr()) continue; - if(EnableTypeSafeOpt) { - if(TS->isTypeSafe(cast(I), &F)) { - continue; - } - } assert(I->getType()->isPointerTy()); const Type *ETy = (cast(I->getType()))->getElementType(); AllocaInst *AI = new AllocaInst(ETy, "", InsertBefore); @@ -945,6 +945,9 @@ //FIXME ui->dump(); } + if(!isa(ui)) { + ui->dump(); + } // Check that F is the called value if(CallInst *CI = dyn_cast(ui++)) { if(CI->getCalledFunction() == &F) { @@ -965,13 +968,6 @@ Args.push_back(CI->getOperand(j)); // If there are attributes on this argument, copy them to the correct // position in the AttributesVec - if(EnableTypeSafeOpt) { - if(TS->isTypeSafe(II, CI->getParent()->getParent())) { - if (Attributes Attrs = CallPAL.getParamAttributes(j)) - AttributesVec.push_back(AttributeWithIndex::get(j, Attrs)); - continue; - } - } //FIXME: copy the rest of the attributes. if(II->hasByValAttr()) continue; @@ -1006,11 +1002,6 @@ for (Function::arg_iterator I = F.arg_begin(); I != F.arg_end(); ++I) { if (!I->hasByValAttr()) continue; - if(EnableTypeSafeOpt) { - if(TS->isTypeSafe(cast(I), &F)) { - continue; - } - } I->removeAttr(llvm::Attribute::ByVal); } return true; @@ -1203,12 +1194,6 @@ bool TypeChecks::visitGlobal(Module &M, GlobalVariable &GV, Constant *C, Instruction &I, unsigned offset) { - if(EnableTypeSafeOpt) { - if(TS->isTypeSafe(&GV)) { - return false; - } - } - if(ConstantArray *CA = dyn_cast(C)) { const Type * ElementType = CA->getType()->getElementType(); unsigned int t = TD->getTypeStoreSize(ElementType); @@ -1327,12 +1312,6 @@ CallInst *CI_Init = CallInst::Create(memsetF, Args2.begin(), Args2.end()); CI_Init->insertAfter(Size); - if(EnableTypeSafeOpt) { - if(TS->isTypeSafe(&AI, AI.getParent()->getParent())) { - return true; - } - } - // Setting metadata to be 0(BOTTOM/Uninitialized) std::vector Args; @@ -1360,7 +1339,6 @@ // Value *Callee = CS.getCalledValue()->stripPointerCasts(); Instruction *I = CS.getInstruction(); - Function *Caller = I->getParent()->getParent(); // Special case handling of certain libc allocation functions here. if (Function *F = dyn_cast(Callee)) { @@ -1369,11 +1347,6 @@ case Intrinsic::memcpy: case Intrinsic::memmove: { - if(EnableTypeSafeOpt) { - if(TS->isTypeSafe(I->getOperand(2), Caller)) { - return false; - } - } CastInst *BCI_Src = BitCastInst::CreatePointerCast(I->getOperand(2), VoidPtrTy, "", I); CastInst *BCI_Dest = BitCastInst::CreatePointerCast(I->getOperand(1), VoidPtrTy, "", I); std::vector Args; @@ -1387,11 +1360,6 @@ } case Intrinsic::memset: - if(EnableTypeSafeOpt) { - if(TS->isTypeSafe(I->getOperand(1), Caller)) { - return false; - } - } CastInst *BCI = BitCastInst::CreatePointerCast(I->getOperand(1), VoidPtrTy, "", I); std::vector Args; Args.push_back(BCI); @@ -1416,7 +1384,7 @@ std::vectorArgs; Args.push_back(BCI); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - Constant *F = M.getOrInsertFunction("trackctype", VoidTy, VoidPtrTy, Int32Ty, NULL); + Constant *F = M.getOrInsertFunction("trackctype_32", VoidTy, VoidPtrTy, Int32Ty, NULL); CallInst *CI = CallInst::Create(F, Args.begin(), Args.end()); CI->insertAfter(BCI); } else if (F->getNameStr() == std::string("__ctype_tolower_loc")) { @@ -1425,7 +1393,7 @@ std::vectorArgs; Args.push_back(BCI); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - Constant *F = M.getOrInsertFunction("trackctype", VoidTy, VoidPtrTy, Int32Ty, NULL); + Constant *F = M.getOrInsertFunction("trackctype_32", VoidTy, VoidPtrTy, Int32Ty, NULL); CallInst *CI = CallInst::Create(F, Args.begin(), Args.end()); CI->insertAfter(BCI); } else if (F->getNameStr() == std::string("strcpy")) { @@ -1444,11 +1412,6 @@ Constant *F = M.getOrInsertFunction("trackStrncpyInst", VoidTy, VoidPtrTy, VoidPtrTy, I->getOperand(3)->getType(), Int32Ty, NULL); CallInst::Create(F, Args.begin(), Args.end(), "", I); } else if(F->getNameStr() == std::string("ftime")) { - if(EnableTypeSafeOpt) { - if(TS->isTypeSafe(I->getOperand(1), Caller)) { - return false; - } - } CastInst *BCI = BitCastInst::CreatePointerCast(I->getOperand(1), VoidPtrTy, "", I); const PointerType *PTy = cast(I->getOperand(1)->getType()); const Type * ElementType = PTy->getElementType(); @@ -1460,11 +1423,6 @@ CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", I); return true; } else if(F->getNameStr() == std::string("read")) { - if(EnableTypeSafeOpt) { - if(TS->isTypeSafe(I->getOperand(2), Caller)) { - return false; - } - } CastInst *BCI = BitCastInst::CreatePointerCast(I->getOperand(2), VoidPtrTy); BCI->insertAfter(I); std::vector Args; @@ -1477,11 +1435,6 @@ CI->insertAfter(BCI); return true; } else if(F->getNameStr() == std::string("fread")) { - if(EnableTypeSafeOpt) { - if(TS->isTypeSafe(I->getOperand(1), Caller)) { - return false; - } - } CastInst *BCI = BitCastInst::CreatePointerCast(I->getOperand(1), VoidPtrTy); BCI->insertAfter(I); std::vector Args; @@ -1494,11 +1447,6 @@ CI->insertAfter(BCI); return true; } else if(F->getNameStr() == std::string("calloc")) { - if(EnableTypeSafeOpt) { - if(TS->isTypeSafe(I, Caller)) { - return false; - } - } CastInst *BCI = BitCastInst::CreatePointerCast(I, VoidPtrTy); BCI->insertAfter(I); std::vector Args; @@ -1518,11 +1466,6 @@ CI_Arr->insertAfter(CI); return true; } else if(F->getNameStr() == std::string("realloc")) { - if(EnableTypeSafeOpt) { - if(TS->isTypeSafe(I, Caller)) { - return false; - } - } CastInst *BCI_Src = BitCastInst::CreatePointerCast(I->getOperand(1), VoidPtrTy); CastInst *BCI_Dest = BitCastInst::CreatePointerCast(I, VoidPtrTy); BCI_Src->insertAfter(I); @@ -1537,11 +1480,6 @@ CI->insertAfter(BCI_Dest); return true; } else if(F->getNameStr() == std::string("fgets")) { - if(EnableTypeSafeOpt) { - if(TS->isTypeSafe(I->getOperand(1), Caller)) { - return true; - } - } CastInst *BCI = BitCastInst::CreatePointerCast(I->getOperand(1), VoidPtrTy, "", I); std::vector Args; Args.push_back(BCI); @@ -1693,11 +1631,6 @@ // Insert runtime checks before all load instructions. bool TypeChecks::visitLoadInst(Module &M, LoadInst &LI) { - if(EnableTypeSafeOpt) { - if(TS->isTypeSafe(LI.getOperand(0), LI.getParent()->getParent())) { - return false; - } - } // Cast the pointer operand to i8* for the runtime function. CastInst *BCI = BitCastInst::CreatePointerCast(LI.getPointerOperand(), VoidPtrTy, "", &LI); @@ -1715,11 +1648,6 @@ // Insert runtime checks before all store instructions. bool TypeChecks::visitStoreInst(Module &M, StoreInst &SI) { - if(EnableTypeSafeOpt) { - if(TS->isTypeSafe(SI.getOperand(1), SI.getParent()->getParent())) { - return false; - } - } // Cast the pointer operand to i8* for the runtime function. CastInst *BCI = BitCastInst::CreatePointerCast(SI.getPointerOperand(), VoidPtrTy, "", &SI); @@ -1739,26 +1667,10 @@ // Insert runtime checks before copying store instructions. bool TypeChecks::visitCopyingStoreInst(Module &M, StoreInst &SI, Value *SS) { - if(EnableTypeSafeOpt) { - if(TS->isTypeSafe(SI.getOperand(1), SI.getParent()->getParent())) { - return false; - } - } // Cast the pointer operand to i8* for the runtime function. CastInst *BCI_Dest = BitCastInst::CreatePointerCast(SI.getPointerOperand(), VoidPtrTy, "", &SI); CastInst *BCI_Src = BitCastInst::CreatePointerCast(SS, VoidPtrTy, "", &SI); - if(EnableTypeSafeOpt) { - LoadInst *LI = cast(SI.getOperand(0)); - if(TS->isTypeSafe(LI->getPointerOperand(), SI.getParent()->getParent())) { - std::vector Args; - Args.push_back(BCI_Src); - Args.push_back(ConstantInt::get(Int64Ty, TD->getTypeStoreSize(SI.getOperand(0)->getType()))); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", &SI); - } - } - std::vector Args; Args.push_back(BCI_Dest); Args.push_back(BCI_Src); Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c?rev=132702&r1=132701&r2=132702&view=diff ============================================================================== --- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c (original) +++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Mon Jun 6 20:00:20 2011 @@ -216,10 +216,20 @@ * Initialize metadata for the pointer returned by __ctype_b_loc */ void trackctype(void *ptr, uint32_t tag) { - char *p, p1; + short *p, *p1, *p2; + trackInitInst(ptr, sizeof(short*), tag); + p = *(short**)ptr; + p1 = p -128; + p2 = p1 + 384; + trackInitInst(p1, sizeof(short)*384, tag); +} + +void trackctype_32(void *ptr, uint32_t tag) { + int *p, *p1, *p2; trackInitInst(ptr, sizeof(int*), tag); p = *(int**)ptr; - p1 = p + (-128 * sizeof(int)); + p1 = p -128 ; + p2 = p1 + 384; trackInitInst(p1, sizeof(int)*384, tag); } From bob.wilson at apple.com Mon Jun 6 18:09:21 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 06 Jun 2011 18:09:21 -0700 Subject: [llvm-commits] [patch] Change how clang produces computed gotos In-Reply-To: <4DED1514.3010000@mozilla.com> References: <4DED1514.3010000@mozilla.com> Message-ID: <5800A678-28DD-49F0-85A1-68F1D0709C64@apple.com> The early tail dup pass is supposed to handle this, but it's not very smart and I know it can fail in some cases. I spent some time trying to improve it but never got the code finished to the point where I could commit it. I still hope to go back to that sometime. I'd be curious to know more about why it's failing. On Jun 6, 2011, at 10:57 AM, Rafael Avila de Espindola wrote: > I tried compiling firefox with both clang and Apple's gcc. The performance was close. Running it on shark showed that the difference was that the clang compiled one was using 2x as much time in the js interpreter. > > There seems to be a register allocator problem that I hope to report shortly, but another problem is the way the computed gotos are produced. > > Currently clang produces a branch to a common bb that has the only inderctbr in the function. This is normally optimized away, but the optimizers are not kicking in jsinterp.o and it has a single 'jmp *%rax' in the generated binary. > > The main reason for the status quo I think is a gradual evolution from the days there was no indirectbr in llvm. Producing n indirectbr instructions does increase the size of the cfg, but I think the results are worth it: > > jsinterp.o goes from 1876288 to 1684448 bytes. The dromaeo score of firefox goes from 1628.59runs/s to 1674.68runs/s. For comparison, gcc is 1667.49runs/s. It is the first time I get firefox to go faster when compiled with clang :-) > > Build time on files that use computed goto does suffer. jsinterp.o with -O3 -g goes from 63s to 140s. Gives that this is one of the two files in all of mozilla that use it, and that it is really performance critical, I think it is worth it. > > A question about indirectbr: I has a list of every label it could branch to. It doesn't look like we optimize it and that we avoid inlining functions that use computed goto. Wouldn't it be better to make the list implicit: every label in this function that has its address taken? > > Cheers, > Rafael > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From ahatanak at gmail.com Mon Jun 6 19:17:21 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Tue, 07 Jun 2011 02:17:21 -0000 Subject: [llvm-commits] [llvm] r132703 - in /llvm/trunk: lib/Target/Mips/MipsFrameLowering.cpp test/CodeGen/Mips/eh.ll Message-ID: <20110607021721.6A8142A6C12C@llvm.org> Author: ahatanak Date: Mon Jun 6 21:17:21 2011 New Revision: 132703 URL: http://llvm.org/viewvc/llvm-project?rev=132703&view=rev Log: Add test case for C++ exception handling and fix the following mistakes in MipsFrameLowering::emitPrologue: - cfi directives are not inserted at the right location or in the right order. - The source MachineLocation for the cfi directive that changes the cfa register to $fp should be MachineLocation::VirtualFP. - A PROLOG_LABEL that marks the beginning of cfi_offset directives for callee-saved register is emitted even when no callee-saved registers are saved. - When a callee-saved double precision register is saved, two cfi_offset directives, one for each of the paired single precision registers, should be emitted. Added: llvm/trunk/test/CodeGen/Mips/eh.ll Modified: llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp?rev=132703&r1=132702&r2=132703&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp Mon Jun 6 21:17:21 2011 @@ -173,6 +173,10 @@ // No need to allocate space on the stack. if (StackSize == 0 && !MFI->adjustsStack()) return; + MachineModuleInfo &MMI = MF.getMMI(); + std::vector &Moves = MMI.getFrameMoves(); + MachineLocation DstML, SrcML; + // Adjust stack : addi sp, sp, (-imm) ATUsed = expandRegLargeImmPair(Mips::SP, -StackSize, NewReg, NewImm, MBB, MBBI); @@ -183,49 +187,75 @@ if (ATUsed) BuildMI(MBB, MBBI, dl, TII.get(Mips::ATMACRO)); + // emit ".cfi_def_cfa_offset StackSize" + MCSymbol *AdjustSPLabel = MMI.getContext().CreateTempSymbol(); + BuildMI(MBB, MBBI, dl, + TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel); + DstML = MachineLocation(MachineLocation::VirtualFP); + SrcML = MachineLocation(MachineLocation::VirtualFP, -StackSize); + Moves.push_back(MachineMove(AdjustSPLabel, DstML, SrcML)); + // Find the instruction past the last instruction that saves a callee-saved // register to the stack. const std::vector &CSI = MFI->getCalleeSavedInfo(); - - for (unsigned i = 0; i < CSI.size(); ++i) - ++MBBI; + + if (CSI.size()) { + for (unsigned i = 0; i < CSI.size(); ++i) + ++MBBI; + + // Iterate over list of callee-saved registers and emit .cfi_offset directives. + MCSymbol *CSLabel = MMI.getContext().CreateTempSymbol(); + BuildMI(MBB, MBBI, dl, + TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel); + for (std::vector::const_iterator I = CSI.begin(), + E = CSI.end(); I != E; ++I) { + int64_t Offset = MFI->getObjectOffset(I->getFrameIdx()); + unsigned Reg = I->getReg(); + + // If Reg is a double precision register, emit two cfa_offsets, + // one for each of the paired single precision registers. + if (Mips::AFGR64RegisterClass->contains(Reg)) { + const unsigned *SubRegs = RegInfo->getSubRegisters(Reg); + MachineLocation DstML0(MachineLocation::VirtualFP, Offset); + MachineLocation DstML1(MachineLocation::VirtualFP, Offset + 4); + MachineLocation SrcML0(*SubRegs); + MachineLocation SrcML1(*(SubRegs + 1)); + + if (!STI.isLittle()) + std::swap(SrcML0, SrcML1); + + Moves.push_back(MachineMove(CSLabel, DstML0, SrcML0)); + Moves.push_back(MachineMove(CSLabel, DstML1, SrcML1)); + } + else { + // Reg is either in CPURegs or FGR32. + DstML = MachineLocation(MachineLocation::VirtualFP, Offset); + SrcML = MachineLocation(Reg); + Moves.push_back(MachineMove(CSLabel, DstML, SrcML)); + } + } + } + // if framepointer enabled, set it to point to the stack pointer. - if (hasFP(MF)) + if (hasFP(MF)) { // Insert instruction "move $fp, $sp" at this location. BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::FP) .addReg(Mips::SP).addReg(Mips::ZERO); + // emit ".cfi_def_cfa_register $fp" + MCSymbol *SetFPLabel = MMI.getContext().CreateTempSymbol(); + BuildMI(MBB, MBBI, dl, + TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel); + DstML = MachineLocation(Mips::FP); + SrcML = MachineLocation(MachineLocation::VirtualFP); + Moves.push_back(MachineMove(SetFPLabel, DstML, SrcML)); + } + // Restore GP from the saved stack location if (MipsFI->needGPSaveRestore()) BuildMI(MBB, MBBI, dl, TII.get(Mips::CPRESTORE)) .addImm(MFI->getObjectOffset(MipsFI->getGPFI())); - - // EH Frame infomation. - MachineModuleInfo &MMI = MF.getMMI(); - std::vector &Moves = MMI.getFrameMoves(); - MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol(); - BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::PROLOG_LABEL)).addSym(FrameLabel); - - if (hasFP(MF)) { - MachineLocation SPDst(Mips::FP); - MachineLocation SPSrc(Mips::SP); - Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc)); - } - - if (StackSize) { - MachineLocation SPDst(MachineLocation::VirtualFP); - MachineLocation SPSrc(MachineLocation::VirtualFP, -StackSize); - Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc)); - } - - for (std::vector::const_iterator I = CSI.begin(), - E = CSI.end(); I != E; ++I) { - int64_t Offset = MFI->getObjectOffset(I->getFrameIdx()); - MachineLocation CSDst(MachineLocation::VirtualFP, Offset); - MachineLocation CSSrc(I->getReg()); - Moves.push_back(MachineMove(FrameLabel, CSDst, CSSrc)); - } } void MipsFrameLowering::emitEpilogue(MachineFunction &MF, Added: llvm/trunk/test/CodeGen/Mips/eh.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/eh.ll?rev=132703&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Mips/eh.ll (added) +++ llvm/trunk/test/CodeGen/Mips/eh.ll Mon Jun 6 21:17:21 2011 @@ -0,0 +1,78 @@ +; RUN: llc < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-EL +; RUN: llc < %s -march=mips -mcpu=4ke | FileCheck %s -check-prefix=CHECK-EB + + at g1 = global double 0.000000e+00, align 8 + at _ZTId = external constant i8* + +define void @_Z1fd(double %i2) { +entry: +; CHECK-EL: addiu $sp, $sp +; CHECK-EL: .cfi_def_cfa_offset +; CHECK-EL: sdc1 $f20 +; CHECK-EL: sw $ra +; CHECK-EL: sw $17 +; CHECK-EL: sw $16 +; CHECK-EL: .cfi_offset 52, -8 +; CHECK-EL: .cfi_offset 53, -4 +; CHECK-EB: .cfi_offset 53, -8 +; CHECK-EB: .cfi_offset 52, -4 +; CHECK-EL: .cfi_offset 31, -12 +; CHECK-EL: .cfi_offset 17, -16 +; CHECK-EL: .cfi_offset 16, -20 +; CHECK-EL: .cprestore + + %exception = tail call i8* @__cxa_allocate_exception(i32 8) nounwind + %0 = bitcast i8* %exception to double* + store double 3.200000e+00, double* %0, align 8, !tbaa !0 + invoke void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTId to i8*), i8* null) noreturn + to label %unreachable unwind label %lpad + +lpad: ; preds = %entry +; CHECK-EL: # %lpad +; CHECK-EL: lw $gp +; CHECK-EL: beq $5 + + %exn = tail call i8* @llvm.eh.exception() nounwind + %eh.selector = tail call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exn, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i8* bitcast (i8** @_ZTId to i8*)) nounwind + %1 = tail call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTId to i8*)) nounwind + %2 = icmp eq i32 %eh.selector, %1 + br i1 %2, label %catch, label %eh.resume + +catch: ; preds = %lpad + %3 = tail call i8* @__cxa_begin_catch(i8* %exn) nounwind + %4 = bitcast i8* %3 to double* + %exn.scalar = load double* %4, align 8 + %add = fadd double %exn.scalar, %i2 + store double %add, double* @g1, align 8, !tbaa !0 + tail call void @__cxa_end_catch() nounwind + ret void + +eh.resume: ; preds = %lpad + tail call void @llvm.eh.resume(i8* %exn, i32 %eh.selector) noreturn + unreachable + +unreachable: ; preds = %entry + unreachable +} + +declare i8* @__cxa_allocate_exception(i32) + +declare i8* @llvm.eh.exception() nounwind readonly + +declare i32 @__gxx_personality_v0(...) + +declare i32 @llvm.eh.selector(i8*, i8*, ...) nounwind + +declare i32 @llvm.eh.typeid.for(i8*) nounwind + +declare void @llvm.eh.resume(i8*, i32) + +declare void @__cxa_throw(i8*, i8*, i8*) + +declare i8* @__cxa_begin_catch(i8*) + +declare void @__cxa_end_catch() + +!0 = metadata !{metadata !"double", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA", null} From aggarwa4 at illinois.edu Mon Jun 6 19:57:37 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Tue, 07 Jun 2011 02:57:37 -0000 Subject: [llvm-commits] [poolalloc] r132705 - /poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Message-ID: <20110607025737.39EDC2A6C12C@llvm.org> Author: aggarwa4 Date: Mon Jun 6 21:57:37 2011 New Revision: 132705 URL: http://llvm.org/viewvc/llvm-project?rev=132705&view=rev Log: Remove some unused variables. Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c?rev=132705&r1=132704&r2=132705&view=diff ============================================================================== --- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c (original) +++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Mon Jun 6 21:57:37 2011 @@ -216,20 +216,18 @@ * Initialize metadata for the pointer returned by __ctype_b_loc */ void trackctype(void *ptr, uint32_t tag) { - short *p, *p1, *p2; + short *p, *p1; trackInitInst(ptr, sizeof(short*), tag); p = *(short**)ptr; p1 = p -128; - p2 = p1 + 384; trackInitInst(p1, sizeof(short)*384, tag); } void trackctype_32(void *ptr, uint32_t tag) { - int *p, *p1, *p2; + int *p, *p1; trackInitInst(ptr, sizeof(int*), tag); p = *(int**)ptr; p1 = p -128 ; - p2 = p1 + 384; trackInitInst(p1, sizeof(int)*384, tag); } From rafael.espindola at gmail.com Mon Jun 6 22:03:19 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Tue, 07 Jun 2011 01:03:19 -0400 Subject: [llvm-commits] [patch] Change how clang produces computed gotos In-Reply-To: <5800A678-28DD-49F0-85A1-68F1D0709C64@apple.com> References: <4DED1514.3010000@mozilla.com> <5800A678-28DD-49F0-85A1-68F1D0709C64@apple.com> Message-ID: <4DEDB117.9090109@gmail.com> On 2011-06-06 21:09, Bob Wilson wrote: > The early tail dup pass is supposed to handle this, but it's not very > smart and I know it can fail in some cases. I spent some time trying > to improve it but never got the code finished to the point where I > could commit it. I still hope to go back to that sometime. I'd be > curious to know more about why it's failing. I am still not sure exactly what the problem is, but I think I found something interesting. By the time we get to tail duplication, the indirectgoto bb looks like BB#4193: derived from LLVM BB %indirectgoto Predecessors according to CFG: ..... %vreg5207 = PHI .... %vreg5208 = PHI .... %vreg5209 = PHI .... %vreg5210 = PHI .... %vreg5211 = PHI .... %vreg5212 = PHI .... %vreg5213 = PHI .... %vreg5214 = PHI .... %vreg5215 = PHI .... %vreg5216 = PHI ... %vreg5292 = MOV64ri64i32 4; GR64:%vreg5292 %vreg5291 = MOV32ri -1; GR32:%vreg5291 %vreg5290 = MOV32r0 %EFLAGS; GR32:%vreg5290 %vreg5289 = MOV64ri32 -2; GR64:%vreg5289 %vreg5288 = MOV64ri64i32 2; GR64:%vreg5288 JMP64m %vreg5216, 1, %noreg, 0, %noreg; mem:LD8[%indirect.goto.dest.in] GR64:%vreg5216 Successors according to CFG: .... Some statistics from the register allocator unpatched clang: 53934 regalloc - Number of copies inserted for splitting patched clang: indirect: 7636 regalloc - Number of copies inserted for splitting So it looks like what the patch really does is help the register allocator. Another interesting ones unpatched clang -disable-early-taildup: 1105 regalloc - Number of copies inserted for splitting patched clang -disable-early-taildup: 6714 regalloc - Number of copies inserted for splitting >From the above my guess is that the register allocator is getting really confused by the extra live ranges introduced. Tail dup in particular seems to do it in a way that is worse than the regular out of ssa pass. Is there any cleanup pass that we currently only run before tail dup but should try to run after it too? Cheers, Rafael From nadav.rotem at intel.com Mon Jun 6 22:23:58 2011 From: nadav.rotem at intel.com (Nadav Rotem) Date: Tue, 07 Jun 2011 05:23:58 -0000 Subject: [llvm-commits] [llvm] r132706 - in /llvm/trunk/test/CodeGen: Generic/basic-promote-integers.ll X86/basic-promote-integers.ll Message-ID: <20110607052359.086282A6C12C@llvm.org> Author: nadav Date: Tue Jun 7 00:23:58 2011 New Revision: 132706 URL: http://llvm.org/viewvc/llvm-project?rev=132706&view=rev Log: Move the legalizer tests to the X86 directory because the test uses the x86 codegen. Thanks Galina. Added: llvm/trunk/test/CodeGen/X86/basic-promote-integers.ll - copied, changed from r132689, llvm/trunk/test/CodeGen/Generic/basic-promote-integers.ll Removed: llvm/trunk/test/CodeGen/Generic/basic-promote-integers.ll Removed: llvm/trunk/test/CodeGen/Generic/basic-promote-integers.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/basic-promote-integers.ll?rev=132705&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Generic/basic-promote-integers.ll (original) +++ llvm/trunk/test/CodeGen/Generic/basic-promote-integers.ll (removed) @@ -1,91 +0,0 @@ -; Test that vectors are scalarized/lowered correctly -; (with both legalization methods). -; RUN: llc -march=x86 -promote-elements < %s -; RUN: llc -march=x86 < %s - -; A simple test to check copyToParts and copyFromParts. - -define <4 x i64> @test_param_0(<4 x i64> %A, <2 x i32> %B, <4 x i8> %C) { - ret <4 x i64> %A -} - -define <2 x i32> @test_param_1(<4 x i64> %A, <2 x i32> %B, <4 x i8> %C) { - ret <2 x i32> %B -} - -define <4 x i8> @test_param_2(<4 x i64> %A, <2 x i32> %B, <4 x i8> %C) { - ret <4 x i8> %C -} - -; Simple tests to check arithmetic and vector operations on types which need to -; be legalized (no loads/stores to/from memory here). - -define <4 x i64> @test_arith_0(<4 x i64> %A, <2 x i32> %B, <4 x i8> %C) { - %K = add <4 x i64> %A, - ret <4 x i64> %K -} - -define <2 x i32> @test_arith_1(<4 x i64> %A, <2 x i32> %B, <4 x i8> %C) { - %K = add <2 x i32> %B, - ret <2 x i32> %K -} - -define <4 x i8> @test_arith_2(<4 x i64> %A, <2 x i32> %B, <4 x i8> %C) { - %K = add <4 x i8> %C, - ret <4 x i8> %K -} - -define i8 @test_arith_3(<4 x i64> %A, <2 x i32> %B, <4 x i8> %C) { - %K = add <4 x i8> %C, - %Y = extractelement <4 x i8> %K, i32 1 - ret i8 %Y -} - -define <4 x i8> @test_arith_4(<4 x i64> %A, <2 x i32> %B, <4 x i8> %C) { - %Y = insertelement <4 x i8> %C, i8 1, i32 0 - ret <4 x i8> %Y -} - -define <4 x i32> @test_arith_5(<4 x i64> %A, <2 x i32> %B, <4 x i32> %C) { - %Y = insertelement <4 x i32> %C, i32 1, i32 0 - ret <4 x i32> %Y -} - -define <4 x i32> @test_arith_6(<4 x i64> %A, <2 x i32> %B, <4 x i32> %C) { - %F = extractelement <2 x i32> %B, i32 1 - %Y = insertelement <4 x i32> %C, i32 %F, i32 0 - ret <4 x i32> %Y -} - -define <4 x i64> @test_arith_7(<4 x i64> %A, <2 x i32> %B, <4 x i32> %C) { - %F = extractelement <2 x i32> %B, i32 1 - %W = zext i32 %F to i64 - %Y = insertelement <4 x i64> %A, i64 %W, i32 0 - ret <4 x i64> %Y -} - -define i64 @test_arith_8(<4 x i64> %A, <2 x i32> %B, <4 x i32> %C) { - %F = extractelement <2 x i32> %B, i32 1 - %W = zext i32 %F to i64 - %T = add i64 %W , 11 - ret i64 %T -} - -define <4 x i64> @test_arith_9(<4 x i64> %A, <2 x i32> %B, <4 x i16> %C) { - %T = add <4 x i16> %C, %C - %F0 = extractelement <4 x i16> %T, i32 0 - %F1 = extractelement <4 x i16> %T, i32 1 - %W0 = zext i16 %F0 to i64 - %W1 = zext i16 %F1 to i64 - %Y0 = insertelement <4 x i64> %A, i64 %W0, i32 0 - %Y1 = insertelement <4 x i64> %Y0, i64 %W1, i32 2 - ret <4 x i64> %Y1 -} - - -define <4 x i16> @test_arith_10(<4 x i64> %A, <2 x i32> %B, <4 x i32> %C) { - %F = bitcast <2 x i32> %B to <4 x i16> - %T = add <4 x i16> %F , - ret <4 x i16> %T -} - Copied: llvm/trunk/test/CodeGen/X86/basic-promote-integers.ll (from r132689, llvm/trunk/test/CodeGen/Generic/basic-promote-integers.ll) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/basic-promote-integers.ll?p2=llvm/trunk/test/CodeGen/X86/basic-promote-integers.ll&p1=llvm/trunk/test/CodeGen/Generic/basic-promote-integers.ll&r1=132689&r2=132706&rev=132706&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Generic/basic-promote-integers.ll (original) +++ llvm/trunk/test/CodeGen/X86/basic-promote-integers.ll Tue Jun 7 00:23:58 2011 @@ -82,10 +82,17 @@ ret <4 x i64> %Y1 } - define <4 x i16> @test_arith_10(<4 x i64> %A, <2 x i32> %B, <4 x i32> %C) { %F = bitcast <2 x i32> %B to <4 x i16> %T = add <4 x i16> %F , ret <4 x i16> %T } + +; Simple tests to check saving/loading from memory +define <4 x i16> @test_mem_0(<4 x i64> %A, <2 x i32> %B, <4 x i32> %C) { + %F = bitcast <2 x i32> %B to <4 x i16> + %T = add <4 x i16> %F , + ret <4 x i16> %T +} + From lhames at gmail.com Mon Jun 6 23:05:58 2011 From: lhames at gmail.com (Lang Hames) Date: Tue, 07 Jun 2011 06:05:58 -0000 Subject: [llvm-commits] [llvm] r132707 - /llvm/trunk/include/llvm/CodeGen/RegAllocPBQP.h Message-ID: <20110607060558.3F0CA2A6C12C@llvm.org> Author: lhames Date: Tue Jun 7 01:05:58 2011 New Revision: 132707 URL: http://llvm.org/viewvc/llvm-project?rev=132707&view=rev Log: Switched to DenseMap for allowed sets in PBQP. Reduces total LLC time by 15% on CINT2006 for x86-32. Modified: llvm/trunk/include/llvm/CodeGen/RegAllocPBQP.h Modified: llvm/trunk/include/llvm/CodeGen/RegAllocPBQP.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegAllocPBQP.h?rev=132707&r1=132706&r2=132707&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/RegAllocPBQP.h (original) +++ llvm/trunk/include/llvm/CodeGen/RegAllocPBQP.h Tue Jun 7 01:05:58 2011 @@ -94,7 +94,7 @@ typedef std::map Node2VReg; typedef DenseMap VReg2Node; - typedef std::map AllowedSetMap; + typedef DenseMap AllowedSetMap; PBQP::Graph graph; Node2VReg node2VReg; From baldrick at free.fr Mon Jun 6 23:44:40 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 07 Jun 2011 06:44:40 -0000 Subject: [llvm-commits] [dragonegg] r132709 - in /dragonegg/trunk/src/x86: Target.cpp x86_builtins Message-ID: <20110607064440.6A55E2A6C12C@llvm.org> Author: baldrick Date: Tue Jun 7 01:44:40 2011 New Revision: 132709 URL: http://llvm.org/viewvc/llvm-project?rev=132709&view=rev Log: Implement rsqrtps_nr (rsqrtps with a Newton-Raphson step). Modified: dragonegg/trunk/src/x86/Target.cpp dragonegg/trunk/src/x86/x86_builtins Modified: dragonegg/trunk/src/x86/Target.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/x86/Target.cpp?rev=132709&r1=132708&r2=132709&view=diff ============================================================================== --- dragonegg/trunk/src/x86/Target.cpp (original) +++ dragonegg/trunk/src/x86/Target.cpp Tue Jun 7 01:44:40 2011 @@ -776,6 +776,20 @@ SI->setAlignment(16); return true; } + case rsqrtps_nr: { + // rsqrtps with a Newton-Raphson step to improve accuracy: + // rsqrtps_nr(x) = rsqrtps(x) * -0.5 * (rsqrtps(x) * x * rsqrtps(x) - 3.0) + Function *rsqrtps = Intrinsic::getDeclaration(TheModule, + Intrinsic::x86_sse_rsqrt_ps); + Value *X = Ops[0]; // x + Value *R = Builder.CreateCall(rsqrtps, X); // rsqrtps(x) + Value *RHS = Builder.CreateFAdd(Builder.CreateFMul(Builder.CreateFMul(R, X), + R), + ConstantFP::get(X->getType(), -3.0)); + Value *LHS = Builder.CreateFMul(R, ConstantFP::get(X->getType(), -0.5)); + Result = Builder.CreateFMul(LHS, RHS); + return true; + } case sqrtps_nr: { // Turn this into sqrtps without a Newton-Raphson step - sqrtps is already // accurate enough. Modified: dragonegg/trunk/src/x86/x86_builtins URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/x86/x86_builtins?rev=132709&r1=132708&r2=132709&view=diff ============================================================================== --- dragonegg/trunk/src/x86/x86_builtins (original) +++ dragonegg/trunk/src/x86/x86_builtins Tue Jun 7 01:44:40 2011 @@ -515,7 +515,7 @@ //DEFINE_BUILTIN(rsqrtf), //DEFINE_BUILTIN(rsqrtps), //DEFINE_BUILTIN(rsqrtps256), -//DEFINE_BUILTIN(rsqrtps_nr), +DEFINE_BUILTIN(rsqrtps_nr), //DEFINE_BUILTIN(rsqrtps_nr256), //DEFINE_BUILTIN(rsqrtss), //DEFINE_BUILTIN(sfence), From pekka.jaaskelainen at tut.fi Mon Jun 6 07:19:58 2011 From: pekka.jaaskelainen at tut.fi (=?ISO-8859-15?Q?Pekka_J=E4=E4skel=E4inen?=) Date: Mon, 06 Jun 2011 17:19:58 +0300 Subject: [llvm-commits] [PATCH] enable printf() -> iprintf() optimization for TCE Message-ID: <4DECE20E.6010801@tut.fi> Hello, Attached trivial patch (applies both to 2.9 and trunk) enables printf() to iprintf() optimization for the TCE target which uses Newlib and benefits greatly from this optimization. BR, -- Pekka -------------- next part -------------- A non-text attachment was scrubbed... Name: llvm-2.9-printf-to-iprintf.diff Type: text/x-patch Size: 670 bytes Desc: not available URL: From nicholas at mxc.ca Tue Jun 7 02:46:27 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 07 Jun 2011 02:46:27 -0700 Subject: [llvm-commits] patch: folding (zext (and x, cst)) Message-ID: <4DEDF373.5000004@mxc.ca> I have an unfinished patch. I was looking to optimize: define i32 @test1(i8 %x) nounwind readnone { %A = and i8 %x, -32 %B = zext i8 %A to i32 ret i32 %B } which currently does a mov into %al, then the "and", then extends, into doing a single extending mov, then an "and" in 32-bits. The rule I decided upon is "(zext (and x, cst)) -> (and (anyext x), (zext cst))" in the DAG combiner. That wasn't so hard to implement, but I haven't been able to chase down all of the fallout. The primary problem is that any-extends are showing up in places that didn't expect them. I added another DAG combine to fold away an anyext in one transform with sbbl, but then got rather stuck. The patterns added in this commit: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20110502/120547.html isn't matching any more. The relevant portion of before: 0x90580f0: i32 = X86ISD::CMP 0x9057a90, 0x9057a08 0x9057f58: i32 = X86ISD::SETCC_CARRY 0x9057fe0, 0x90580f0 0x9058068: i32 = sub 0x9057a90, 0x9057f58 and after: 0x96ff548: i32 = X86ISD::CMP 0x96feee8, 0x96fee60 0x96ff4c0: i8 = X86ISD::SETCC_CARRY 0x96ff438, 0x96ff548 0x96fef70: i32 = sign_extend 0x96ff4c0 0x96ff080: i32 = sub 0x96feee8, 0x96fef70 I'm not sure why this isn't being folded away, because X86InstrCompiler.td has a pattern that matches anyext(X86setcc_c) and turns it into a single X86setcc_c of the extended type. Why isn't that firing here? I've attached my patch and the result of running 'llc -debug test/CodeGen/X86/add-of-carry.ll' with my patch in place. Nick -------------- next part -------------- A non-text attachment was scrubbed... Name: dagcombine.patch Type: text/x-patch Size: 3990 bytes Desc: not available URL: -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: after.txt URL: From baldrick at free.fr Tue Jun 7 07:16:28 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 07 Jun 2011 14:16:28 -0000 Subject: [llvm-commits] [dragonegg] r132710 - in /dragonegg/trunk/src/x86: Target.cpp x86_builtins Message-ID: <20110607141628.F31052A6C12C@llvm.org> Author: baldrick Date: Tue Jun 7 09:16:28 2011 New Revision: 132710 URL: http://llvm.org/viewvc/llvm-project?rev=132710&view=rev Log: Implement rsqrtf. Note that while this works fine for float and double operands, it fails miserably for long double. However the long double code is identical to gcc's, so this failure is OK :) Modified: dragonegg/trunk/src/x86/Target.cpp dragonegg/trunk/src/x86/x86_builtins Modified: dragonegg/trunk/src/x86/Target.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/x86/Target.cpp?rev=132710&r1=132709&r2=132710&view=diff ============================================================================== --- dragonegg/trunk/src/x86/Target.cpp (original) +++ dragonegg/trunk/src/x86/Target.cpp Tue Jun 7 09:16:28 2011 @@ -776,6 +776,33 @@ SI->setAlignment(16); return true; } + case rsqrtf: { + // rsqrtss with a Newton-Raphson step to improve accuracy: + // rsqrtf(x) = rsqrtss(x) * -0.5 * (rsqrtss(x) * x * rsqrtss(x) - 3.0) + Function *rsqrtss = Intrinsic::getDeclaration(TheModule, + Intrinsic::x86_sse_rsqrt_ss); + // As rsqrtss is declared as taking a <4 x float> operand, mulch the operand + // into a vector. + Value *X = Ops[0]; + const Type *FloatTy = Type::getFloatTy(Context); + Value *AsFloat = Builder.CreateFPTrunc(X, FloatTy); + const Type *V4SFTy = VectorType::get(FloatTy, 4); + Value *AsVec = Builder.CreateInsertElement(UndefValue::get(V4SFTy), AsFloat, + Builder.getInt32(0)); + // Take the reciprocal square root of the vector and mulch it back into a + // scalar of the original type. + AsVec = Builder.CreateCall(rsqrtss, AsVec); + Value *R = Builder.CreateExtractElement(AsVec, Builder.getInt32(0)); + R = Builder.CreateFPExt(R, X->getType()); // rsqrtss(x) + + // Perform the Newton-Raphson step. + Value *RHS = Builder.CreateFAdd(Builder.CreateFMul(Builder.CreateFMul(R, X), + R), + ConstantFP::get(X->getType(), -3.0)); + Value *LHS = Builder.CreateFMul(R, ConstantFP::get(X->getType(), -0.5)); + Result = Builder.CreateFMul(LHS, RHS); + return true; + } case rsqrtps_nr: { // rsqrtps with a Newton-Raphson step to improve accuracy: // rsqrtps_nr(x) = rsqrtps(x) * -0.5 * (rsqrtps(x) * x * rsqrtps(x) - 3.0) Modified: dragonegg/trunk/src/x86/x86_builtins URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/x86/x86_builtins?rev=132710&r1=132709&r2=132710&view=diff ============================================================================== --- dragonegg/trunk/src/x86/x86_builtins (original) +++ dragonegg/trunk/src/x86/x86_builtins Tue Jun 7 09:16:28 2011 @@ -512,7 +512,7 @@ //DEFINE_BUILTIN(roundps256), //DEFINE_BUILTIN(roundsd), //DEFINE_BUILTIN(roundss), -//DEFINE_BUILTIN(rsqrtf), +DEFINE_BUILTIN(rsqrtf), //DEFINE_BUILTIN(rsqrtps), //DEFINE_BUILTIN(rsqrtps256), DEFINE_BUILTIN(rsqrtps_nr), From eli.friedman at gmail.com Tue Jun 7 07:58:34 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 7 Jun 2011 07:58:34 -0700 Subject: [llvm-commits] patch: folding (zext (and x, cst)) In-Reply-To: <4DEDF373.5000004@mxc.ca> References: <4DEDF373.5000004@mxc.ca> Message-ID: On Tue, Jun 7, 2011 at 2:46 AM, Nick Lewycky wrote: > I have an unfinished patch. I was looking to optimize: > >  define i32 @test1(i8 %x) nounwind readnone { >    %A = and i8 %x, -32 >    %B = zext i8 %A to i32 >    ret i32 %B >  } > > which currently does a mov into %al, then the "and", then extends, into > doing a single extending mov, then an "and" in 32-bits. The rule I decided > upon is "(zext (and x, cst)) -> (and (anyext x), (zext cst))" in the DAG > combiner. Just a comment, without reading the patch: it would be much more conservative to fold (zext (and (load x), cst)) -> (and (zextload x), (zext cst)). The transform you're proposing is much less obviously beneficial. -Eli > That wasn't so hard to implement, but I haven't been able to chase down all > of the fallout. The primary problem is that any-extends are showing up in > places that didn't expect them. I added another DAG combine to fold away an > anyext in one transform with sbbl, but then got rather stuck. > > The patterns added in this commit: > http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20110502/120547.html > isn't matching any more. The relevant portion of before: > >        0x90580f0: i32 = X86ISD::CMP 0x9057a90, 0x9057a08 >      0x9057f58: i32 = X86ISD::SETCC_CARRY 0x9057fe0, 0x90580f0 >    0x9058068: i32 = sub 0x9057a90, 0x9057f58 > > and after: > >          0x96ff548: i32 = X86ISD::CMP 0x96feee8, 0x96fee60 >        0x96ff4c0: i8 = X86ISD::SETCC_CARRY 0x96ff438, 0x96ff548 >      0x96fef70: i32 = sign_extend 0x96ff4c0 >    0x96ff080: i32 = sub 0x96feee8, 0x96fef70 > > I'm not sure why this isn't being folded away, because X86InstrCompiler.td > has a pattern that matches anyext(X86setcc_c) and turns it into a single > X86setcc_c of the extended type. Why isn't that firing here? > > I've attached my patch and the result of running 'llc -debug > test/CodeGen/X86/add-of-carry.ll' with my patch in place. > > Nick > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > From stuart at apple.com Tue Jun 7 08:23:11 2011 From: stuart at apple.com (Stuart Hastings) Date: Tue, 07 Jun 2011 15:23:11 -0000 Subject: [llvm-commits] [llvm] r132711 - /llvm/trunk/test/CodeGen/X86/2011-06-03-x87chain.ll Message-ID: <20110607152311.94CEE2A6C12C@llvm.org> Author: stuart Date: Tue Jun 7 10:23:11 2011 New Revision: 132711 URL: http://llvm.org/viewvc/llvm-project?rev=132711&view=rev Log: Tweak this test for ARM-hosted 'bot. Modified: llvm/trunk/test/CodeGen/X86/2011-06-03-x87chain.ll Modified: llvm/trunk/test/CodeGen/X86/2011-06-03-x87chain.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-06-03-x87chain.ll?rev=132711&r1=132710&r2=132711&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2011-06-03-x87chain.ll (original) +++ llvm/trunk/test/CodeGen/X86/2011-06-03-x87chain.ll Tue Jun 7 10:23:11 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=+sse | FileCheck %s define float @chainfail1(i64* nocapture %a, i64* nocapture %b, i32 %x, i32 %y, float* nocapture %f) nounwind uwtable noinline ssp { entry: From stoklund at 2pi.dk Tue Jun 7 08:44:57 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 7 Jun 2011 08:44:57 -0700 Subject: [llvm-commits] patch: folding (zext (and x, cst)) In-Reply-To: References: <4DEDF373.5000004@mxc.ca> Message-ID: On Jun 7, 2011, at 7:58 AM, Eli Friedman wrote: > On Tue, Jun 7, 2011 at 2:46 AM, Nick Lewycky wrote: >> I have an unfinished patch. I was looking to optimize: >> >> define i32 @test1(i8 %x) nounwind readnone { >> %A = and i8 %x, -32 >> %B = zext i8 %A to i32 >> ret i32 %B >> } >> >> which currently does a mov into %al, then the "and", then extends, into >> doing a single extending mov, then an "and" in 32-bits. The rule I decided >> upon is "(zext (and x, cst)) -> (and (anyext x), (zext cst))" in the DAG >> combiner. > > Just a comment, without reading the patch: it would be much more > conservative to fold (zext (and (load x), cst)) -> (and (zextload x), > (zext cst)). The transform you're proposing is much less obviously > beneficial. Also make sure this does the right thing on x86 when the zext is i32 -> i64. The and implicitly zero-extends to 64 bit. /jakob From aggarwa4 at illinois.edu Tue Jun 7 09:06:33 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Tue, 07 Jun 2011 16:06:33 -0000 Subject: [llvm-commits] [poolalloc] r132712 - in /poolalloc/trunk: include/assistDS/TypeChecks.h lib/AssistDS/TypeChecks.cpp Message-ID: <20110607160633.19A822A6C12C@llvm.org> Author: aggarwa4 Date: Tue Jun 7 11:06:32 2011 New Revision: 132712 URL: http://llvm.org/viewvc/llvm-project?rev=132712&view=rev Log: Add some utility functions. Modified: poolalloc/trunk/include/assistDS/TypeChecks.h poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/include/assistDS/TypeChecks.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/TypeChecks.h?rev=132712&r1=132711&r2=132712&view=diff ============================================================================== --- poolalloc/trunk/include/assistDS/TypeChecks.h (original) +++ poolalloc/trunk/include/assistDS/TypeChecks.h Tue Jun 7 11:06:32 2011 @@ -82,8 +82,9 @@ bool visitInputFunctionValue(Module &M, Value *V, Instruction *CI); void visitVAListCall(Function *F); - unsigned int getTypeMarker(const llvm::Type*); + unsigned int getTypeMarker(const Type*); unsigned int getTypeMarker(Value*); + unsigned int getSize(const Type*); // Return the map containing all of the types used in the module. const std::map &getTypes() const { return UsedTypes; Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=132712&r1=132711&r2=132712&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Tue Jun 7 11:06:32 2011 @@ -79,6 +79,14 @@ return getTypeMarker(V->getType()); } +unsigned int TypeChecks::getSize(const Type *Ty) { + return TD->getTypeStoreSize(Ty); +} + +static Constant *getTagCounter() { + return ConstantInt::get(Int32Ty, tagCounter++); +} + bool TypeChecks::runOnModule(Module &M) { bool modified = false; // Flags whether we modified the module. @@ -554,7 +562,7 @@ Args.push_back(OldValue); Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(VI))); Args.push_back(VAMetaData); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(getTagCounter()); CallInst::Create(compareTypeAndNumber, Args.begin(), Args.end(), @@ -789,7 +797,7 @@ Args.push_back(OldValue); Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(VI))); Args.push_back(VAMetaData); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(getTagCounter()); CallInst::Create(compareTypeAndNumber, Args.begin(), Args.end(), @@ -1022,7 +1030,7 @@ std::vector Args; Args.push_back(BCI); Args.push_back(AllocSize); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(getTagCounter()); // Set the metadata for the byval argument to TOP/Initialized CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", InsertPt); registeredArguments.push_back(&*I); @@ -1053,7 +1061,7 @@ std::vector Args; Args.push_back(BCI); Args.push_back(AllocSize); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(getTagCounter()); CallInst::Create(trackUnInitInst, Args.begin(), Args.end(), "", Pt); } } @@ -1103,9 +1111,9 @@ CastInst *BCI = BitCastInst::CreatePointerCast(I, VoidPtrTy, "", InsertPt); std::vector Args; Args.push_back(BCI); - unsigned int size = TD->getTypeStoreSize(I->getType()->getElementType()); + unsigned int size = getSize(I->getType()->getElementType()); Args.push_back(ConstantInt::get(Int64Ty, size)); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(getTagCounter()); CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", InsertPt); continue; } @@ -1196,7 +1204,7 @@ if(ConstantArray *CA = dyn_cast(C)) { const Type * ElementType = CA->getType()->getElementType(); - unsigned int t = TD->getTypeStoreSize(ElementType); + unsigned int t = getSize(ElementType); // Create the type entry for the first element // using recursive creation till we get to the base types visitGlobal(M, GV, CA->getOperand(0), I, offset); @@ -1208,7 +1216,7 @@ Args.push_back(BCI); Args.push_back(ConstantInt::get(Int64Ty, t)); Args.push_back(ConstantInt::get(Int64Ty, CA->getNumOperands())); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(getTagCounter()); CallInst::Create(trackArray, Args.begin(), Args.end(), "", &I); } else if(ConstantStruct *CS = dyn_cast(C)) { @@ -1228,14 +1236,14 @@ const Type *Ty = CAZ->getType(); if(const ArrayType * ATy = dyn_cast(Ty)) { const Type * ElementType = ATy->getElementType(); - unsigned int t = TD->getTypeStoreSize(ElementType); + unsigned int size = getSize(ElementType); visitGlobal(M, GV, Constant::getNullValue(ElementType), I, offset); CastInst *BCI = BitCastInst::CreatePointerCast(&GV, VoidPtrTy, "", &I); std::vector Args; Args.push_back(BCI); - Args.push_back(ConstantInt::get(Int64Ty, t)); + Args.push_back(ConstantInt::get(Int64Ty, size)); Args.push_back(ConstantInt::get(Int64Ty, ATy->getNumElements())); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(getTagCounter()); CallInst::Create(trackArray, Args.begin(), Args.end(), "", &I); } else if(const StructType *STy = dyn_cast(Ty)) { const StructLayout *SL = TD->getStructLayout(STy); @@ -1256,8 +1264,8 @@ std::vector Args; Args.push_back(GEP); Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(CAZ))); - Args.push_back(ConstantInt::get(Int64Ty, TD->getTypeStoreSize(CAZ->getType()))); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(ConstantInt::get(Int64Ty, getSize(CAZ->getType()))); + Args.push_back(getTagCounter()); CallInst::Create(trackGlobal, Args.begin(), Args.end(), "", &I); } } @@ -1272,8 +1280,8 @@ std::vector Args; Args.push_back(GEP); Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(C))); - Args.push_back(ConstantInt::get(Int64Ty, TD->getTypeStoreSize(C->getType()))); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(ConstantInt::get(Int64Ty, getSize(C->getType()))); + Args.push_back(getTagCounter()); CallInst::Create(trackGlobal, Args.begin(), Args.end(), "", &I); } @@ -1317,7 +1325,7 @@ std::vector Args; Args.push_back(BCI); Args.push_back(Size); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(getTagCounter()); CallInst *CI = CallInst::Create(trackUnInitInst, Args.begin(), Args.end()); CI->insertAfter(CI_Init); return true; @@ -1354,7 +1362,7 @@ Args.push_back(BCI_Src); CastInst *Size = CastInst::CreateIntegerCast(I->getOperand(3), Int64Ty, false, "", I); Args.push_back(Size); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(getTagCounter()); CallInst::Create(copyTypeInfo, Args.begin(), Args.end(), "", I); return true; } @@ -1365,7 +1373,7 @@ Args.push_back(BCI); CastInst *Size = CastInst::CreateIntegerCast(I->getOperand(3), Int64Ty, false, "", I); Args.push_back(Size); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(getTagCounter()); CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", I); return true; } @@ -1374,7 +1382,7 @@ BCI->insertAfter(I); std::vectorArgs; Args.push_back(BCI); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(getTagCounter()); Constant *F = M.getOrInsertFunction("trackctype", VoidTy, VoidPtrTy, Int32Ty, NULL); CallInst *CI = CallInst::Create(F, Args.begin(), Args.end()); CI->insertAfter(BCI); @@ -1383,7 +1391,7 @@ BCI->insertAfter(I); std::vectorArgs; Args.push_back(BCI); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(getTagCounter()); Constant *F = M.getOrInsertFunction("trackctype_32", VoidTy, VoidPtrTy, Int32Ty, NULL); CallInst *CI = CallInst::Create(F, Args.begin(), Args.end()); CI->insertAfter(BCI); @@ -1392,7 +1400,7 @@ BCI->insertAfter(I); std::vectorArgs; Args.push_back(BCI); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(getTagCounter()); Constant *F = M.getOrInsertFunction("trackctype_32", VoidTy, VoidPtrTy, Int32Ty, NULL); CallInst *CI = CallInst::Create(F, Args.begin(), Args.end()); CI->insertAfter(BCI); @@ -1400,7 +1408,7 @@ std::vector Args; Args.push_back(I->getOperand(1)); Args.push_back(I->getOperand(2)); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(getTagCounter()); Constant *F = M.getOrInsertFunction("trackStrcpyInst", VoidTy, VoidPtrTy, VoidPtrTy, Int32Ty, NULL); CallInst::Create(F, Args.begin(), Args.end(), "", I); } else if (F->getNameStr() == std::string("strncpy")) { @@ -1408,18 +1416,18 @@ Args.push_back(I->getOperand(1)); Args.push_back(I->getOperand(2)); Args.push_back(I->getOperand(3)); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(getTagCounter()); Constant *F = M.getOrInsertFunction("trackStrncpyInst", VoidTy, VoidPtrTy, VoidPtrTy, I->getOperand(3)->getType(), Int32Ty, NULL); CallInst::Create(F, Args.begin(), Args.end(), "", I); } else if(F->getNameStr() == std::string("ftime")) { CastInst *BCI = BitCastInst::CreatePointerCast(I->getOperand(1), VoidPtrTy, "", I); const PointerType *PTy = cast(I->getOperand(1)->getType()); const Type * ElementType = PTy->getElementType(); - unsigned int t = TD->getTypeStoreSize(ElementType); + unsigned int size = getSize(ElementType); std::vector Args; Args.push_back(BCI); - Args.push_back(ConstantInt::get(Int64Ty, t)); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(ConstantInt::get(Int64Ty, size)); + Args.push_back(getTagCounter()); CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", I); return true; } else if(F->getNameStr() == std::string("read")) { @@ -1430,7 +1438,7 @@ CastInst *Size = CastInst::CreateIntegerCast(I, Int64Ty, false); Size->insertAfter(I); Args.push_back(Size); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(getTagCounter()); CallInst *CI = CallInst::Create(trackInitInst, Args.begin(), Args.end()); CI->insertAfter(BCI); return true; @@ -1442,7 +1450,7 @@ CastInst *Size = CastInst::CreateIntegerCast(I, Int64Ty, false); Size->insertAfter(I); Args.push_back(Size); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(getTagCounter()); CallInst *CI = CallInst::Create(trackInitInst, Args.begin(), Args.end()); CI->insertAfter(BCI); return true; @@ -1453,7 +1461,7 @@ Args.push_back(BCI); CastInst *Size = CastInst::CreateIntegerCast(I->getOperand(2), Int64Ty, false, "", I); Args.push_back(Size); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(getTagCounter()); CallInst *CI = CallInst::Create(trackInitInst, Args.begin(), Args.end()); CI->insertAfter(BCI); std::vector Args1; @@ -1461,7 +1469,7 @@ Args1.push_back(Size); CastInst *Num = CastInst::CreateIntegerCast(I->getOperand(1), Int64Ty, false, "", I); Args1.push_back(Num); - Args1.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(getTagCounter()); CallInst *CI_Arr = CallInst::Create(trackArray, Args1.begin(), Args1.end()); CI_Arr->insertAfter(CI); return true; @@ -1475,7 +1483,7 @@ Args.push_back(BCI_Src); CastInst *Size = CastInst::CreateIntegerCast(I->getOperand(2), Int64Ty, false, "", I); Args.push_back(Size); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(getTagCounter()); CallInst *CI = CallInst::Create(copyTypeInfo, Args.begin(), Args.end()); CI->insertAfter(BCI_Dest); return true; @@ -1485,7 +1493,7 @@ Args.push_back(BCI); CastInst *Size = CastInst::CreateIntegerCast(I->getOperand(2), Int64Ty, false, "", I); Args.push_back(Size); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(getTagCounter()); CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", I); return true; } else if(F->getNameStr() == std::string("sprintf")) { @@ -1500,7 +1508,7 @@ One); NewValue->insertAfter(Size); Args.push_back(NewValue); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(getTagCounter()); CallInst *CINew = CallInst::Create(trackInitInst, Args.begin(), Args.end()); CINew->insertAfter(NewValue); } else if(F->getNameStr() == std::string("sscanf")) { @@ -1610,8 +1618,8 @@ std::vector Args; Args.push_back(BCI); Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(PTy->getElementType()))); - Args.push_back(ConstantInt::get(Int64Ty, TD->getTypeStoreSize(PTy->getElementType()))); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(ConstantInt::get(Int64Ty, getSize(PTy->getElementType()))); + Args.push_back(getTagCounter()); // Create the call to the runtime check and place it before the store instruction. CallInst::Create(trackStoreInst, Args.begin(), Args.end(), "", CI); @@ -1621,7 +1629,7 @@ // input functions, treat as string, and get length using strlen. std::vector Args; Args.push_back(BCI); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(getTagCounter()); CallInst *CINew = CallInst::Create(trackStringInput, Args.begin(), Args.end()); CINew->insertAfter(CI); } @@ -1637,8 +1645,8 @@ std::vector Args; Args.push_back(BCI); Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(&LI))); - Args.push_back(ConstantInt::get(Int64Ty, TD->getTypeStoreSize(LI.getType()))); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(ConstantInt::get(Int64Ty, getSize(LI.getType()))); + Args.push_back(getTagCounter()); // Create the call to the runtime check and place it before the load instruction. CallInst::Create(trackLoadInst, Args.begin(), Args.end(), "", &LI); @@ -1655,8 +1663,8 @@ Args.push_back(BCI); Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(SI.getOperand(0)))); // SI.getValueOperand() - Args.push_back(ConstantInt::get(Int64Ty, TD->getTypeStoreSize(SI.getOperand(0)->getType()))); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(ConstantInt::get(Int64Ty, getSize(SI.getOperand(0)->getType()))); + Args.push_back(getTagCounter()); // Create the call to the runtime check and place it before the store instruction. CallInst::Create(trackStoreInst, Args.begin(), Args.end(), "", &SI); @@ -1674,8 +1682,8 @@ std::vector Args; Args.push_back(BCI_Dest); Args.push_back(BCI_Src); - Args.push_back(ConstantInt::get(Int64Ty, TD->getTypeStoreSize(SI.getOperand(0)->getType()))); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Args.push_back(ConstantInt::get(Int64Ty, getSize(SI.getOperand(0)->getType()))); + Args.push_back(getTagCounter()); // Create the call to the runtime check and place it before the copying store instruction. CallInst::Create(copyTypeInfo, Args.begin(), Args.end(), "", &SI); From aggarwa4 at illinois.edu Tue Jun 7 09:20:00 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Tue, 07 Jun 2011 16:20:00 -0000 Subject: [llvm-commits] [poolalloc] r132713 - in /poolalloc/trunk: include/assistDS/TypeChecks.h lib/AssistDS/TypeChecks.cpp Message-ID: <20110607162000.34A102A6C12C@llvm.org> Author: aggarwa4 Date: Tue Jun 7 11:20:00 2011 New Revision: 132713 URL: http://llvm.org/viewvc/llvm-project?rev=132713&view=rev Log: Clean up by adding some utility functions. Modified: poolalloc/trunk/include/assistDS/TypeChecks.h poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/include/assistDS/TypeChecks.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/TypeChecks.h?rev=132713&r1=132712&r2=132713&view=diff ============================================================================== --- poolalloc/trunk/include/assistDS/TypeChecks.h (original) +++ poolalloc/trunk/include/assistDS/TypeChecks.h Tue Jun 7 11:20:00 2011 @@ -46,45 +46,57 @@ TypeAnalysis *TA; dsa::TypeSafety *TS; AddressTakenAnalysis* addrAnalysis; - -public: - static char ID; - TypeChecks() : ModulePass(&ID) {} - virtual bool runOnModule(Module &M); - virtual void print(raw_ostream &OS, const Module *M) const; - - virtual void getAnalysisUsage(AnalysisUsage &AU) const { - AU.addRequired(); - AU.addRequired(); - AU.addRequired(); - } - + + unsigned int getTypeMarker(const Type*); + unsigned int getTypeMarker(Value*); + Constant *getTypeMarkerConstant(Value * V); + Constant *getTypeMarkerConstant(const Type* T); + unsigned int getSize(const Type*); + bool initShadow(Module &M); void addTypeMap(Module &M) ; + + bool visitMain(Module &M, Function &F); + bool visitCallInst(Module &M, CallInst &CI); bool visitInvokeInst(Module &M, InvokeInst &CI); bool visitCallSite(Module &M, CallSite CS); bool visitIndirectCallSite(Module &M, Instruction *I); + + bool visitLoadInst(Module &M, LoadInst &LI); + bool visitStoreInst(Module &M, StoreInst &SI); + bool visitCopyingStoreInst(Module &M, StoreInst &SI, Value *SS); + bool visitAllocaInst(Module &M, AllocaInst &AI); + + bool visitGlobal(Module &M, GlobalVariable &GV, + Constant *C, Instruction &I, unsigned offset); + bool visitInternalByValFunction(Module &M, Function &F); bool visitExternalByValFunction(Module &M, Function &F); bool visitByValFunction(Module &M, Function &F); - bool visitMain(Module &M, Function &F); + + bool visitAddressTakenFunction(Module &M, Function &F); + + bool visitVarArgFunction(Module &M, Function &F); - bool visitAddressTakenFunction(Module &M, Function &F); bool visitVAListFunction(Module &M, Function &F); + void visitVAListCall(Function *F); bool visitInternalVarArgFunction(Module &M, Function &F); - bool visitLoadInst(Module &M, LoadInst &LI); - bool visitStoreInst(Module &M, StoreInst &SI); - bool visitAllocaInst(Module &M, AllocaInst &AI); - bool visitGlobal(Module &M, GlobalVariable &GV, - Constant *C, Instruction &I, unsigned offset); - bool visitCopyingStoreInst(Module &M, StoreInst &SI, Value *SS); + bool visitInputFunctionValue(Module &M, Value *V, Instruction *CI); - void visitVAListCall(Function *F); - unsigned int getTypeMarker(const Type*); - unsigned int getTypeMarker(Value*); - unsigned int getSize(const Type*); +public: + static char ID; + TypeChecks() : ModulePass(&ID) {} + virtual bool runOnModule(Module &M); + virtual void print(raw_ostream &OS, const Module *M) const; + + virtual void getAnalysisUsage(AnalysisUsage &AU) const { + AU.addRequired(); + AU.addRequired(); + AU.addRequired(); + } + // Return the map containing all of the types used in the module. const std::map &getTypes() const { return UsedTypes; Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=132713&r1=132712&r2=132713&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Tue Jun 7 11:20:00 2011 @@ -87,6 +87,14 @@ return ConstantInt::get(Int32Ty, tagCounter++); } +Constant *TypeChecks::getTypeMarkerConstant(Value * V) { + return ConstantInt::get(Int8Ty, getTypeMarker(V)); +} + +Constant *TypeChecks::getTypeMarkerConstant(const Type *T) { + return ConstantInt::get(Int8Ty, getTypeMarker(T)); +} + bool TypeChecks::runOnModule(Module &M) { bool modified = false; // Flags whether we modified the module. @@ -306,7 +314,6 @@ } } - // visit all the uses of the address taken functions and modify if // visit all the indirect call sites std::set::iterator II = IndCalls.begin(); @@ -560,7 +567,7 @@ Instruction *VAMetaData = new LoadInst(VAMDLoc, "", VI); Args.push_back(VASize); Args.push_back(OldValue); - Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(VI))); + Args.push_back(getTypeMarkerConstant(VI)); Args.push_back(VAMetaData); Args.push_back(getTagCounter()); CallInst::Create(compareTypeAndNumber, @@ -640,8 +647,7 @@ Idx, Idx + 1, "", CI); - Constant *C = ConstantInt::get(Int8Ty, - getTypeMarker(CI->getOperand(i))); + Constant *C = getTypeMarkerConstant(CI->getOperand(i)); new StoreInst(C, GEP, CI); } @@ -795,7 +801,7 @@ Instruction *VAMetaData = new LoadInst(VAMDLoc, "", VI); Args.push_back(VASize); Args.push_back(OldValue); - Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(VI))); + Args.push_back(getTypeMarkerConstant(VI)); Args.push_back(VAMetaData); Args.push_back(getTagCounter()); CallInst::Create(compareTypeAndNumber, @@ -878,8 +884,7 @@ Idx, Idx + 1, "", CI); - Constant *C = ConstantInt::get(Int8Ty, - getTypeMarker(CI->getOperand(i))); + Constant *C = getTypeMarkerConstant(CI->getOperand(i)); new StoreInst(C, GEP, CI); } @@ -1263,7 +1268,7 @@ std::vector Args; Args.push_back(GEP); - Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(CAZ))); + Args.push_back(getTypeMarkerConstant(CAZ)); Args.push_back(ConstantInt::get(Int64Ty, getSize(CAZ->getType()))); Args.push_back(getTagCounter()); CallInst::Create(trackGlobal, Args.begin(), Args.end(), "", &I); @@ -1279,7 +1284,7 @@ std::vector Args; Args.push_back(GEP); - Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(C))); + Args.push_back(getTypeMarkerConstant(C)); Args.push_back(ConstantInt::get(Int64Ty, getSize(C->getType()))); Args.push_back(getTagCounter()); CallInst::Create(trackGlobal, Args.begin(), Args.end(), "", &I); @@ -1547,8 +1552,7 @@ Idx, Idx + 1, "", I); - Constant *C = ConstantInt::get(Int8Ty, - getTypeMarker(I->getOperand(i))); + Constant *C = getTypeMarkerConstant(I->getOperand(i)); new StoreInst(C, GEP, I); } std::vector Args; @@ -1617,7 +1621,7 @@ std::vector Args; Args.push_back(BCI); - Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(PTy->getElementType()))); + Args.push_back(getTypeMarkerConstant(PTy->getElementType())); Args.push_back(ConstantInt::get(Int64Ty, getSize(PTy->getElementType()))); Args.push_back(getTagCounter()); @@ -1644,7 +1648,7 @@ std::vector Args; Args.push_back(BCI); - Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(&LI))); + Args.push_back(getTypeMarkerConstant(&LI)); Args.push_back(ConstantInt::get(Int64Ty, getSize(LI.getType()))); Args.push_back(getTagCounter()); @@ -1661,8 +1665,7 @@ std::vector Args; Args.push_back(BCI); - Args.push_back(ConstantInt::get(Int8Ty, - getTypeMarker(SI.getOperand(0)))); // SI.getValueOperand() + Args.push_back(getTypeMarkerConstant(SI.getOperand(0))); // SI.getValueOperand() Args.push_back(ConstantInt::get(Int64Ty, getSize(SI.getOperand(0)->getType()))); Args.push_back(getTagCounter()); From aggarwa4 at illinois.edu Tue Jun 7 09:30:15 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Tue, 07 Jun 2011 16:30:15 -0000 Subject: [llvm-commits] [poolalloc] r132714 - in /poolalloc/trunk: include/assistDS/TypeChecks.h lib/AssistDS/TypeChecks.cpp Message-ID: <20110607163015.B18F52A6C12C@llvm.org> Author: aggarwa4 Date: Tue Jun 7 11:30:15 2011 New Revision: 132714 URL: http://llvm.org/viewvc/llvm-project?rev=132714&view=rev Log: Cleanup by adding utility function. Modified: poolalloc/trunk/include/assistDS/TypeChecks.h poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/include/assistDS/TypeChecks.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/TypeChecks.h?rev=132714&r1=132713&r2=132714&view=diff ============================================================================== --- poolalloc/trunk/include/assistDS/TypeChecks.h (original) +++ poolalloc/trunk/include/assistDS/TypeChecks.h Tue Jun 7 11:30:15 2011 @@ -52,6 +52,7 @@ Constant *getTypeMarkerConstant(Value * V); Constant *getTypeMarkerConstant(const Type* T); unsigned int getSize(const Type*); + Constant* getSizeConstant(const Type*); bool initShadow(Module &M); void addTypeMap(Module &M) ; Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=132714&r1=132713&r2=132714&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Tue Jun 7 11:30:15 2011 @@ -83,6 +83,10 @@ return TD->getTypeStoreSize(Ty); } +Constant *TypeChecks::getSizeConstant(const Type *Ty) { + return (ConstantInt::get(Int64Ty, getSize(Ty))); +} + static Constant *getTagCounter() { return ConstantInt::get(Int32Ty, tagCounter++); } @@ -1116,8 +1120,7 @@ CastInst *BCI = BitCastInst::CreatePointerCast(I, VoidPtrTy, "", InsertPt); std::vector Args; Args.push_back(BCI); - unsigned int size = getSize(I->getType()->getElementType()); - Args.push_back(ConstantInt::get(Int64Ty, size)); + Args.push_back(getSizeConstant(I->getType()->getElementType())); Args.push_back(getTagCounter()); CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", InsertPt); continue; @@ -1209,7 +1212,6 @@ if(ConstantArray *CA = dyn_cast(C)) { const Type * ElementType = CA->getType()->getElementType(); - unsigned int t = getSize(ElementType); // Create the type entry for the first element // using recursive creation till we get to the base types visitGlobal(M, GV, CA->getOperand(0), I, offset); @@ -1219,7 +1221,7 @@ CastInst *BCI = BitCastInst::CreatePointerCast(&GV, VoidPtrTy, "", &I); std::vector Args; Args.push_back(BCI); - Args.push_back(ConstantInt::get(Int64Ty, t)); + Args.push_back(getSizeConstant(ElementType)); Args.push_back(ConstantInt::get(Int64Ty, CA->getNumOperands())); Args.push_back(getTagCounter()); CallInst::Create(trackArray, Args.begin(), Args.end(), "", &I); @@ -1241,12 +1243,11 @@ const Type *Ty = CAZ->getType(); if(const ArrayType * ATy = dyn_cast(Ty)) { const Type * ElementType = ATy->getElementType(); - unsigned int size = getSize(ElementType); visitGlobal(M, GV, Constant::getNullValue(ElementType), I, offset); CastInst *BCI = BitCastInst::CreatePointerCast(&GV, VoidPtrTy, "", &I); std::vector Args; Args.push_back(BCI); - Args.push_back(ConstantInt::get(Int64Ty, size)); + Args.push_back(getSizeConstant(ElementType)); Args.push_back(ConstantInt::get(Int64Ty, ATy->getNumElements())); Args.push_back(getTagCounter()); CallInst::Create(trackArray, Args.begin(), Args.end(), "", &I); @@ -1269,7 +1270,7 @@ std::vector Args; Args.push_back(GEP); Args.push_back(getTypeMarkerConstant(CAZ)); - Args.push_back(ConstantInt::get(Int64Ty, getSize(CAZ->getType()))); + Args.push_back(getSizeConstant(CAZ->getType())); Args.push_back(getTagCounter()); CallInst::Create(trackGlobal, Args.begin(), Args.end(), "", &I); } @@ -1285,7 +1286,7 @@ std::vector Args; Args.push_back(GEP); Args.push_back(getTypeMarkerConstant(C)); - Args.push_back(ConstantInt::get(Int64Ty, getSize(C->getType()))); + Args.push_back(getSizeConstant(C->getType())); Args.push_back(getTagCounter()); CallInst::Create(trackGlobal, Args.begin(), Args.end(), "", &I); } @@ -1428,10 +1429,9 @@ CastInst *BCI = BitCastInst::CreatePointerCast(I->getOperand(1), VoidPtrTy, "", I); const PointerType *PTy = cast(I->getOperand(1)->getType()); const Type * ElementType = PTy->getElementType(); - unsigned int size = getSize(ElementType); std::vector Args; Args.push_back(BCI); - Args.push_back(ConstantInt::get(Int64Ty, size)); + Args.push_back(getSizeConstant(ElementType)); Args.push_back(getTagCounter()); CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", I); return true; @@ -1622,7 +1622,7 @@ std::vector Args; Args.push_back(BCI); Args.push_back(getTypeMarkerConstant(PTy->getElementType())); - Args.push_back(ConstantInt::get(Int64Ty, getSize(PTy->getElementType()))); + Args.push_back(getSizeConstant(PTy->getElementType())); Args.push_back(getTagCounter()); // Create the call to the runtime check and place it before the store instruction. @@ -1649,7 +1649,7 @@ std::vector Args; Args.push_back(BCI); Args.push_back(getTypeMarkerConstant(&LI)); - Args.push_back(ConstantInt::get(Int64Ty, getSize(LI.getType()))); + Args.push_back(getSizeConstant(LI.getType())); Args.push_back(getTagCounter()); // Create the call to the runtime check and place it before the load instruction. @@ -1666,7 +1666,7 @@ std::vector Args; Args.push_back(BCI); Args.push_back(getTypeMarkerConstant(SI.getOperand(0))); // SI.getValueOperand() - Args.push_back(ConstantInt::get(Int64Ty, getSize(SI.getOperand(0)->getType()))); + Args.push_back(getSizeConstant(SI.getOperand(0)->getType())); Args.push_back(getTagCounter()); // Create the call to the runtime check and place it before the store instruction. @@ -1685,7 +1685,7 @@ std::vector Args; Args.push_back(BCI_Dest); Args.push_back(BCI_Src); - Args.push_back(ConstantInt::get(Int64Ty, getSize(SI.getOperand(0)->getType()))); + Args.push_back(getSizeConstant(SI.getOperand(0)->getType())); Args.push_back(getTagCounter()); // Create the call to the runtime check and place it before the copying store instruction. From mcinally at cray.com Tue Jun 7 09:56:59 2011 From: mcinally at cray.com (Cameron McInally) Date: Tue, 7 Jun 2011 11:56:59 -0500 Subject: [llvm-commits] [PATCH] Asserts never trip Message-ID: <4DEE585B.2050805@cray.com> Hey guys, I found a few asserts for illegal paths that should always trip, but currently never trip: mcinally/llvm> svn diff Index: utils/TableGen/FastISelEmitter.cpp =================================================================== --- utils/TableGen/FastISelEmitter.cpp (revision 132714) +++ utils/TableGen/FastISelEmitter.cpp (working copy) @@ -278,7 +278,7 @@ } else if (Operands[i].isFP()) { OS << "ConstantFP *f" << i; } else { - assert("Unknown operand kind!"); + assert(0 && "Unknown operand kind!"); abort(); } if (i + 1 != e) @@ -307,7 +307,7 @@ OS << "f" << i; PrintedArg = true; } else { - assert("Unknown operand kind!"); + assert(0 && "Unknown operand kind!"); abort(); } } @@ -322,7 +322,7 @@ } else if (Operands[i].isFP()) { OS << "f" << i; } else { - assert("Unknown operand kind!"); + assert(0 && "Unknown operand kind!"); abort(); } if (i + 1 != e) Tx, Cameron From rdivacky at freebsd.org Tue Jun 7 10:31:02 2011 From: rdivacky at freebsd.org (Roman Divacky) Date: Tue, 07 Jun 2011 17:31:02 -0000 Subject: [llvm-commits] [llvm] r132715 - /llvm/trunk/lib/MC/MCStreamer.cpp Message-ID: <20110607173102.BC46D2A6C12C@llvm.org> Author: rdivacky Date: Tue Jun 7 12:31:02 2011 New Revision: 132715 URL: http://llvm.org/viewvc/llvm-project?rev=132715&view=rev Log: Make EmitIntValue() work properly on big-endian targets. Modified: llvm/trunk/lib/MC/MCStreamer.cpp Modified: llvm/trunk/lib/MC/MCStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCStreamer.cpp?rev=132715&r1=132714&r2=132715&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCStreamer.cpp Tue Jun 7 12:31:02 2011 @@ -15,6 +15,7 @@ #include "llvm/MC/MCSymbol.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/Target/TargetAsmInfo.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/Twine.h" #include @@ -80,9 +81,11 @@ assert((isUIntN(8 * Size, Value) || isIntN(8 * Size, Value)) && "Invalid size"); char buf[8]; - // FIXME: Endianness assumption. - for (unsigned i = 0; i != Size; ++i) - buf[i] = uint8_t(Value >> (i * 8)); + const bool isLittleEndian = Context.getTargetAsmInfo().isLittleEndian(); + for (unsigned i = 0; i != Size; ++i) { + unsigned index = isLittleEndian ? i : (Size - i - 1); + buf[i] = uint8_t(Value >> (index * 8)); + } EmitBytes(StringRef(buf, Size), AddrSpace); } From rdivacky at freebsd.org Tue Jun 7 10:32:18 2011 From: rdivacky at freebsd.org (Roman Divacky) Date: Tue, 07 Jun 2011 17:32:18 -0000 Subject: [llvm-commits] [llvm] r132716 - /llvm/trunk/test/MC/AsmParser/directive_values.s Message-ID: <20110607173218.16BB92A6C12C@llvm.org> Author: rdivacky Date: Tue Jun 7 12:32:17 2011 New Revision: 132716 URL: http://llvm.org/viewvc/llvm-project?rev=132716&view=rev Log: Test that ".byte 1, 2, 3, 4" does the right thing. Requested by nbjoerg! Modified: llvm/trunk/test/MC/AsmParser/directive_values.s Modified: llvm/trunk/test/MC/AsmParser/directive_values.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/directive_values.s?rev=132716&r1=132715&r2=132716&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/directive_values.s (original) +++ llvm/trunk/test/MC/AsmParser/directive_values.s Tue Jun 7 12:32:17 2011 @@ -56,3 +56,10 @@ # CHECK: .byte 35 # CHECK: .byte 9 # CHECK: .byte 10 + +TEST7: + .byte 1, 2, 3, 4 +# CHECK: .byte 1 +# CHECK-NEXT: .byte 2 +# CHECK-NEXT: .byte 3 +# CHECK-NEXT: .byte 4 From ahatanak at gmail.com Tue Jun 7 11:00:15 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Tue, 07 Jun 2011 18:00:15 -0000 Subject: [llvm-commits] [llvm] r132717 - /llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Message-ID: <20110607180015.1C2A32A6C12C@llvm.org> Author: ahatanak Date: Tue Jun 7 13:00:14 2011 New Revision: 132717 URL: http://llvm.org/viewvc/llvm-project?rev=132717&view=rev Log: Add comments for wrapper node patterns in MipsInstrInfo.td. Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=132717&r1=132716&r2=132717&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Jun 7 13:00:14 2011 @@ -87,7 +87,16 @@ def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem, [SDNPOutGlue]>; -// wrapper node +// Target constant nodes that are not part of any isel patterns and remain +// unchanged can cause instructions with illegal operands to be emitted. +// Wrapper node patterns give the instruction selector a chance to replace +// target constant nodes that would otherwise remain unchanged with ADDiu +// nodes. Without these wrapper node patterns, the following conditional move +// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is +// compiled: +// movn %got(d)($gp), %got(c)($gp), $4 +// This instruction is illegal since movn can take only register operands. + def MipsWrapperPIC : SDNode<"MipsISD::WrapperPIC", SDTIntUnaryOp>; //===----------------------------------------------------------------------===// From ahatanak at gmail.com Tue Jun 7 11:16:51 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Tue, 07 Jun 2011 18:16:51 -0000 Subject: [llvm-commits] [llvm] r132718 - /llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Message-ID: <20110607181651.5CD2E2A6C12C@llvm.org> Author: ahatanak Date: Tue Jun 7 13:16:51 2011 New Revision: 132718 URL: http://llvm.org/viewvc/llvm-project?rev=132718&view=rev Log: Use tabs to separate opcode and operand strings. Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=132718&r1=132717&r2=132718&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Tue Jun 7 13:16:51 2011 @@ -77,39 +77,39 @@ multiclass FFR1_1 funct, string asmstr> { def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs), - !strconcat(asmstr, ".s $fd, $fs"), []>; + !strconcat(asmstr, ".s\t$fd, $fs"), []>; def _D32 : FFR<0x11, funct, 0x1, (outs FGR32:$fd), (ins AFGR64:$fs), - !strconcat(asmstr, ".d $fd, $fs"), []>, Requires<[In32BitMode]>; + !strconcat(asmstr, ".d\t$fd, $fs"), []>, Requires<[In32BitMode]>; } multiclass FFR1_2 funct, string asmstr, SDNode FOp> { def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs), - !strconcat(asmstr, ".s $fd, $fs"), + !strconcat(asmstr, ".s\t$fd, $fs"), [(set FGR32:$fd, (FOp FGR32:$fs))]>; def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs), - !strconcat(asmstr, ".d $fd, $fs"), + !strconcat(asmstr, ".d\t$fd, $fs"), [(set AFGR64:$fd, (FOp AFGR64:$fs))]>, Requires<[In32BitMode]>; } class FFR1_3 funct, bits<5> fmt, RegisterClass RcSrc, RegisterClass RcDst, string asmstr>: FFR<0x11, funct, fmt, (outs RcSrc:$fd), (ins RcDst:$fs), - !strconcat(asmstr, " $fd, $fs"), []>; + !strconcat(asmstr, "\t$fd, $fs"), []>; multiclass FFR1_4 funct, string asmstr, SDNode FOp, bit isComm = 0> { let isCommutable = isComm in { def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs, FGR32:$ft), - !strconcat(asmstr, ".s $fd, $fs, $ft"), + !strconcat(asmstr, ".s\t$fd, $fs, $ft"), [(set FGR32:$fd, (FOp FGR32:$fs, FGR32:$ft))]>; def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs, AFGR64:$ft), - !strconcat(asmstr, ".d $fd, $fs, $ft"), + !strconcat(asmstr, ".d\t$fd, $fs, $ft"), [(set AFGR64:$fd, (FOp AFGR64:$fs, AFGR64:$ft))]>, Requires<[In32BitMode]>; } @@ -172,37 +172,37 @@ let fd = 0 in { /// Move Control Registers From/To CPU Registers def CFC1 : FFR<0x11, 0x0, 0x2, (outs CPURegs:$rt), (ins CCR:$fs), - "cfc1 $rt, $fs", []>; + "cfc1\t$rt, $fs", []>; def CTC1 : FFR<0x11, 0x0, 0x6, (outs CCR:$rt), (ins CPURegs:$fs), - "ctc1 $fs, $rt", []>; + "ctc1\t$fs, $rt", []>; def MFC1 : FFR<0x11, 0x00, 0x00, (outs CPURegs:$rt), (ins FGR32:$fs), - "mfc1 $rt, $fs", []>; + "mfc1\t$rt, $fs", []>; def MTC1 : FFR<0x11, 0x00, 0x04, (outs FGR32:$fs), (ins CPURegs:$rt), - "mtc1 $rt, $fs", []>; + "mtc1\t$rt, $fs", []>; } def FMOV_S32 : FFR<0x11, 0b000110, 0x0, (outs FGR32:$fd), (ins FGR32:$fs), - "mov.s $fd, $fs", []>; + "mov.s\t$fd, $fs", []>; def FMOV_D32 : FFR<0x11, 0b000110, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs), - "mov.d $fd, $fs", []>; + "mov.d\t$fd, $fs", []>; /// Floating Point Memory Instructions let Predicates = [IsNotSingleFloat, IsNotMipsI] in { def LDC1 : FFI<0b110101, (outs AFGR64:$ft), (ins mem:$addr), - "ldc1 $ft, $addr", [(set AFGR64:$ft, (load addr:$addr))]>; + "ldc1\t$ft, $addr", [(set AFGR64:$ft, (load addr:$addr))]>; def SDC1 : FFI<0b111101, (outs), (ins AFGR64:$ft, mem:$addr), - "sdc1 $ft, $addr", [(store AFGR64:$ft, addr:$addr)]>; + "sdc1\t$ft, $addr", [(store AFGR64:$ft, addr:$addr)]>; } // LWC1 and SWC1 can always be emitted with odd registers. -def LWC1 : FFI<0b110001, (outs FGR32:$ft), (ins mem:$addr), "lwc1 $ft, $addr", +def LWC1 : FFI<0b110001, (outs FGR32:$ft), (ins mem:$addr), "lwc1\t$ft, $addr", [(set FGR32:$ft, (load addr:$addr))]>; -def SWC1 : FFI<0b111001, (outs), (ins FGR32:$ft, mem:$addr), "swc1 $ft, $addr", - [(store FGR32:$ft, addr:$addr)]>; +def SWC1 : FFI<0b111001, (outs), (ins FGR32:$ft, mem:$addr), + "swc1\t$ft, $addr", [(store FGR32:$ft, addr:$addr)]>; /// Floating-point Aritmetic defm FADD : FFR1_4<0x10, "add", fadd, 1>; @@ -223,7 +223,7 @@ /// Floating Point Branch of False/True (Likely) let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in class FBRANCH : FFI<0x11, (outs), - (ins brtarget:$dst), !strconcat(asmstr, " $dst"), + (ins brtarget:$dst), !strconcat(asmstr, "\t$dst"), [(MipsFPBrcond op, bb:$dst)]>; def BC1F : FBRANCH; @@ -256,11 +256,11 @@ /// Floating Point Compare let hasDelaySlot = 1, Defs=[FCR31] in { def FCMP_S32 : FCC<0x0, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc), - "c.$cc.s $fs, $ft", + "c.$cc.s\t$fs, $ft", [(MipsFPCmp FGR32:$fs, FGR32:$ft, imm:$cc)]>; def FCMP_D32 : FCC<0x1, (outs), (ins AFGR64:$fs, AFGR64:$ft, condcode:$cc), - "c.$cc.d $fs, $ft", + "c.$cc.d\t$fs, $ft", [(MipsFPCmp AFGR64:$fs, AFGR64:$ft, imm:$cc)]>, Requires<[In32BitMode]>; } From aggarwa4 at illinois.edu Tue Jun 7 11:39:48 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Tue, 07 Jun 2011 18:39:48 -0000 Subject: [llvm-commits] [poolalloc] r132720 - in /poolalloc/trunk: include/assistDS/TypeChecksOpt.h lib/AssistDS/TypeChecksOpt.cpp Message-ID: <20110607183948.EC5F62A6C12C@llvm.org> Author: aggarwa4 Date: Tue Jun 7 13:39:48 2011 New Revision: 132720 URL: http://llvm.org/viewvc/llvm-project?rev=132720&view=rev Log: Initial work on removing typesafe runtime checks. Added: poolalloc/trunk/include/assistDS/TypeChecksOpt.h poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Added: poolalloc/trunk/include/assistDS/TypeChecksOpt.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/TypeChecksOpt.h?rev=132720&view=auto ============================================================================== --- poolalloc/trunk/include/assistDS/TypeChecksOpt.h (added) +++ poolalloc/trunk/include/assistDS/TypeChecksOpt.h Tue Jun 7 13:39:48 2011 @@ -0,0 +1,54 @@ +//===---------- TypeChecksOpt.h - Remove safe runtime type checks ---------===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This pass removes type checks that are statically proven safe +// +//===----------------------------------------------------------------------===// + +#ifndef TYPE_CHECKS_OPT_H +#define TYPE_CHECKS_OPT_H + +#include "assistDS/TypeAnalysis.h" +#include "dsa/TypeSafety.h" +#include "dsa/AddressTakenAnalysis.h" + +#include "llvm/Instructions.h" +#include "llvm/Pass.h" +#include "llvm/Target/TargetData.h" +#include "llvm/Support/CallSite.h" + +#include + +namespace llvm { + +class Type; +class Value; + +class TypeChecksOpt : public ModulePass { + +private: + + // Analysis from other passes. + dsa::TypeSafety *TS; + std::list toDelete; + +public: + static char ID; + TypeChecksOpt() : ModulePass(&ID) {} + virtual bool runOnModule(Module &M); + + virtual void getAnalysisUsage(AnalysisUsage &AU) const { + AU.addRequired >(); + } + +}; + +} // End llvm namespace + +#endif Added: poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp?rev=132720&view=auto ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp (added) +++ poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Tue Jun 7 13:39:48 2011 @@ -0,0 +1,186 @@ +//===---------- TypeChecksOpt.h - Remove safe runtime type checks ---------===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This pass removes type checks that are statically proven safe +// +//===----------------------------------------------------------------------===// + +#include "assistDS/TypeChecksOpt.h" +#include "llvm/Constants.h" +#include "llvm/Transforms/Utils/Cloning.h" +#include "llvm/DerivedTypes.h" +#include "llvm/Module.h" +#include "llvm/Assembly/Writer.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/InstIterator.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/Intrinsics.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/ADT/Statistic.h" + +#include +#include + +using namespace llvm; + +char TypeChecksOpt::ID = 0; + +static RegisterPass +TC("typechecks-opt", "Remove safe runtime type checks", false, true); + +// Pass statistics +STATISTIC(numSafe, "Number of statically proven safe type checks"); + +static const Type *VoidTy = 0; +static const Type *Int8Ty = 0; +static const Type *Int32Ty = 0; +static const Type *Int64Ty = 0; +static const PointerType *VoidPtrTy = 0; +static Constant *trackGlobal; +static Constant *trackStringInput; +static Constant *trackArray; +static Constant *trackInitInst; +static Constant *trackStoreInst; +static Constant *trackLoadInst; +static Constant *copyTypeInfo; + +bool TypeChecksOpt::runOnModule(Module &M) { + bool modified = false; // Flags whether we modified the module. + TS = &getAnalysis >(); + + // Create the necessary prototypes + VoidTy = IntegerType::getVoidTy(M.getContext()); + Int8Ty = IntegerType::getInt8Ty(M.getContext()); + Int32Ty = IntegerType::getInt32Ty(M.getContext()); + Int64Ty = IntegerType::getInt64Ty(M.getContext()); + VoidPtrTy = PointerType::getUnqual(Int8Ty); + + trackGlobal = M.getOrInsertFunction("trackGlobal", + VoidTy, + VoidPtrTy,/*ptr*/ + Int8Ty,/*type*/ + Int64Ty,/*size*/ + Int32Ty,/*tag*/ + NULL); + trackArray = M.getOrInsertFunction("trackArray", + VoidTy, + VoidPtrTy,/*ptr*/ + Int64Ty,/*size*/ + Int64Ty,/*count*/ + Int32Ty,/*tag*/ + NULL); + trackInitInst = M.getOrInsertFunction("trackInitInst", + VoidTy, + VoidPtrTy,/*ptr*/ + Int64Ty,/*size*/ + Int32Ty,/*tag*/ + NULL); + trackStoreInst = M.getOrInsertFunction("trackStoreInst", + VoidTy, + VoidPtrTy,/*ptr*/ + Int8Ty,/*type*/ + Int64Ty,/*size*/ + Int32Ty,/*tag*/ + NULL); + trackLoadInst = M.getOrInsertFunction("trackLoadInst", + VoidTy, + VoidPtrTy,/*ptr*/ + Int8Ty,/*type*/ + Int64Ty,/*size*/ + Int32Ty,/*tag*/ + NULL); + copyTypeInfo = M.getOrInsertFunction("copyTypeInfo", + VoidTy, + VoidPtrTy,/*dest ptr*/ + VoidPtrTy,/*src ptr*/ + Int64Ty,/*size*/ + Int32Ty,/*tag*/ + NULL); + trackStringInput = M.getOrInsertFunction("trackStringInput", + VoidTy, + VoidPtrTy, + Int32Ty, + NULL); + + for(Value::use_iterator User = trackGlobal->use_begin(); User != trackGlobal->use_end(); ++User) { + CallInst *CI = dyn_cast(User); + assert(CI); + + if(TS->isTypeSafe(cast(CI->getOperand(1)->stripPointerCasts()))) { + toDelete.push_back(CI); + } + } + + for(Value::use_iterator User = trackLoadInst->use_begin(); User != trackLoadInst->use_end(); ++User) { + CallInst *CI = dyn_cast(User); + assert(CI); + + if(TS->isTypeSafe(CI->getOperand(1)->stripPointerCasts(), CI->getParent()->getParent())) { + toDelete.push_back(CI); + } + } + + for(Value::use_iterator User = trackStoreInst->use_begin(); User != trackStoreInst->use_end(); ++User) { + CallInst *CI = dyn_cast(User); + assert(CI); + + if(TS->isTypeSafe(CI->getOperand(1)->stripPointerCasts(), CI->getParent()->getParent())) { + toDelete.push_back(CI); + } + } + + for(Value::use_iterator User = trackInitInst->use_begin(); User != trackInitInst->use_end(); ++User) { + CallInst *CI = dyn_cast(User); + assert(CI); + + if(TS->isTypeSafe(CI->getOperand(1)->stripPointerCasts(), CI->getParent()->getParent())) { + toDelete.push_back(CI); + } + } + + for(Value::use_iterator User = trackArray->use_begin(); User != trackArray->use_end(); ++User) { + CallInst *CI = dyn_cast(User); + assert(CI); + + if(TS->isTypeSafe(CI->getOperand(1)->stripPointerCasts(), CI->getParent()->getParent())) { + toDelete.push_back(CI); + } + } + for(Value::use_iterator User = copyTypeInfo->use_begin(); User != copyTypeInfo->use_end(); ++User) { + CallInst *CI = dyn_cast(User); + assert(CI); + + if(TS->isTypeSafe(CI->getOperand(1)->stripPointerCasts(), CI->getParent()->getParent())) { + toDelete.push_back(CI); + continue; + } + if(TS->isTypeSafe(CI->getOperand(2)->stripPointerCasts(), CI->getParent()->getParent())) { + std::vector Args; + Args.push_back(CI->getOperand(1)); + Args.push_back(CI->getOperand(3)); // size + Args.push_back(CI->getOperand(4)); + CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", CI); + toDelete.push_back(CI); + } + } + + numSafe += toDelete.size(); + + numSafe += toDelete.size(); + + while(!toDelete.empty()) { + Instruction *I = toDelete.back(); + toDelete.pop_back(); + I->eraseFromParent(); + } + + return modified; +} + + From aggarwa4 at illinois.edu Tue Jun 7 11:41:30 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Tue, 07 Jun 2011 18:41:30 -0000 Subject: [llvm-commits] [poolalloc] r132721 - in /poolalloc/trunk/include: assistDS/TypeChecks.h dsa/AddressTakenAnalysis.h Message-ID: <20110607184130.B3A142A6C12C@llvm.org> Author: aggarwa4 Date: Tue Jun 7 13:41:30 2011 New Revision: 132721 URL: http://llvm.org/viewvc/llvm-project?rev=132721&view=rev Log: Fix includes. Modified: poolalloc/trunk/include/assistDS/TypeChecks.h poolalloc/trunk/include/dsa/AddressTakenAnalysis.h Modified: poolalloc/trunk/include/assistDS/TypeChecks.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/TypeChecks.h?rev=132721&r1=132720&r2=132721&view=diff ============================================================================== --- poolalloc/trunk/include/assistDS/TypeChecks.h (original) +++ poolalloc/trunk/include/assistDS/TypeChecks.h Tue Jun 7 13:41:30 2011 @@ -15,15 +15,17 @@ #define TYPE_CHECKS_H #include "assistDS/TypeAnalysis.h" -#include "dsa/TypeSafety.h" #include "dsa/AddressTakenAnalysis.h" #include "llvm/Instructions.h" +#include "llvm/Function.h" #include "llvm/Pass.h" #include "llvm/Target/TargetData.h" #include "llvm/Support/CallSite.h" #include +#include +#include namespace llvm { @@ -44,7 +46,6 @@ // Analysis from other passes. TargetData *TD; TypeAnalysis *TA; - dsa::TypeSafety *TS; AddressTakenAnalysis* addrAnalysis; unsigned int getTypeMarker(const Type*); Modified: poolalloc/trunk/include/dsa/AddressTakenAnalysis.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/AddressTakenAnalysis.h?rev=132721&r1=132720&r2=132721&view=diff ============================================================================== --- poolalloc/trunk/include/dsa/AddressTakenAnalysis.h (original) +++ poolalloc/trunk/include/dsa/AddressTakenAnalysis.h Tue Jun 7 13:41:30 2011 @@ -16,15 +16,16 @@ #ifndef _ADDRESSTAKENANALYSIS_H #define _ADDRESSTAKENANALYSIS_H +#include "llvm/Pass.h" + +#include +#include + namespace llvm { class Function; class Module; class Instruction; - -#include -#include "llvm/Pass.h" - class AddressTakenAnalysis : public llvm::ModulePass { std::set addressTakenFunctions; public: From ahatanak at gmail.com Tue Jun 7 11:58:42 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Tue, 07 Jun 2011 18:58:42 -0000 Subject: [llvm-commits] [llvm] r132724 - in /llvm/trunk/lib/Target/Mips: MipsFrameLowering.cpp MipsISelDAGToDAG.cpp MipsISelLowering.cpp Message-ID: <20110607185842.C30AB2A6C12C@llvm.org> Author: ahatanak Date: Tue Jun 7 13:58:42 2011 New Revision: 132724 URL: http://llvm.org/viewvc/llvm-project?rev=132724&view=rev Log: Coding style fixes. - Fix indentation. - Move comments. - Fit lines in 80 columns. - Remove dead code. Modified: llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp?rev=132724&r1=132723&r2=132724&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp Tue Jun 7 13:58:42 2011 @@ -195,15 +195,16 @@ SrcML = MachineLocation(MachineLocation::VirtualFP, -StackSize); Moves.push_back(MachineMove(AdjustSPLabel, DstML, SrcML)); - // Find the instruction past the last instruction that saves a callee-saved - // register to the stack. const std::vector &CSI = MFI->getCalleeSavedInfo(); if (CSI.size()) { + // Find the instruction past the last instruction that saves a callee-saved + // register to the stack. for (unsigned i = 0; i < CSI.size(); ++i) ++MBBI; - // Iterate over list of callee-saved registers and emit .cfi_offset directives. + // Iterate over list of callee-saved registers and emit .cfi_offset + // directives. MCSymbol *CSLabel = MMI.getContext().CreateTempSymbol(); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel); Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=132724&r1=132723&r2=132724&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Tue Jun 7 13:58:42 2011 @@ -323,7 +323,6 @@ // tablegen selection should be handled here. /// switch(Opcode) { - default: break; case ISD::SUBE: @@ -357,10 +356,6 @@ LHS, SDValue(AddCarry,0)); } - /// Mul/Div with two results - case ISD::SDIVREM: - case ISD::UDIVREM: - break; case ISD::SMUL_LOHI: case ISD::UMUL_LOHI: { SDValue Op1 = Node->getOperand(0); @@ -407,13 +402,6 @@ return CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag); } - /// Div/Rem operations - case ISD::SREM: - case ISD::UREM: - case ISD::SDIV: - case ISD::UDIV: - break; - // Get target GOT address. case ISD::GLOBAL_OFFSET_TABLE: return getGlobalBaseReg(); Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=132724&r1=132723&r2=132724&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Jun 7 13:58:42 2011 @@ -13,7 +13,6 @@ //===----------------------------------------------------------------------===// #define DEBUG_TYPE "mips-lower" -//#include #include "MipsISelLowering.h" #include "MipsMachineFunction.h" #include "MipsTargetMachine.h" @@ -60,7 +59,7 @@ case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; case MipsISD::WrapperPIC: return "MipsISD::WrapperPIC"; - default: return NULL; + default: return NULL; } } @@ -722,7 +721,8 @@ // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) MachineBasicBlock * MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, - unsigned Size, unsigned BinOpcode, bool Nand) const { + unsigned Size, unsigned BinOpcode, + bool Nand) const { assert(Size == 4 && "Unsupported size for EmitAtomicBinary."); MachineFunction *MF = BB->getParent(); @@ -815,8 +815,9 @@ MachineBasicBlock * MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI, - MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, - bool Nand) const { + MachineBasicBlock *BB, + unsigned Size, unsigned BinOpcode, + bool Nand) const { assert((Size == 1 || Size == 2) && "Unsupported size for EmitAtomicBinaryPartial."); @@ -974,8 +975,8 @@ MachineBasicBlock * MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, - MachineBasicBlock *BB, - unsigned Size) const { + MachineBasicBlock *BB, + unsigned Size) const { assert(Size == 4 && "Unsupported size for EmitAtomicCmpSwap."); MachineFunction *MF = BB->getParent(); @@ -1061,8 +1062,8 @@ MachineBasicBlock * MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI, - MachineBasicBlock *BB, - unsigned Size) const { + MachineBasicBlock *BB, + unsigned Size) const { assert((Size == 1 || Size == 2) && "Unsupported size for EmitAtomicCmpSwapPartial."); @@ -1296,26 +1297,23 @@ SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1); SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo); return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); - } else { - SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, - MipsII::MO_GOT); - GA = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, GA); - SDValue ResNode = DAG.getLoad(MVT::i32, dl, - DAG.getEntryNode(), GA, MachinePointerInfo(), - false, false, 0); - // On functions and global targets not internal linked only - // a load from got/GP is necessary for PIC to work. - if (!GV->hasInternalLinkage() && - (!GV->hasLocalLinkage() || isa(GV))) - return ResNode; - SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, - MipsII::MO_ABS_LO); - SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo); - return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo); } - llvm_unreachable("Dont know how to handle GlobalAddress"); - return SDValue(0,0); + SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, + MipsII::MO_GOT); + GA = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, GA); + SDValue ResNode = DAG.getLoad(MVT::i32, dl, + DAG.getEntryNode(), GA, MachinePointerInfo(), + false, false, 0); + // On functions and global targets not internal linked only + // a load from got/GP is necessary for PIC to work. + if (!GV->hasInternalLinkage() && + (!GV->hasLocalLinkage() || isa(GV))) + return ResNode; + SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, + MipsII::MO_ABS_LO); + SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo); + return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo); } SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op, @@ -1555,7 +1553,8 @@ SDValue MipsTargetLowering:: LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { unsigned Depth = cast(Op.getOperand(0))->getZExtValue(); - assert((Depth == 0) && "Frame address can only be determined for current frame."); + assert((Depth == 0) && + "Frame address can only be determined for current frame."); MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); MFI->setFrameAddressIsTaken(true); @@ -1988,7 +1987,6 @@ const SmallVectorImpl &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl &InVals) const { - // Assign locations to each value returned by this call. SmallVector RVLocs; CCState CCInfo(CallConv, isVarArg, getTargetMachine(), From ahatanak at gmail.com Tue Jun 7 12:03:14 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Tue, 07 Jun 2011 19:03:14 -0000 Subject: [llvm-commits] [llvm] r132725 - /llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Message-ID: <20110607190314.B783B2A6C12C@llvm.org> Author: ahatanak Date: Tue Jun 7 14:03:14 2011 New Revision: 132725 URL: http://llvm.org/viewvc/llvm-project?rev=132725&view=rev Log: Put back removed line. Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=132725&r1=132724&r2=132725&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Tue Jun 7 14:03:14 2011 @@ -356,6 +356,7 @@ LHS, SDValue(AddCarry,0)); } + /// Mul with two results case ISD::SMUL_LOHI: case ISD::UMUL_LOHI: { SDValue Op1 = Node->getOperand(0); From ahatanak at gmail.com Tue Jun 7 12:28:39 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Tue, 07 Jun 2011 19:28:39 -0000 Subject: [llvm-commits] [llvm] r132726 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Message-ID: <20110607192839.A9C7C2A6C12C@llvm.org> Author: ahatanak Date: Tue Jun 7 14:28:39 2011 New Revision: 132726 URL: http://llvm.org/viewvc/llvm-project?rev=132726&view=rev Log: Refactor MipsTargetLowering::EmitInstrWithCustomInserter. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=132726&r1=132725&r2=132726&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Jun 7 14:28:39 2011 @@ -554,97 +554,11 @@ return Mips::BRANCH_INVALID; } -MachineBasicBlock * -MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, - MachineBasicBlock *BB) const { - const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); - bool isFPCmp = false; - DebugLoc dl = MI->getDebugLoc(); - unsigned Opc; - - switch (MI->getOpcode()) { - default: assert(false && "Unexpected instr type to insert"); - - case Mips::ATOMIC_LOAD_ADD_I8: - return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); - case Mips::ATOMIC_LOAD_ADD_I16: - return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); - case Mips::ATOMIC_LOAD_ADD_I32: - return EmitAtomicBinary(MI, BB, 4, Mips::ADDu); - - case Mips::ATOMIC_LOAD_AND_I8: - return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND); - case Mips::ATOMIC_LOAD_AND_I16: - return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND); - case Mips::ATOMIC_LOAD_AND_I32: - return EmitAtomicBinary(MI, BB, 4, Mips::AND); - - case Mips::ATOMIC_LOAD_OR_I8: - return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR); - case Mips::ATOMIC_LOAD_OR_I16: - return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR); - case Mips::ATOMIC_LOAD_OR_I32: - return EmitAtomicBinary(MI, BB, 4, Mips::OR); - - case Mips::ATOMIC_LOAD_XOR_I8: - return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); - case Mips::ATOMIC_LOAD_XOR_I16: - return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); - case Mips::ATOMIC_LOAD_XOR_I32: - return EmitAtomicBinary(MI, BB, 4, Mips::XOR); - - case Mips::ATOMIC_LOAD_NAND_I8: - return EmitAtomicBinaryPartword(MI, BB, 1, 0, true); - case Mips::ATOMIC_LOAD_NAND_I16: - return EmitAtomicBinaryPartword(MI, BB, 2, 0, true); - case Mips::ATOMIC_LOAD_NAND_I32: - return EmitAtomicBinary(MI, BB, 4, 0, true); - - case Mips::ATOMIC_LOAD_SUB_I8: - return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); - case Mips::ATOMIC_LOAD_SUB_I16: - return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); - case Mips::ATOMIC_LOAD_SUB_I32: - return EmitAtomicBinary(MI, BB, 4, Mips::SUBu); - - case Mips::ATOMIC_SWAP_I8: - return EmitAtomicBinaryPartword(MI, BB, 1, 0); - case Mips::ATOMIC_SWAP_I16: - return EmitAtomicBinaryPartword(MI, BB, 2, 0); - case Mips::ATOMIC_SWAP_I32: - return EmitAtomicBinary(MI, BB, 4, 0); - - case Mips::ATOMIC_CMP_SWAP_I8: - return EmitAtomicCmpSwapPartword(MI, BB, 1); - case Mips::ATOMIC_CMP_SWAP_I16: - return EmitAtomicCmpSwapPartword(MI, BB, 2); - case Mips::ATOMIC_CMP_SWAP_I32: - return EmitAtomicCmpSwap(MI, BB, 4); - - case Mips::MOVT: - case Mips::MOVT_S: - case Mips::MOVT_D: - isFPCmp = true; - Opc = Mips::BC1F; - break; - case Mips::MOVF: - case Mips::MOVF_S: - case Mips::MOVF_D: - isFPCmp = true; - Opc = Mips::BC1T; - break; - case Mips::MOVZ_I: - case Mips::MOVZ_S: - case Mips::MOVZ_D: - Opc = Mips::BNE; - break; - case Mips::MOVN_I: - case Mips::MOVN_S: - case Mips::MOVN_D: - Opc = Mips::BEQ; - break; - } - +static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB, + DebugLoc dl, + const MipsSubtarget* Subtarget, + const TargetInstrInfo *TII, + bool isFPCmp, unsigned Opc) { // There is no need to expand CMov instructions if target has // conditional moves. if (Subtarget->hasCondMov()) @@ -688,7 +602,6 @@ BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg()) .addReg(Mips::ZERO).addMBB(sinkMBB); - // copy0MBB: // %FalseValue = ... // # fallthrough to sinkMBB @@ -717,6 +630,91 @@ return BB; } +MachineBasicBlock * +MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, + MachineBasicBlock *BB) const { + const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + DebugLoc dl = MI->getDebugLoc(); + + switch (MI->getOpcode()) { + default: + assert(false && "Unexpected instr type to insert"); + return NULL; + case Mips::MOVT: + case Mips::MOVT_S: + case Mips::MOVT_D: + return ExpandCondMov(MI, BB, dl, Subtarget, TII, true, Mips::BC1F); + case Mips::MOVF: + case Mips::MOVF_S: + case Mips::MOVF_D: + return ExpandCondMov(MI, BB, dl, Subtarget, TII, true, Mips::BC1T); + case Mips::MOVZ_I: + case Mips::MOVZ_S: + case Mips::MOVZ_D: + return ExpandCondMov(MI, BB, dl, Subtarget, TII, false, Mips::BNE); + case Mips::MOVN_I: + case Mips::MOVN_S: + case Mips::MOVN_D: + return ExpandCondMov(MI, BB, dl, Subtarget, TII, false, Mips::BEQ); + + case Mips::ATOMIC_LOAD_ADD_I8: + return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); + case Mips::ATOMIC_LOAD_ADD_I16: + return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); + case Mips::ATOMIC_LOAD_ADD_I32: + return EmitAtomicBinary(MI, BB, 4, Mips::ADDu); + + case Mips::ATOMIC_LOAD_AND_I8: + return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND); + case Mips::ATOMIC_LOAD_AND_I16: + return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND); + case Mips::ATOMIC_LOAD_AND_I32: + return EmitAtomicBinary(MI, BB, 4, Mips::AND); + + case Mips::ATOMIC_LOAD_OR_I8: + return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR); + case Mips::ATOMIC_LOAD_OR_I16: + return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR); + case Mips::ATOMIC_LOAD_OR_I32: + return EmitAtomicBinary(MI, BB, 4, Mips::OR); + + case Mips::ATOMIC_LOAD_XOR_I8: + return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); + case Mips::ATOMIC_LOAD_XOR_I16: + return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); + case Mips::ATOMIC_LOAD_XOR_I32: + return EmitAtomicBinary(MI, BB, 4, Mips::XOR); + + case Mips::ATOMIC_LOAD_NAND_I8: + return EmitAtomicBinaryPartword(MI, BB, 1, 0, true); + case Mips::ATOMIC_LOAD_NAND_I16: + return EmitAtomicBinaryPartword(MI, BB, 2, 0, true); + case Mips::ATOMIC_LOAD_NAND_I32: + return EmitAtomicBinary(MI, BB, 4, 0, true); + + case Mips::ATOMIC_LOAD_SUB_I8: + return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); + case Mips::ATOMIC_LOAD_SUB_I16: + return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); + case Mips::ATOMIC_LOAD_SUB_I32: + return EmitAtomicBinary(MI, BB, 4, Mips::SUBu); + + case Mips::ATOMIC_SWAP_I8: + return EmitAtomicBinaryPartword(MI, BB, 1, 0); + case Mips::ATOMIC_SWAP_I16: + return EmitAtomicBinaryPartword(MI, BB, 2, 0); + case Mips::ATOMIC_SWAP_I32: + return EmitAtomicBinary(MI, BB, 4, 0); + + case Mips::ATOMIC_CMP_SWAP_I8: + return EmitAtomicCmpSwapPartword(MI, BB, 1); + case Mips::ATOMIC_CMP_SWAP_I16: + return EmitAtomicCmpSwapPartword(MI, BB, 2); + case Mips::ATOMIC_CMP_SWAP_I32: + return EmitAtomicCmpSwap(MI, BB, 4); + } +} + // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) MachineBasicBlock * From aggarwa4 at illinois.edu Tue Jun 7 12:30:21 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Tue, 07 Jun 2011 19:30:21 -0000 Subject: [llvm-commits] [poolalloc] r132727 - /poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Message-ID: <20110607193021.10B9E2A6C12C@llvm.org> Author: aggarwa4 Date: Tue Jun 7 14:30:20 2011 New Revision: 132727 URL: http://llvm.org/viewvc/llvm-project?rev=132727&view=rev Log: Fix typo. Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=132727&r1=132726&r2=132727&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Tue Jun 7 14:30:20 2011 @@ -1474,7 +1474,7 @@ Args1.push_back(Size); CastInst *Num = CastInst::CreateIntegerCast(I->getOperand(1), Int64Ty, false, "", I); Args1.push_back(Num); - Args.push_back(getTagCounter()); + Args1.push_back(getTagCounter()); CallInst *CI_Arr = CallInst::Create(trackArray, Args1.begin(), Args1.end()); CI_Arr->insertAfter(CI); return true; From aggarwa4 at illinois.edu Tue Jun 7 12:33:08 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Tue, 07 Jun 2011 19:33:08 -0000 Subject: [llvm-commits] [poolalloc] r132728 - /poolalloc/trunk/lib/DSA/StdLibPass.cpp Message-ID: <20110607193308.C0CC72A6C12C@llvm.org> Author: aggarwa4 Date: Tue Jun 7 14:33:08 2011 New Revision: 132728 URL: http://llvm.org/viewvc/llvm-project?rev=132728&view=rev Log: Teach DSA about the type checking runtime checks. Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/StdLibPass.cpp?rev=132728&r1=132727&r2=132728&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/StdLibPass.cpp (original) +++ poolalloc/trunk/lib/DSA/StdLibPass.cpp Tue Jun 7 14:33:08 2011 @@ -297,6 +297,22 @@ {"pool_strncasecmp",{NRET_NNYARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"pool_bcopy", {NRET_NNYARGS, NRET_NNNYARGS, NRET_NARGS, NRET_NNYARGS, true}}, {"pool_bcmp", {NRET_NNYARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, true}}, + + // Type Checks + {"trackGlobal", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"trackLoadInst", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"trackStoreInst", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"copyTypeInfo", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"trackInitInst", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"trackUnInitInst", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"trackArray", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"trackStringInput", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"trackArgvType", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"compareTypeAndNumber", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"trackctype", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"trackctype_32", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"trackStrcpyInst", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"trackStrcnpyInst", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, #if 0 {"wait", {false, false, false, false, true, false, false, false, false}}, From mcrosier at apple.com Tue Jun 7 13:03:13 2011 From: mcrosier at apple.com (Chad Rosier) Date: Tue, 07 Jun 2011 20:03:13 -0000 Subject: [llvm-commits] [llvm] r132730 - /llvm/trunk/docs/HowToSubmitABug.html Message-ID: <20110607200313.D433F2A6C12C@llvm.org> Author: mcrosier Date: Tue Jun 7 15:03:13 2011 New Revision: 132730 URL: http://llvm.org/viewvc/llvm-project?rev=132730&view=rev Log: Typo. Modified: llvm/trunk/docs/HowToSubmitABug.html Modified: llvm/trunk/docs/HowToSubmitABug.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/HowToSubmitABug.html?rev=132730&r1=132729&r2=132730&view=diff ============================================================================== --- llvm/trunk/docs/HowToSubmitABug.html (original) +++ llvm/trunk/docs/HowToSubmitABug.html Tue Jun 7 15:03:13 2011 @@ -151,7 +151,7 @@

This command should do two things: it should print out a list of passes, and -then it should crash in the same was as llvm-gcc. If it doesn't crash, please +then it should crash in the same way as llvm-gcc. If it doesn't crash, please follow the instructions for a front-end bug.

If this does crash, then you should be able to debug this with the following From mcrosier at apple.com Tue Jun 7 13:41:31 2011 From: mcrosier at apple.com (Chad Rosier) Date: Tue, 07 Jun 2011 20:41:31 -0000 Subject: [llvm-commits] [llvm] r132732 - /llvm/trunk/utils/TableGen/FastISelEmitter.cpp Message-ID: <20110607204132.03E232A6C12C@llvm.org> Author: mcrosier Date: Tue Jun 7 15:41:31 2011 New Revision: 132732 URL: http://llvm.org/viewvc/llvm-project?rev=132732&view=rev Log: Fixed a few illegal paths with llvm_unreachable. Patch by Cameron McInally. Modified: llvm/trunk/utils/TableGen/FastISelEmitter.cpp Modified: llvm/trunk/utils/TableGen/FastISelEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FastISelEmitter.cpp?rev=132732&r1=132731&r2=132732&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/FastISelEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/FastISelEmitter.cpp Tue Jun 7 15:41:31 2011 @@ -19,9 +19,10 @@ #include "FastISelEmitter.h" #include "Record.h" -#include "llvm/Support/Debug.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/VectorExtras.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" using namespace llvm; namespace { @@ -278,8 +279,7 @@ } else if (Operands[i].isFP()) { OS << "ConstantFP *f" << i; } else { - assert("Unknown operand kind!"); - abort(); + llvm_unreachable("Unknown operand kind!"); } if (i + 1 != e) OS << ", "; @@ -307,8 +307,7 @@ OS << "f" << i; PrintedArg = true; } else { - assert("Unknown operand kind!"); - abort(); + llvm_unreachable("Unknown operand kind!"); } } } @@ -322,8 +321,7 @@ } else if (Operands[i].isFP()) { OS << "f" << i; } else { - assert("Unknown operand kind!"); - abort(); + llvm_unreachable("Unknown operand kind!"); } if (i + 1 != e) OS << ", "; From mcrosier at apple.com Tue Jun 7 13:47:43 2011 From: mcrosier at apple.com (Chad Rosier) Date: Tue, 07 Jun 2011 13:47:43 -0700 Subject: [llvm-commits] [PATCH] Asserts never trip In-Reply-To: <4DEE585B.2050805@cray.com> References: <4DEE585B.2050805@cray.com> Message-ID: <067F4FEE-D1E6-458D-BF9B-A4A8A0895A62@apple.com> Thanks Cameron. Committed revision 132732. Chad On Jun 7, 2011, at 9:56 AM, Cameron McInally wrote: > Hey guys, > > I found a few asserts for illegal paths that should always trip, but > currently never trip: > > mcinally/llvm> svn diff > Index: utils/TableGen/FastISelEmitter.cpp > =================================================================== > --- utils/TableGen/FastISelEmitter.cpp (revision 132714) > +++ utils/TableGen/FastISelEmitter.cpp (working copy) > @@ -278,7 +278,7 @@ > } else if (Operands[i].isFP()) { > OS << "ConstantFP *f" << i; > } else { > - assert("Unknown operand kind!"); > + assert(0 && "Unknown operand kind!"); > abort(); > } > if (i + 1 != e) > @@ -307,7 +307,7 @@ > OS << "f" << i; > PrintedArg = true; > } else { > - assert("Unknown operand kind!"); > + assert(0 && "Unknown operand kind!"); > abort(); > } > } > @@ -322,7 +322,7 @@ > } else if (Operands[i].isFP()) { > OS << "f" << i; > } else { > - assert("Unknown operand kind!"); > + assert(0 && "Unknown operand kind!"); > abort(); > } > if (i + 1 != e) > > > Tx, > Cameron > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From echristo at apple.com Tue Jun 7 15:20:13 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 07 Jun 2011 22:20:13 -0000 Subject: [llvm-commits] [llvm] r132734 - in /llvm/trunk/test/FrontendC: ARM/ ARM/inline-asm-multichar.c inline-asm-multichar.c Message-ID: <20110607222013.BAC602A6C12C@llvm.org> Author: echristo Date: Tue Jun 7 17:20:13 2011 New Revision: 132734 URL: http://llvm.org/viewvc/llvm-project?rev=132734&view=rev Log: Create a new ARM directory for FrontendC tests and use it. Added: llvm/trunk/test/FrontendC/ARM/ llvm/trunk/test/FrontendC/ARM/inline-asm-multichar.c - copied unchanged from r132733, llvm/trunk/test/FrontendC/inline-asm-multichar.c Removed: llvm/trunk/test/FrontendC/inline-asm-multichar.c Removed: llvm/trunk/test/FrontendC/inline-asm-multichar.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/inline-asm-multichar.c?rev=132733&view=auto ============================================================================== --- llvm/trunk/test/FrontendC/inline-asm-multichar.c (original) +++ llvm/trunk/test/FrontendC/inline-asm-multichar.c (removed) @@ -1,11 +0,0 @@ -// RUN: %llvmgcc -S -march=armv7a %s - -// XFAIL: * -// XTARGET: arm - -int t1() { - static float k = 1.0f; -CHECK: call void asm sideeffect "flds s15, $0 \0A", "*^Uv,~{s15}" - __asm__ volatile ("flds s15, %[k] \n" :: [k] "Uv,m" (k) : "s15"); - return 0; -} From rafael.espindola at gmail.com Tue Jun 7 16:26:45 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Tue, 07 Jun 2011 23:26:45 -0000 Subject: [llvm-commits] [llvm] r132735 - in /llvm/trunk: lib/CodeGen/TargetLoweringObjectFileImpl.cpp test/CodeGen/X86/eh_frame.ll Message-ID: <20110607232646.20A1B2A6C12C@llvm.org> Author: rafael Date: Tue Jun 7 18:26:45 2011 New Revision: 132735 URL: http://llvm.org/viewvc/llvm-project?rev=132735&view=rev Log: Fix a silly error I introduce in r131951. Fixes PR10095. Modified: llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp llvm/trunk/test/CodeGen/X86/eh_frame.ll Modified: llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp?rev=132735&r1=132734&r2=132735&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp (original) +++ llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Tue Jun 7 18:26:45 2011 @@ -255,9 +255,6 @@ Name.startswith(".llvm.linkonce.tb.")) return SectionKind::getThreadBSS(); - if (Name == ".eh_frame") - return SectionKind::getReadOnlyWithRel(); - return K; } @@ -290,7 +287,7 @@ if (K.isText()) Flags |= ELF::SHF_EXECINSTR; - if (K.isWriteable() && !K.isReadOnlyWithRel()) + if (K.isWriteable()) Flags |= ELF::SHF_WRITE; if (K.isThreadLocal()) Modified: llvm/trunk/test/CodeGen/X86/eh_frame.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/eh_frame.ll?rev=132735&r1=132734&r2=132735&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/eh_frame.ll (original) +++ llvm/trunk/test/CodeGen/X86/eh_frame.ll Tue Jun 7 18:26:45 2011 @@ -1,5 +1,14 @@ -; RUN: llc < %s -mtriple x86_64-unknown-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple x86_64-unknown-linux-gnu | FileCheck -check-prefix=STATIC %s +; RUN: llc < %s -mtriple x86_64-unknown-linux-gnu -relocation-model=pic | FileCheck -check-prefix=PIC %s @__FRAME_END__ = constant [1 x i32] zeroinitializer, section ".eh_frame" -; CHECK: .section .eh_frame,"a", at progbits + at foo = external global i32 + at bar1 = constant i8* bitcast (i32* @foo to i8*), section "my_bar1", align 8 + + +; STATIC: .section .eh_frame,"a", at progbits +; STATIC: .section my_bar1,"a", at progbits + +; PIC: .section .eh_frame,"a", at progbits +; PIC: .section my_bar1,"aw", at progbits From zwarich at apple.com Tue Jun 7 16:54:00 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Tue, 07 Jun 2011 23:54:00 -0000 Subject: [llvm-commits] [llvm] r132738 - in /llvm/trunk: lib/CodeGen/TwoAddressInstructionPass.cpp test/CodeGen/Thumb2/2011-06-07-TwoAddrEarlyClobber.ll Message-ID: <20110607235400.776222A6C12C@llvm.org> Author: zwarich Date: Tue Jun 7 18:54:00 2011 New Revision: 132738 URL: http://llvm.org/viewvc/llvm-project?rev=132738&view=rev Log: Fix an issue where the two-address conversion pass incorrectly rewrites untied operands to an early clobber register. This fixes . Added: llvm/trunk/test/CodeGen/Thumb2/2011-06-07-TwoAddrEarlyClobber.ll Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=132738&r1=132737&r2=132738&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original) +++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Tue Jun 7 18:54:00 2011 @@ -1125,6 +1125,7 @@ break; // The tied operands have been eliminated. } + bool IsEarlyClobber = false; bool RemovedKillFlag = false; bool AllUsesCopied = true; unsigned LastCopiedReg = 0; @@ -1132,7 +1133,11 @@ for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) { unsigned SrcIdx = TiedPairs[tpi].first; unsigned DstIdx = TiedPairs[tpi].second; - unsigned regA = mi->getOperand(DstIdx).getReg(); + + const MachineOperand &DstMO = mi->getOperand(DstIdx); + unsigned regA = DstMO.getReg(); + IsEarlyClobber |= DstMO.isEarlyClobber(); + // Grab regB from the instruction because it may have changed if the // instruction was commuted. regB = mi->getOperand(SrcIdx).getReg(); @@ -1196,15 +1201,17 @@ } if (AllUsesCopied) { - // Replace other (un-tied) uses of regB with LastCopiedReg. - for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) { - MachineOperand &MO = mi->getOperand(i); - if (MO.isReg() && MO.getReg() == regB && MO.isUse()) { - if (MO.isKill()) { - MO.setIsKill(false); - RemovedKillFlag = true; + if (!IsEarlyClobber) { + // Replace other (un-tied) uses of regB with LastCopiedReg. + for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) { + MachineOperand &MO = mi->getOperand(i); + if (MO.isReg() && MO.getReg() == regB && MO.isUse()) { + if (MO.isKill()) { + MO.setIsKill(false); + RemovedKillFlag = true; + } + MO.setReg(LastCopiedReg); } - MO.setReg(LastCopiedReg); } } Added: llvm/trunk/test/CodeGen/Thumb2/2011-06-07-TwoAddrEarlyClobber.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2011-06-07-TwoAddrEarlyClobber.ll?rev=132738&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2011-06-07-TwoAddrEarlyClobber.ll (added) +++ llvm/trunk/test/CodeGen/Thumb2/2011-06-07-TwoAddrEarlyClobber.ll Tue Jun 7 18:54:00 2011 @@ -0,0 +1,36 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin10" + +%struct.op = type { %struct.op*, %struct.op*, %struct.op* ()*, i32, i16, i16, i8, i8 } + +; CHECK: Perl_ck_sort +; CHECK: ldr +; CHECK: mov [[REGISTER:(r[0-9]+)|(lr)]] +; CHECK: str {{(r[0-9])|(lr)}}, {{\[}}[[REGISTER]]{{\]}}, #24 + +define void @Perl_ck_sort() nounwind optsize { +entry: + %tmp27 = load %struct.op** undef, align 4 + switch i16 undef, label %if.end151 [ + i16 178, label %if.then60 + i16 177, label %if.then60 + ] + +if.then60: ; preds = %if.then40 + br i1 undef, label %if.then67, label %if.end95 + +if.then67: ; preds = %if.then60 + %op_next71 = getelementptr inbounds %struct.op* %tmp27, i32 0, i32 0 + store %struct.op* %tmp27, %struct.op** %op_next71, align 4 + %0 = getelementptr inbounds %struct.op* %tmp27, i32 1, i32 0 + br label %if.end95 + +if.end95: ; preds = %if.else92, %if.then67 + %.pre-phi = phi %struct.op** [ undef, %if.then60 ], [ %0, %if.then67 ] + %tmp98 = load %struct.op** %.pre-phi, align 4 + br label %if.end151 + +if.end151: ; preds = %if.end100, %if.end, %entry + ret void +} From atrick at apple.com Tue Jun 7 18:37:51 2011 From: atrick at apple.com (Andrew Trick) Date: Tue, 07 Jun 2011 18:37:51 -0700 Subject: [llvm-commits] [llvm] r132613 - in /llvm/trunk: include/llvm/Analysis/BranchProbabilityInfo.h include/llvm/InitializePasses.h lib/Analysis/Analysis.cpp lib/Analysis/BranchProbabilityInfo.cpp lib/Analysis/CMakeLists.txt In-Reply-To: <05052AFC-4F19-4689-8E3D-37B7A083C472@gmail.com> References: <20110604011630.EB7B52A6C12C@llvm.org> <05052AFC-4F19-4689-8E3D-37B7A083C472@gmail.com> Message-ID: On Jun 3, 2011, at 7:29 PM, Alistair Lynn wrote: > Hi- > > Given that > >> + // Returned value is between 1 and UINT_MAX. Look at BranchProbabilityInfo.cpp >> + // for details. > > Is this function not prone to integer overflow issues? > >> +// TODO: This currently hardcodes 80% as a fraction 4/5. We will soon add a >> +// BranchProbability class to encapsulate the fractional probability and >> +// define a few static instances of the class for use as predefined thresholds. >> +bool BranchProbabilityInfo::isEdgeHot(BasicBlock *Src, BasicBlock *Dst) const { >> + unsigned Sum = 0; >> + for (succ_iterator I = succ_begin(Src), E = succ_end(Src); I != E; ++I) { >> + BasicBlock *Succ = *I; >> + unsigned Weight = getEdgeWeight(Src, Succ); >> + unsigned PrevSum = Sum; >> + >> + Sum += Weight; >> + assert(Sum > PrevSum); (void) PrevSum; >> + } >> + >> + return getEdgeWeight(Src, Dst) * 5 > Sum * 4; >> +} > > The sum itself is checked for overflow in the assert, but surely there's nothing preventing overflow on the multiplies on the condition at the end? > > Alistair Thanks for the review. Jakub is planning to implement multiplication by branch probability as 64 bit multiply with overflow check. This case should be fixed soon. FYI. The design doc expresses our intent to avoid numerical issues but we probably won't have it perfect in the first patch set. Still it's good to keep pointing out discrepancies. Jakub, feel free to use FIXME comments in places that need more work. Andy From atrick at apple.com Tue Jun 7 18:49:44 2011 From: atrick at apple.com (Andrew Trick) Date: Tue, 07 Jun 2011 18:49:44 -0700 Subject: [llvm-commits] [llvm] r132613 - in /llvm/trunk: include/llvm/Analysis/BranchProbabilityInfo.h include/llvm/InitializePasses.h lib/Analysis/Analysis.cpp lib/Analysis/BranchProbabilityInfo.cpp lib/Analysis/CMakeLists.txt In-Reply-To: <083E2883-621E-4E61-91D7-2CECD31D1F6A@2pi.dk> References: <20110604011630.EB7B52A6C12C@llvm.org> <8A8469FC-8F84-4974-B227-3944E47B2301@2pi.dk> <083E2883-621E-4E61-91D7-2CECD31D1F6A@2pi.dk> Message-ID: <4BE86E59-86D5-4513-9314-938EEBA03428@apple.com> On Jun 4, 2011, at 9:53 AM, Jakob Stoklund Olesen wrote: > > On Jun 4, 2011, at 1:50 AM, Frits van Bommel wrote: > >> On 4 June 2011 10:19, Jakob Stoklund Olesen wrote: >>> On Jun 4, 2011, at 12:56 AM, Frits van Bommel wrote: >>>> Shouldn't you use 'uint32_t' instead of 'unsigned (int)' throughout >>>> (and UINT32_MAX instead of UINT_MAX, etc.)? >>> >>> LLVM assumes that unsigned is 32 bits in *many* places. It won't work with >>> any other int size. >> >> Do they assume it's 32 bits, or that it's *at least* 32 bits? > > You can grep '~0' on the sources to get an idea, but I am sure most places would work with a larger int. > >> Note >> that this code essentially assumes it's *exactly* 32 bits because its >> results depend on the exact value of UINT_MAX. > > Sure, let's use UINT32_MAX for the exact value. > >> But even if what you say is true, I don't consider that to be a good >> excuse to contribute to the problem. > > Which problem? 36-bit preparedness? > >> And many places in LLVM use >> (u)int32_t, too. >> >> If nothing else, uint32_t is more self-documenting. > > If a C implementation decides to take on all the portability issues that come from having a 64-bit int, it has to be because 32-bit arithmetic performance is horrible. The uint32_t type makes sense when you need the compact size, or when you depend on modulo 2^32 arithmetic. > > /jakob > Then what do we cast to for overflow checking? Andy From aggarwa4 at illinois.edu Tue Jun 7 19:01:45 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 08 Jun 2011 02:01:45 -0000 Subject: [llvm-commits] [poolalloc] r132739 - /poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Message-ID: <20110608020145.D7D252A6C12C@llvm.org> Author: aggarwa4 Date: Tue Jun 7 21:01:45 2011 New Revision: 132739 URL: http://llvm.org/viewvc/llvm-project?rev=132739&view=rev Log: track Global is also used for gep's into globals. Treat as Value instead of globalvalue. Modified: poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp?rev=132739&r1=132738&r2=132739&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Tue Jun 7 21:01:45 2011 @@ -112,7 +112,7 @@ CallInst *CI = dyn_cast(User); assert(CI); - if(TS->isTypeSafe(cast(CI->getOperand(1)->stripPointerCasts()))) { + if(TS->isTypeSafe((CI->getOperand(1)->stripPointerCasts(), CI->getParent()->getParent()))) { toDelete.push_back(CI); } } From stoklund at 2pi.dk Tue Jun 7 20:00:37 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 7 Jun 2011 20:00:37 -0700 Subject: [llvm-commits] [llvm] r132613 - in /llvm/trunk: include/llvm/Analysis/BranchProbabilityInfo.h include/llvm/InitializePasses.h lib/Analysis/Analysis.cpp lib/Analysis/BranchProbabilityInfo.cpp lib/Analysis/CMakeLists.txt In-Reply-To: <4BE86E59-86D5-4513-9314-938EEBA03428@apple.com> References: <20110604011630.EB7B52A6C12C@llvm.org> <8A8469FC-8F84-4974-B227-3944E47B2301@2pi.dk> <083E2883-621E-4E61-91D7-2CECD31D1F6A@2pi.dk> <4BE86E59-86D5-4513-9314-938EEBA03428@apple.com> Message-ID: <3BE1AC6C-154A-460F-94E7-A8DF0910DE92@2pi.dk> On Jun 7, 2011, at 6:49 PM, Andrew Trick wrote: >>> And many places in LLVM use >>> (u)int32_t, too. >>> >>> If nothing else, uint32_t is more self-documenting. >> >> If a C implementation decides to take on all the portability issues that come from having a 64-bit int, it has to be because 32-bit arithmetic performance is horrible. The uint32_t type makes sense when you need the compact size, or when you depend on modulo 2^32 arithmetic. > Then what do we cast to for overflow checking? uint32_t This discussion is rather academic. LLVM builds on ILP32, LP64, and LLP64 platforms where an int is 32 bits and plenty fast. I don't think anyone has tried porting it to a platform where that isn't true, but they would likely have to fix a lot of code that uses int/unsigned. If we start using uint32_t everywhere, they will now have to check if we really meant "I need exactly 32 bits, regardless of performance", or did we really mean to use uint_fast32_t instead. Either way, they get to look at all the code. But yeah, if you depend on having exactly 32 bits for an overflow test, use uint32_t. Of course a C implementation is not required to have a 32-bit type, so uint32_t may not exist. If you want to pretend to write portable code, you have to stick to uint_least32_t and uint_fast32_t. I have never seen code that does that, and we don't even bother defining these types in DataTypes.h /jakob -------------- next part -------------- An HTML attachment was scrubbed... URL: From nicholas at mxc.ca Tue Jun 7 23:11:05 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 07 Jun 2011 23:11:05 -0700 Subject: [llvm-commits] patch: folding (zext (and x, cst)) In-Reply-To: References: <4DEDF373.5000004@mxc.ca> Message-ID: <4DEF1279.5040002@mxc.ca> Jakob Stoklund Olesen wrote: > > On Jun 7, 2011, at 7:58 AM, Eli Friedman wrote: > >> On Tue, Jun 7, 2011 at 2:46 AM, Nick Lewycky wrote: >>> I have an unfinished patch. I was looking to optimize: >>> >>> define i32 @test1(i8 %x) nounwind readnone { >>> %A = and i8 %x, -32 >>> %B = zext i8 %A to i32 >>> ret i32 %B >>> } >>> >>> which currently does a mov into %al, then the "and", then extends, into >>> doing a single extending mov, then an "and" in 32-bits. The rule I decided >>> upon is "(zext (and x, cst)) -> (and (anyext x), (zext cst))" in the DAG >>> combiner. >> >> Just a comment, without reading the patch: it would be much more >> conservative to fold (zext (and (load x), cst)) -> (and (zextload x), >> (zext cst)). The transform you're proposing is much less obviously >> beneficial. > > Also make sure this does the right thing on x86 when the zext is i32 -> i64. The and implicitly zero-extends to 64 bit. Could you elaborate? Are you saying that ISD::AND may have a wider result than its arguments? Nick From baldrick at free.fr Wed Jun 8 00:03:04 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 08 Jun 2011 07:03:04 -0000 Subject: [llvm-commits] [dragonegg] r132740 - /dragonegg/trunk/src/Constants.cpp Message-ID: <20110608070304.A016A2A6C12C@llvm.org> Author: baldrick Date: Wed Jun 8 02:03:04 2011 New Revision: 132740 URL: http://llvm.org/viewvc/llvm-project?rev=132740&view=rev Log: Hoist getting IntPtrTy out of the loop. Modified: dragonegg/trunk/src/Constants.cpp Modified: dragonegg/trunk/src/Constants.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Constants.cpp?rev=132740&r1=132739&r2=132740&view=diff ============================================================================== --- dragonegg/trunk/src/Constants.cpp (original) +++ dragonegg/trunk/src/Constants.cpp Wed Jun 8 02:03:04 2011 @@ -541,15 +541,14 @@ unsigned NumElts = TYPE_VECTOR_SUBPARTS(type); unsigned Stride = GET_MODE_BITSIZE(TYPE_MODE(elt_type)); SmallVector Vals(NumElts); + const IntegerType *IntPtrTy = getTargetData().getIntPtrType(Context); for (unsigned i = 0; i != NumElts; ++i) { Vals[i] = ExtractRegisterFromConstantImpl(C, elt_type, StartingBit+i*Stride, Folder); // LLVM does not support vectors of pointers, so turn any pointers into // integers. - if (isa(Vals[i]->getType())) { - const IntegerType *IntTy = getTargetData().getIntPtrType(Context); - Vals[i] = Folder.CreatePtrToInt(Vals[i], IntTy); - } + if (isa(Vals[i]->getType())) + Vals[i] = Folder.CreatePtrToInt(Vals[i], IntPtrTy); } return ConstantVector::get(Vals); } From baldrick at free.fr Wed Jun 8 00:03:32 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 08 Jun 2011 07:03:32 -0000 Subject: [llvm-commits] [dragonegg] r132741 - /dragonegg/trunk/src/Convert.cpp Message-ID: <20110608070332.DD2D22A6C12C@llvm.org> Author: baldrick Date: Wed Jun 8 02:03:32 2011 New Revision: 132741 URL: http://llvm.org/viewvc/llvm-project?rev=132741&view=rev Log: Support for constant vectors of pointers at the gimple level. Modified: dragonegg/trunk/src/Convert.cpp Modified: dragonegg/trunk/src/Convert.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=132741&r1=132740&r2=132741&view=diff ============================================================================== --- dragonegg/trunk/src/Convert.cpp (original) +++ dragonegg/trunk/src/Convert.cpp Wed Jun 8 02:03:32 2011 @@ -6240,13 +6240,20 @@ // Convert the elements. SmallVector Elts; - for (tree elt = TREE_VECTOR_CST_ELTS(reg); elt; elt = TREE_CHAIN(elt)) - Elts.push_back(EmitRegisterConstant(TREE_VALUE(elt))); + const IntegerType *IntTy = getTargetData().getIntPtrType(Context); + for (tree elt = TREE_VECTOR_CST_ELTS(reg); elt; elt = TREE_CHAIN(elt)) { + Constant *Elt = EmitRegisterConstant(TREE_VALUE(elt)); + // LLVM does not support vectors of pointers, so turn any pointers into + // integers. + if (isa(Elt->getType())) + Elt = Builder.getFolder().CreatePtrToInt(Elt, IntTy); + Elts.push_back(Elt); + } // If there weren't enough elements then set the rest of the vector to the // default value. if (Elts.size() < TYPE_VECTOR_SUBPARTS(TREE_TYPE(reg))) { - Constant *Default = getDefaultValue(getRegType(TREE_TYPE(TREE_TYPE(reg)))); + Constant *Default = getDefaultValue(Elts[0]->getType()); Elts.append(TYPE_VECTOR_SUBPARTS(TREE_TYPE(reg)) - Elts.size(), Default); } From baldrick at free.fr Wed Jun 8 01:07:00 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 08 Jun 2011 08:07:00 -0000 Subject: [llvm-commits] [dragonegg] r132742 - in /dragonegg/trunk: include/dragonegg/Internals.h src/Convert.cpp Message-ID: <20110608080700.1FC212A6C12D@llvm.org> Author: baldrick Date: Wed Jun 8 03:06:59 2011 New Revision: 132742 URL: http://llvm.org/viewvc/llvm-project?rev=132742&view=rev Log: Add support for VEC_UNPACK_FLOAT_HI_EXPR/VEC_UNPACK_FLOAT_LO_EXPR. It turns out that the existing code for VEC_UNPACK_HI/LO_EXPR works fine for this, so just reuse it. This fixes PR10014. Modified: dragonegg/trunk/include/dragonegg/Internals.h dragonegg/trunk/src/Convert.cpp Modified: dragonegg/trunk/include/dragonegg/Internals.h URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/include/dragonegg/Internals.h?rev=132742&r1=132741&r2=132742&view=diff ============================================================================== --- dragonegg/trunk/include/dragonegg/Internals.h (original) +++ dragonegg/trunk/include/dragonegg/Internals.h Wed Jun 8 03:06:59 2011 @@ -701,6 +701,8 @@ Value *EmitReg_VecShiftOp(tree_node *op0, tree_node *op1, bool isLeftShift); Value *EmitReg_TruthOp(tree_node *type, tree_node *op0, tree_node *op1, unsigned Opc); + Value *EmitReg_VecUnpackHiExpr(tree_node *type, tree_node *op0); + Value *EmitReg_VecUnpackLoExpr(tree_node *type, tree_node *op0); Value *EmitReg_BIT_AND_EXPR(tree_node *op0, tree_node *op1); Value *EmitReg_BIT_IOR_EXPR(tree_node *op0, tree_node *op1); Value *EmitReg_BIT_XOR_EXPR(tree_node *op0, tree_node *op1); @@ -723,8 +725,6 @@ Value *EmitReg_VEC_INTERLEAVE_LOW_EXPR(tree_node *op0, tree_node *op1); Value *EmitReg_VEC_PACK_TRUNC_EXPR(tree_node *type, tree_node *op0, tree_node *op1); - Value *EmitReg_VEC_UNPACK_HI_EXPR(tree_node *type, tree_node *op0); - Value *EmitReg_VEC_UNPACK_LO_EXPR(tree_node *type, tree_node *op0); Value *EmitLoadOfLValue(tree_node *exp); Value *EmitOBJ_TYPE_REF(tree_node *exp); Modified: dragonegg/trunk/src/Convert.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=132742&r1=132741&r2=132742&view=diff ============================================================================== --- dragonegg/trunk/src/Convert.cpp (original) +++ dragonegg/trunk/src/Convert.cpp Wed Jun 8 03:06:59 2011 @@ -7375,7 +7375,7 @@ return Builder.CreateShuffleVector(LHS, RHS, ConstantVector::get(Mask)); } -Value *TreeToLLVM::EmitReg_VEC_UNPACK_HI_EXPR(tree type, tree op0) { +Value *TreeToLLVM::EmitReg_VecUnpackHiExpr(tree type, tree op0) { // Eg: <2 x double> = VEC_UNPACK_HI_EXPR(<4 x float>) Value *Op = EmitRegister(op0); @@ -7389,7 +7389,7 @@ !TYPE_UNSIGNED(TREE_TYPE(type))); } -Value *TreeToLLVM::EmitReg_VEC_UNPACK_LO_EXPR(tree type, tree op0) { +Value *TreeToLLVM::EmitReg_VecUnpackLoExpr(tree type, tree op0) { // Eg: <2 x double> = VEC_UNPACK_LO_EXPR(<4 x float>) Value *Op = EmitRegister(op0); @@ -8390,10 +8390,12 @@ RHS = EmitReg_VEC_PACK_TRUNC_EXPR(type, rhs1, rhs2); break; case VEC_RSHIFT_EXPR: RHS = EmitReg_VecShiftOp(rhs1, rhs2, /*isLeftShift*/false); break; + case VEC_UNPACK_FLOAT_HI_EXPR: case VEC_UNPACK_HI_EXPR: - RHS = EmitReg_VEC_UNPACK_HI_EXPR(type, rhs1); break; + RHS = EmitReg_VecUnpackHiExpr(type, rhs1); break; + case VEC_UNPACK_FLOAT_LO_EXPR: case VEC_UNPACK_LO_EXPR: - RHS = EmitReg_VEC_UNPACK_LO_EXPR(type, rhs1); break; + RHS = EmitReg_VecUnpackLoExpr(type, rhs1); break; } return TriviallyTypeConvert(RHS, getRegType(type)); From stoklund at 2pi.dk Wed Jun 8 06:18:54 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 8 Jun 2011 06:18:54 -0700 Subject: [llvm-commits] patch: folding (zext (and x, cst)) In-Reply-To: <4DEF1279.5040002@mxc.ca> References: <4DEDF373.5000004@mxc.ca> <4DEF1279.5040002@mxc.ca> Message-ID: <88ADE6CB-0F93-4031-A3EE-4CE48E7C6E32@2pi.dk> On Jun 7, 2011, at 11:11 PM, Nick Lewycky wrote: > Jakob Stoklund Olesen wrote: >> >> On Jun 7, 2011, at 7:58 AM, Eli Friedman wrote: >> >>> On Tue, Jun 7, 2011 at 2:46 AM, Nick Lewycky wrote: >>>> I have an unfinished patch. I was looking to optimize: >>>> >>>> define i32 @test1(i8 %x) nounwind readnone { >>>> %A = and i8 %x, -32 >>>> %B = zext i8 %A to i32 >>>> ret i32 %B >>>> } >>>> >>>> which currently does a mov into %al, then the "and", then extends, into >>>> doing a single extending mov, then an "and" in 32-bits. The rule I decided >>>> upon is "(zext (and x, cst)) -> (and (anyext x), (zext cst))" in the DAG >>>> combiner. >>> >>> Just a comment, without reading the patch: it would be much more >>> conservative to fold (zext (and (load x), cst)) -> (and (zextload x), >>> (zext cst)). The transform you're proposing is much less obviously >>> beneficial. >> >> Also make sure this does the right thing on x86 when the zext is i32 -> i64. The and implicitly zero-extends to 64 bit. > > Could you elaborate? Are you saying that ISD::AND may have a wider result than its arguments? 32-bit operations on x86-64 will usually clear the high part of the destination register. That means the 32-64 bit zero-extension is really a noop: // Any instruction that defines a 32-bit result leaves the high half of the // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may // be copying from a truncate. And x86's cmov doesn't do anything if the // condition is false. But any other 32-bit operation will zero-extend // up to 64 bits. def def32 : PatLeaf<(i32 GR32:$src), [{ return N->getOpcode() != ISD::TRUNCATE && N->getOpcode() != TargetOpcode::EXTRACT_SUBREG && N->getOpcode() != ISD::CopyFromReg && N->getOpcode() != X86ISD::CMOV; }]>; // In the case of a 32-bit def that is known to implicitly zero-extend, // we can use a SUBREG_TO_REG. def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; That means (zext (and x, cst)) simply becomes (SUBREG_TO_REG (AND32ri x,cst), sub_32bit). The SUBREG_TO_REG is emitted as a copy which is almost always coalesced away. It looks like it will work out, but you should make sure that you are not increasing code size for this common case. /jakob From baldrick at free.fr Wed Jun 8 07:06:18 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 08 Jun 2011 14:06:18 -0000 Subject: [llvm-commits] [dragonegg] r132747 - /dragonegg/trunk/src/Convert.cpp Message-ID: <20110608140618.E45182A6C12C@llvm.org> Author: baldrick Date: Wed Jun 8 09:06:18 2011 New Revision: 132747 URL: http://llvm.org/viewvc/llvm-project?rev=132747&view=rev Log: GCC sometimes generates shifts of vectors where the shift amount is a scalar. It seems to want all elements to be shifted by that scalar, so implement that. Modified: dragonegg/trunk/src/Convert.cpp Modified: dragonegg/trunk/src/Convert.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=132747&r1=132746&r2=132747&view=diff ============================================================================== --- dragonegg/trunk/src/Convert.cpp (original) +++ dragonegg/trunk/src/Convert.cpp Wed Jun 8 09:06:18 2011 @@ -6797,9 +6797,31 @@ Value *TreeToLLVM::EmitReg_ShiftOp(tree op0, tree op1, unsigned Opc) { Value *LHS = EmitRegister(op0); Value *RHS = EmitRegister(op1); - if (RHS->getType() != LHS->getType()) - RHS = CastToAnyType(RHS, /*isSigned*/false, LHS->getType(), - /*isSigned*/false); + // Ensure that the shift amount has the same type as the shiftee. + if (RHS->getType() != LHS->getType()) { + if (LHS->getType()->isVectorTy() == RHS->getType()->isVectorTy()) { + // Scalar shifted by a scalar amount, or a vector shifted by a vector + // amount. + assert((!LHS->getType()->isVectorTy() || + cast(LHS->getType())->getNumElements() == + cast(RHS->getType())->getNumElements()) && + "Vector length mismatch!"); + RHS = CastToAnyType(RHS, /*isSigned*/false, LHS->getType(), + /*isSigned*/false); + } else { + // Vector shifted by a scalar amount. Turn the shift amount into a vector + // with all elements equal. + assert(LHS->getType()->isVectorTy() && + "Shifting a scalar by a vector amount!"); + const VectorType *VecTy = cast(LHS->getType()); + RHS = CastToAnyType(RHS, /*isSigned*/false, VecTy->getElementType(), + /*isSigned*/false); + RHS = Builder.CreateInsertElement(UndefValue::get(VecTy), RHS, + Builder.getInt32(0)); + RHS = Builder.CreateShuffleVector(RHS, UndefValue::get(VecTy), + ConstantInt::get(VecTy, 0)); + } + } return Builder.CreateBinOp((Instruction::BinaryOps)Opc, LHS, RHS); } From rafael.espindola at gmail.com Wed Jun 8 07:13:31 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Wed, 08 Jun 2011 14:13:31 -0000 Subject: [llvm-commits] [llvm] r132748 - /llvm/trunk/lib/CodeGen/TailDuplication.cpp Message-ID: <20110608141331.B02A62A6C12C@llvm.org> Author: rafael Date: Wed Jun 8 09:13:31 2011 New Revision: 132748 URL: http://llvm.org/viewvc/llvm-project?rev=132748&view=rev Log: Count how many phis we are creating. Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=132748&r1=132747&r2=132748&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original) +++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Wed Jun 8 09:13:31 2011 @@ -34,6 +34,7 @@ STATISTIC(NumTailDups , "Number of tail duplicated blocks"); STATISTIC(NumInstrDups , "Additional instructions due to tail duplication"); STATISTIC(NumDeadBlocks, "Number of dead blocks removed"); +STATISTIC(NumAddedPHIs , "Number of phis added"); // Heuristic for tail duplication. static cl::opt @@ -246,6 +247,7 @@ } } + NumAddedPHIs += NewPHIs.size(); SSAUpdateVRs.clear(); SSAUpdateVals.clear(); } From rafael.espindola at gmail.com Wed Jun 8 07:23:19 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Wed, 08 Jun 2011 14:23:19 -0000 Subject: [llvm-commits] [llvm] r132749 - /llvm/trunk/lib/CodeGen/TailDuplication.cpp Message-ID: <20110608142319.DCBE92A6C12C@llvm.org> Author: rafael Date: Wed Jun 8 09:23:19 2011 New Revision: 132749 URL: http://llvm.org/viewvc/llvm-project?rev=132749&view=rev Log: Fix count. Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=132749&r1=132748&r2=132749&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original) +++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Wed Jun 8 09:23:19 2011 @@ -247,7 +247,6 @@ } } - NumAddedPHIs += NewPHIs.size(); SSAUpdateVRs.clear(); SSAUpdateVals.clear(); } @@ -273,6 +272,7 @@ MadeChange = true; } } + NumAddedPHIs += NewPHIs.size(); return MadeChange; } From atrick at apple.com Wed Jun 8 08:19:50 2011 From: atrick at apple.com (Andrew Trick) Date: Wed, 08 Jun 2011 15:19:50 -0000 Subject: [llvm-commits] [llvm] r132751 - /llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Message-ID: <20110608151950.129262A6C12C@llvm.org> Author: atrick Date: Wed Jun 8 10:19:49 2011 New Revision: 132751 URL: http://llvm.org/viewvc/llvm-project?rev=132751&view=rev Log: Remove a temporary test case probe in CheckForLiveRegDef. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=132751&r1=132750&r2=132751&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Wed Jun 8 10:19:49 2011 @@ -1015,7 +1015,6 @@ // Add Reg to the set of interfering live regs. if (RegAdded.insert(*AliasI)) { - assert(*AliasI == Reg && "alias clobber"); //!!! LRegs.push_back(*AliasI); } } From grosser at fim.uni-passau.de Wed Jun 8 10:36:11 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Wed, 08 Jun 2011 17:36:11 -0000 Subject: [llvm-commits] [polly] r132755 - /polly/trunk/www/experiments/matmul/.htaccess Message-ID: <20110608173611.B5A232A6C12C@llvm.org> Author: grosser Date: Wed Jun 8 12:36:11 2011 New Revision: 132755 URL: http://llvm.org/viewvc/llvm-project?rev=132755&view=rev Log: www: Allow file listing in directory of example files. Added: polly/trunk/www/experiments/matmul/.htaccess Added: polly/trunk/www/experiments/matmul/.htaccess URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/experiments/matmul/.htaccess?rev=132755&view=auto ============================================================================== --- polly/trunk/www/experiments/matmul/.htaccess (added) +++ polly/trunk/www/experiments/matmul/.htaccess Wed Jun 8 12:36:11 2011 @@ -0,0 +1 @@ +Options +Indexes From ahatanak at gmail.com Wed Jun 8 10:39:33 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Wed, 08 Jun 2011 17:39:33 -0000 Subject: [llvm-commits] [llvm] r132756 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Message-ID: <20110608173933.CEA9A2A6C12C@llvm.org> Author: ahatanak Date: Wed Jun 8 12:39:33 2011 New Revision: 132756 URL: http://llvm.org/viewvc/llvm-project?rev=132756&view=rev Log: Reorganize code in MipsTargetLowering::LowerCall to improve readability. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=132756&r1=132755&r2=132756&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Jun 8 12:39:33 2011 @@ -1760,20 +1760,41 @@ CCInfo.AnalyzeCallOperands(Outs, CC_Mips); // Get a count of how many bytes are to be pushed on the stack. - unsigned NumBytes = CCInfo.getNextStackOffset(); - Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); + unsigned NextStackOffset = CCInfo.getNextStackOffset(); - // With EABI is it possible to have 16 args on registers. - SmallVector, 16> RegsToPass; - SmallVector MemOpChains; + Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NextStackOffset, + true)); // If this is the first call, create a stack frame object that points to - // a location to which .cprestore saves $gp. The offset of this frame object - // is set to 0, since we know nothing about the size of the argument area at - // this point. + // a location to which .cprestore saves $gp. if (IsPIC && !MipsFI->getGPFI()) MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true)); + // Update size of the maximum argument space. + // For O32, a minimum of four words (16 bytes) of argument space is + // allocated. + if (Subtarget->isABI_O32()) + NextStackOffset = std::max(NextStackOffset, (unsigned)16); + + unsigned MaxCallFrameSize = MipsFI->getMaxCallFrameSize(); + + if (MaxCallFrameSize < NextStackOffset) { + MipsFI->setMaxCallFrameSize(NextStackOffset); + + if (IsPIC) { + // $gp restore slot must be aligned. + unsigned StackAlignment = TFL->getStackAlignment(); + NextStackOffset = (NextStackOffset + StackAlignment - 1) / + StackAlignment * StackAlignment; + int GPFI = MipsFI->getGPFI(); + MFI->setObjectOffset(GPFI, NextStackOffset); + } + } + + // With EABI is it possible to have 16 args on registers. + SmallVector, 16> RegsToPass; + SmallVector MemOpChains; + int FirstFI = -MFI->getNumFixedObjects() - 1, LastFI = 0; // Walk the register/memloc assignments, inserting copies/loads. @@ -1846,6 +1867,12 @@ false, false, 0)); } + // Extend range of indices of frame objects for outgoing arguments that were + // created during this function call. Skip this step if no such objects were + // created. + if (LastFI) + MipsFI->extendOutArgFIRange(FirstFI, LastFI); + // Transform all store nodes into one single node because all store // nodes are independent of each other. if (!MemOpChains.empty()) @@ -1937,37 +1964,8 @@ Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size()); InFlag = Chain.getValue(1); - // Function can have an arbitrary number of calls, so - // hold the LastArgStackLoc with the biggest offset. - unsigned MaxCallFrameSize = MipsFI->getMaxCallFrameSize(); - unsigned NextStackOffset = CCInfo.getNextStackOffset(); - - // For O32, a minimum of four words (16 bytes) of argument space is - // allocated. - if (Subtarget->isABI_O32()) - NextStackOffset = std::max(NextStackOffset, (unsigned)16); - - if (MaxCallFrameSize < NextStackOffset) { - MipsFI->setMaxCallFrameSize(NextStackOffset); - - if (IsPIC) { - // $gp restore slot must be aligned. - unsigned StackAlignment = TFL->getStackAlignment(); - NextStackOffset = (NextStackOffset + StackAlignment - 1) / - StackAlignment * StackAlignment; - int GPFI = MipsFI->getGPFI(); - MFI->setObjectOffset(GPFI, NextStackOffset); - } - } - - // Extend range of indices of frame objects for outgoing arguments that were - // created during this function call. Skip this step if no such objects were - // created. - if (LastFI) - MipsFI->extendOutArgFIRange(FirstFI, LastFI); - // Create the CALLSEQ_END node. - Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), + Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NextStackOffset, true), DAG.getIntPtrConstant(0, true), InFlag); InFlag = Chain.getValue(1); From ahatanak at gmail.com Wed Jun 8 14:28:09 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Wed, 08 Jun 2011 21:28:09 -0000 Subject: [llvm-commits] [llvm] r132758 - in /llvm/trunk: lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsISelLowering.h lib/Target/Mips/MipsInstrInfo.td lib/Target/Mips/MipsMachineFunction.h lib/Target/Mips/MipsRegisterInfo.cpp test/CodeGen/Mips/alloca.ll Message-ID: <20110608212809.4AD492A6C12C@llvm.org> Author: ahatanak Date: Wed Jun 8 16:28:09 2011 New Revision: 132758 URL: http://llvm.org/viewvc/llvm-project?rev=132758&view=rev Log: Fix bug in lowering of DYNAMIC_STACKALLOC nodes. The correct offset of the dynamically allocated stack area was not set. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.h llvm/trunk/lib/Target/Mips/MipsInstrInfo.td llvm/trunk/lib/Target/Mips/MipsMachineFunction.h llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp llvm/trunk/test/CodeGen/Mips/alloca.ll Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=132758&r1=132757&r2=132758&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Jun 8 16:28:09 2011 @@ -59,6 +59,7 @@ case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; case MipsISD::WrapperPIC: return "MipsISD::WrapperPIC"; + case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; default: return NULL; } } @@ -1189,6 +1190,9 @@ SDValue MipsTargetLowering:: LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const { + MachineFunction &MF = DAG.getMachineFunction(); + MipsFunctionInfo *MipsFI = MF.getInfo(); + unsigned StackAlignment = getTargetMachine().getFrameLowering()->getStackAlignment(); assert(StackAlignment >= @@ -1211,24 +1215,14 @@ // must be placed in the stack pointer register. Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub, SDValue()); - // Retrieve updated $sp. There is a glue input to prevent instructions that - // clobber $sp from being inserted between copytoreg and copyfromreg. - SDValue NewSP = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32, - Chain.getValue(1)); - - // The stack space reserved by alloca is located right above the argument - // area. It is aligned on a boundary that is a multiple of StackAlignment. - MachineFunction &MF = DAG.getMachineFunction(); - MipsFunctionInfo *MipsFI = MF.getInfo(); - unsigned SPOffset = (MipsFI->getMaxCallFrameSize() + StackAlignment - 1) / - StackAlignment * StackAlignment; - SDValue AllocPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP, - DAG.getConstant(SPOffset, MVT::i32)); // This node always has two return values: a new stack pointer // value and a chain - SDValue Ops[2] = { AllocPtr, NewSP.getValue(1) }; - return DAG.getMergeValues(Ops, 2, dl); + SDVTList VTLs = DAG.getVTList(MVT::i32, MVT::Other); + SDValue Ptr = DAG.getFrameIndex(MipsFI->getDynAllocFI(), getPointerTy()); + SDValue Ops[] = { Chain, Ptr, Chain.getValue(1) }; + + return DAG.getNode(MipsISD::DynAlloc, dl, VTLs, Ops, 3); } SDValue MipsTargetLowering:: @@ -1770,6 +1764,10 @@ if (IsPIC && !MipsFI->getGPFI()) MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true)); + // Get the frame index of the stack frame object that points to the location + // of dynamically allocated area on the stack. + int DynAllocFI = MipsFI->getDynAllocFI(); + // Update size of the maximum argument space. // For O32, a minimum of four words (16 bytes) of argument space is // allocated. @@ -1781,14 +1779,17 @@ if (MaxCallFrameSize < NextStackOffset) { MipsFI->setMaxCallFrameSize(NextStackOffset); - if (IsPIC) { - // $gp restore slot must be aligned. - unsigned StackAlignment = TFL->getStackAlignment(); - NextStackOffset = (NextStackOffset + StackAlignment - 1) / - StackAlignment * StackAlignment; - int GPFI = MipsFI->getGPFI(); - MFI->setObjectOffset(GPFI, NextStackOffset); - } + // Set the offsets relative to $sp of the $gp restore slot and dynamically + // allocated stack space. These offsets must be aligned to a boundary + // determined by the stack alignment of the ABI. + unsigned StackAlignment = TFL->getStackAlignment(); + NextStackOffset = (NextStackOffset + StackAlignment - 1) / + StackAlignment * StackAlignment; + + if (IsPIC) + MFI->setObjectOffset(MipsFI->getGPFI(), NextStackOffset); + + MFI->setObjectOffset(DynAllocFI, NextStackOffset); } // With EABI is it possible to have 16 args on registers. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=132758&r1=132757&r2=132758&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Wed Jun 8 16:28:09 2011 @@ -79,7 +79,9 @@ BuildPairF64, ExtractElementF64, - WrapperPIC + WrapperPIC, + + DynAlloc }; } Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=132758&r1=132757&r2=132758&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Wed Jun 8 16:28:09 2011 @@ -39,6 +39,9 @@ def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; +def SDT_MipsDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, + SDTCisVT<1, iPTR>]>; + // Call def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, @@ -99,6 +102,10 @@ def MipsWrapperPIC : SDNode<"MipsISD::WrapperPIC", SDTIntUnaryOp>; +// Pointer to dynamically allocated stack area. +def MipsDynAlloc : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc, + [SDNPHasChain, SDNPInGlue]>; + //===----------------------------------------------------------------------===// // Mips Instruction Predicate Definitions. //===----------------------------------------------------------------------===// @@ -675,6 +682,12 @@ // can be matched. It's similar to Sparc LEA_ADDRi def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">; +// DynAlloc node points to dynamically allocated stack space. +// $sp is added to the list of implicitly used registers to prevent dead code +// elimination from removing instructions that modify $sp. +let Uses = [SP] in +def DynAlloc : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">; + // MADD*/MSUB* def MADD : MArithR<0, "madd", MipsMAdd, 1>; def MADDU : MArithR<1, "maddu", MipsMAddu, 1>; @@ -852,6 +865,9 @@ def : Pat<(setuge CPURegs:$lhs, immSExt16:$rhs), (XORi (SLTiu CPURegs:$lhs, immSExt16:$rhs), 1)>; +// select MipsDynAlloc +def : Pat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>; + //===----------------------------------------------------------------------===// // Floating Point Support //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/Mips/MipsMachineFunction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMachineFunction.h?rev=132758&r1=132757&r2=132758&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsMachineFunction.h (original) +++ llvm/trunk/lib/Target/Mips/MipsMachineFunction.h Wed Jun 8 16:28:09 2011 @@ -27,6 +27,7 @@ class MipsFunctionInfo : public MachineFunctionInfo { private: + MachineFunction& MF; /// SRetReturnReg - Some subtargets require that sret lowering includes /// returning the value of the returned struct in a register. This field /// holds the virtual register into which the sret argument is passed. @@ -47,6 +48,7 @@ // LowerCall except for the frame object for restoring $gp. std::pair InArgFIRange, OutArgFIRange; int GPFI; // Index of the frame object for restoring $gp + mutable int DynAllocFI; // Frame index of dynamically allocated stack area. unsigned MaxCallFrameSize; /// AtomicFrameIndex - To implement atomic.swap and atomic.cmp.swap @@ -55,10 +57,10 @@ int AtomicFrameIndex; public: MipsFunctionInfo(MachineFunction& MF) - : SRetReturnReg(0), GlobalBaseReg(0), + : MF(MF), SRetReturnReg(0), GlobalBaseReg(0), VarArgsFrameIndex(0), InArgFIRange(std::make_pair(-1, 0)), - OutArgFIRange(std::make_pair(-1, 0)), GPFI(0), MaxCallFrameSize(0), - AtomicFrameIndex(-1) + OutArgFIRange(std::make_pair(-1, 0)), GPFI(0), DynAllocFI(0), + MaxCallFrameSize(0), AtomicFrameIndex(-1) {} bool isInArgFI(int FI) const { @@ -81,6 +83,16 @@ bool needGPSaveRestore() const { return getGPFI(); } bool isGPFI(int FI) const { return GPFI && GPFI == FI; } + // The first call to this function creates a frame object for dynamically + // allocated stack area. + int getDynAllocFI() const { + if (!DynAllocFI) + DynAllocFI = MF.getFrameInfo()->CreateFixedObject(4, 0, true); + + return DynAllocFI; + } + bool isDynAllocFI(int FI) const { return DynAllocFI && DynAllocFI == FI; } + unsigned getSRetReturnReg() const { return SRetReturnReg; } void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=132758&r1=132757&r2=132758&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Wed Jun 8 16:28:09 2011 @@ -177,12 +177,14 @@ int Offset; // Calculate final offset. - // - There is no need to change the offset if the frame object is an outgoing - // argument or a $gp restore location, + // - There is no need to change the offset if the frame object is one of the + // following: an outgoing argument, pointer to a dynamically allocated + // stack space or a $gp restore location, // - If the frame object is any of the following, its offset must be adjusted // by adding the size of the stack: // incoming argument, callee-saved register location or local variable. - if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isGPFI(FrameIndex)) + if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isGPFI(FrameIndex) || + MipsFI->isDynAllocFI(FrameIndex)) Offset = spOffset; else Offset = spOffset + stackSize; @@ -211,7 +213,7 @@ // 3. Locations for callee-saved registers. // Everything else is referenced relative to whatever register // getFrameRegister() returns. - if (MipsFI->isOutArgFI(FrameIndex) || + if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isDynAllocFI(FrameIndex) || (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI)) FrameReg = Mips::SP; else Modified: llvm/trunk/test/CodeGen/Mips/alloca.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/alloca.ll?rev=132758&r1=132757&r2=132758&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/alloca.ll (original) +++ llvm/trunk/test/CodeGen/Mips/alloca.ll Wed Jun 8 16:28:09 2011 @@ -4,15 +4,15 @@ entry: ; CHECK: subu $[[T0:[0-9]+]], $sp, $[[SZ:[0-9]+]] ; CHECK: addu $sp, $zero, $[[T0]] -; CHECK: addu $[[SP1:[0-9]+]], $zero, $sp -; CHECK: subu $[[T1:[0-9]+]], $sp, $[[SZ]] -; CHECK: addu $sp, $zero, $[[T1]] -; CHECK: addu $[[SP2:[0-9]+]], $zero, $sp +; CHECK: addiu $[[T1:[0-9]+]], $sp, [[OFF:[0-9]+]] +; CHECK: subu $[[T2:[0-9]+]], $sp, $[[SZ]] +; CHECK: addu $sp, $zero, $[[T2]] +; CHECK: addiu $[[T3:[0-9]+]], $sp, [[OFF]] ; CHECK: lw $25, %call16(foo)($gp) -; CHECK: addiu $4, $[[SP1]], 24 +; CHECK: addu $4, $zero, $[[T1]] ; CHECK: jalr $25 ; CHECK: lw $25, %call16(foo)($gp) -; CHECK: addiu $4, $[[SP2]], 24 +; CHECK: addu $4, $zero, $[[T3]] ; CHECK: jalr $25 %tmp1 = alloca i8, i32 %size, align 4 %add.ptr = getelementptr inbounds i8* %tmp1, i32 5 @@ -29,3 +29,72 @@ declare i32 @foo(i8*) + at .str = private unnamed_addr constant [22 x i8] c"%d %d %d %d %d %d %d\0A\00", align 1 + +define i32 @alloca2(i32 %size) nounwind { +entry: +; dynamic allocated stack area and $gp restore slot have the same offsets +; relative to $sp. +; +; CHECK: alloca2 +; CHECK: .cprestore [[OFF:[0-9]+]] +; CHECK: subu $[[T0:[0-9]+]], $sp, $[[SZ:[0-9]+]] +; CHECK: addu $sp, $zero, $[[T0]] +; CHECK: addiu $[[T1:[0-9]+]], $sp, [[OFF]] + + %tmp1 = alloca i8, i32 %size, align 4 + %0 = bitcast i8* %tmp1 to i32* + %cmp = icmp sgt i32 %size, 10 + br i1 %cmp, label %if.then, label %if.else + +if.then: ; preds = %entry +; CHECK: addiu $4, $[[T1]], 40 + + %add.ptr = getelementptr inbounds i8* %tmp1, i32 40 + %1 = bitcast i8* %add.ptr to i32* + call void @foo3(i32* %1) nounwind + %arrayidx15.pre = getelementptr inbounds i8* %tmp1, i32 12 + %.pre = bitcast i8* %arrayidx15.pre to i32* + br label %if.end + +if.else: ; preds = %entry +; CHECK: addiu $4, $[[T1]], 12 + + %add.ptr5 = getelementptr inbounds i8* %tmp1, i32 12 + %2 = bitcast i8* %add.ptr5 to i32* + call void @foo3(i32* %2) nounwind + br label %if.end + +if.end: ; preds = %if.else, %if.then +; CHECK: lw $5, 0($[[T1]]) +; CHECK: lw $25, %call16(printf) + + %.pre-phi = phi i32* [ %2, %if.else ], [ %.pre, %if.then ] + %tmp7 = load i32* %0, align 4, !tbaa !0 + %arrayidx9 = getelementptr inbounds i8* %tmp1, i32 4 + %3 = bitcast i8* %arrayidx9 to i32* + %tmp10 = load i32* %3, align 4, !tbaa !0 + %arrayidx12 = getelementptr inbounds i8* %tmp1, i32 8 + %4 = bitcast i8* %arrayidx12 to i32* + %tmp13 = load i32* %4, align 4, !tbaa !0 + %tmp16 = load i32* %.pre-phi, align 4, !tbaa !0 + %arrayidx18 = getelementptr inbounds i8* %tmp1, i32 16 + %5 = bitcast i8* %arrayidx18 to i32* + %tmp19 = load i32* %5, align 4, !tbaa !0 + %arrayidx21 = getelementptr inbounds i8* %tmp1, i32 20 + %6 = bitcast i8* %arrayidx21 to i32* + %tmp22 = load i32* %6, align 4, !tbaa !0 + %arrayidx24 = getelementptr inbounds i8* %tmp1, i32 24 + %7 = bitcast i8* %arrayidx24 to i32* + %tmp25 = load i32* %7, align 4, !tbaa !0 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([22 x i8]* @.str, i32 0, i32 0), i32 %tmp7, i32 %tmp10, i32 %tmp13, i32 %tmp16, i32 %tmp19, i32 %tmp22, i32 %tmp25) nounwind + ret i32 0 +} + +declare void @foo3(i32*) + +declare i32 @printf(i8* nocapture, ...) nounwind + +!0 = metadata !{metadata !"int", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA", null} From zwarich at apple.com Wed Jun 8 15:08:31 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Wed, 08 Jun 2011 22:08:31 -0000 Subject: [llvm-commits] [llvm] r132759 - in /llvm/trunk: lib/Transforms/Scalar/ScalarReplAggregates.cpp test/Transforms/ScalarRepl/2011-06-08-VectorExtractValue.ll Message-ID: <20110608220831.688BC2A6C12C@llvm.org> Author: zwarich Date: Wed Jun 8 17:08:31 2011 New Revision: 132759 URL: http://llvm.org/viewvc/llvm-project?rev=132759&view=rev Log: Fix an assymmetry between ConvertScalar_ExtractValue and ConvertScalar_InsertValue. The former was using the size of the entire alloca, whereas the latter was correctly using the allocated size of the immediate type being converted (which may differ from the size of the alloca). This fixes PR10082. Added: llvm/trunk/test/Transforms/ScalarRepl/2011-06-08-VectorExtractValue.ll Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=132759&r1=132758&r2=132759&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Wed Jun 8 17:08:31 2011 @@ -742,8 +742,9 @@ // If the result alloca is a vector type, this is either an element // access or a bitcast to another vector type of the same size. if (const VectorType *VTy = dyn_cast(FromType)) { + unsigned FromTypeSize = TD.getTypeAllocSize(FromType); unsigned ToTypeSize = TD.getTypeAllocSize(ToType); - if (ToTypeSize == AllocaSize) { + if (FromTypeSize == ToTypeSize) { // If the two types have the same primitive size, use a bit cast. // Otherwise, it is two vectors with the same element type that has // the same allocation size but different number of elements so use @@ -755,13 +756,13 @@ return CreateShuffleVectorCast(FromVal, ToType, Builder); } - if (isPowerOf2_64(AllocaSize / ToTypeSize)) { + if (isPowerOf2_64(FromTypeSize / ToTypeSize)) { assert(!(ToType->isVectorTy() && Offset != 0) && "Can't extract a value " "of a smaller vector type at a nonzero offset."); const Type *CastElementTy = getScaledElementType(FromType, ToType, ToTypeSize * 8); - unsigned NumCastVectorElements = AllocaSize / ToTypeSize; + unsigned NumCastVectorElements = FromTypeSize / ToTypeSize; LLVMContext &Context = FromVal->getContext(); const Type *CastTy = VectorType::get(CastElementTy, Added: llvm/trunk/test/Transforms/ScalarRepl/2011-06-08-VectorExtractValue.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/2011-06-08-VectorExtractValue.ll?rev=132759&view=auto ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/2011-06-08-VectorExtractValue.ll (added) +++ llvm/trunk/test/Transforms/ScalarRepl/2011-06-08-VectorExtractValue.ll Wed Jun 8 17:08:31 2011 @@ -0,0 +1,60 @@ +; RUN: opt < %s -S -scalarrepl | FileCheck %s +; RUN: opt < %s -S -scalarrepl-ssa | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-macosx10.7.0" + +%0 = type { <2 x float>, float } +%struct.PointC3 = type { %struct.array } +%struct.Point_3 = type { %struct.PointC3 } +%struct.array = type { [3 x float], [4 x i8] } + +; CHECK: main +; CHECK-NOT: alloca +; CHECK: extractelement <2 x float> zeroinitializer + +define void @main() uwtable ssp { +entry: + %ref.tmp2 = alloca %0, align 16 + %tmpcast = bitcast %0* %ref.tmp2 to %struct.Point_3* + %0 = getelementptr %0* %ref.tmp2, i64 0, i32 0 + store <2 x float> zeroinitializer, <2 x float>* %0, align 16 + %1 = getelementptr inbounds %struct.Point_3* %tmpcast, i64 0, i32 0 + %base.i.i.i = getelementptr inbounds %struct.PointC3* %1, i64 0, i32 0 + %arrayidx.i.i.i.i = getelementptr inbounds %struct.array* %base.i.i.i, i64 0, i32 0, i64 0 + %tmp5.i.i = load float* %arrayidx.i.i.i.i, align 4 + ret void +} + +; CHECK: test1 +; CHECK-NOT: alloca +; CHECK: extractelement <2 x float> zeroinitializer + +define void @test1() uwtable ssp { +entry: + %ref.tmp2 = alloca {<2 x float>, float}, align 16 + %tmpcast = bitcast {<2 x float>, float}* %ref.tmp2 to float* + %0 = getelementptr {<2 x float>, float}* %ref.tmp2, i64 0, i32 0 + store <2 x float> zeroinitializer, <2 x float>* %0, align 16 + %tmp5.i.i = load float* %tmpcast, align 4 + ret void +} + +; CHECK: test2 +; CHECK-NOT: alloca +; CHECK: insertelement <2 x float> zeroinitializer +; CHECK: extractelement <2 x float> %tmp2 +; CHECK: extractelement <2 x float> %tmp2 + +define float @test2() uwtable ssp { +entry: + %ref.tmp2 = alloca {<2 x float>, float}, align 16 + %tmpcast = bitcast {<2 x float>, float}* %ref.tmp2 to float* + %tmpcast2 = getelementptr {<2 x float>, float}* %ref.tmp2, i64 0, i32 1 + %0 = getelementptr {<2 x float>, float}* %ref.tmp2, i64 0, i32 0 + store <2 x float> zeroinitializer, <2 x float>* %0, align 16 + store float 1.0, float* %tmpcast2, align 4 + %r1 = load float* %tmpcast, align 4 + %r2 = load float* %tmpcast2, align 4 + %r = fadd float %r1, %r2 + ret float %r +} From jake at waskett.org Wed Jun 8 13:33:10 2011 From: jake at waskett.org (Jake Waskett) Date: Wed, 08 Jun 2011 21:33:10 +0100 Subject: [llvm-commits] Tweaks to HowToUseJIT.cpp Message-ID: <1307565190.1989.14.camel@jake-desktop> Recently I've been developing some code that uses LLVM's JIT functionality. Quite late in the process, I discovered the IRBuilder class. My reaction was, "this is so much nicer! Why didn't I find out about this earlier?" That's the purpose of this patch: to make it easier to discover this simple API. It modifies the HowToUseJIT.cpp example file *only*. -------------- next part -------------- A non-text attachment was scrubbed... Name: jitexample.diff Type: text/x-patch Size: 2385 bytes Desc: not available URL: From grosser at fim.uni-passau.de Wed Jun 8 15:46:40 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Wed, 08 Jun 2011 22:46:40 -0000 Subject: [llvm-commits] [polly] r132761 - /polly/trunk/www/get_started.html Message-ID: <20110608224640.B81222A6C12C@llvm.org> Author: grosser Date: Wed Jun 8 17:46:40 2011 New Revision: 132761 URL: http://llvm.org/viewvc/llvm-project?rev=132761&view=rev Log: www: Fix path to git repository. Modified: polly/trunk/www/get_started.html Modified: polly/trunk/www/get_started.html URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/get_started.html?rev=132761&r1=132760&r2=132761&view=diff ============================================================================== --- polly/trunk/www/get_started.html (original) +++ polly/trunk/www/get_started.html Wed Jun 8 17:46:40 2011 @@ -91,7 +91,7 @@ export LLVM_SRC=`pwd`/llvm git clone http://llvm.org/git/llvm.git ${LLVM_SRC} cd ${LLVM_SRC}/tools -git clone git://repo.or.cz/polly.git +git clone http://llvm.org/git/polly.git From eli.friedman at gmail.com Wed Jun 8 15:58:16 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 8 Jun 2011 15:58:16 -0700 Subject: [llvm-commits] [llvm] r132759 - in /llvm/trunk: lib/Transforms/Scalar/ScalarReplAggregates.cpp test/Transforms/ScalarRepl/2011-06-08-VectorExtractValue.ll In-Reply-To: <20110608220831.688BC2A6C12C@llvm.org> References: <20110608220831.688BC2A6C12C@llvm.org> Message-ID: On Wed, Jun 8, 2011 at 3:08 PM, Cameron Zwarich wrote: > Author: zwarich > Date: Wed Jun  8 17:08:31 2011 > New Revision: 132759 > > URL: http://llvm.org/viewvc/llvm-project?rev=132759&view=rev > Log: > Fix an assymmetry between ConvertScalar_ExtractValue and ConvertScalar_InsertValue. The > former was using the size of the entire alloca, whereas the latter was correctly using > the allocated size of the immediate type being converted (which may differ from the size > of the alloca). This fixes PR10082. [...] > +define float @test2() uwtable ssp { > +entry: > +  %ref.tmp2 = alloca {<2 x float>, float}, align 16 > +  %tmpcast = bitcast {<2 x float>, float}* %ref.tmp2 to float* > +  %tmpcast2 = getelementptr {<2 x float>, float}* %ref.tmp2, i64 0, i32 1 > +  %0 = getelementptr {<2 x float>, float}* %ref.tmp2, i64 0, i32 0 > +  store <2 x float> zeroinitializer, <2 x float>* %0, align 16 > +  store float 1.0, float* %tmpcast2, align 4 > +  %r1 = load float* %tmpcast, align 4 > +  %r2 = load float* %tmpcast2, align 4 > +  %r = fadd float %r1, %r2 > +  ret float %r > +} I forgot to mention: the reason for including this test was to make sure it doesn't get miscompiled. And with your patch, it does get miscompiled... -Eli From zwarich at apple.com Wed Jun 8 16:10:38 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Wed, 08 Jun 2011 16:10:38 -0700 Subject: [llvm-commits] [llvm] r132759 - in /llvm/trunk: lib/Transforms/Scalar/ScalarReplAggregates.cpp test/Transforms/ScalarRepl/2011-06-08-VectorExtractValue.ll In-Reply-To: References: <20110608220831.688BC2A6C12C@llvm.org> Message-ID: <90922843-F051-41B5-9CED-8EF3610A739C@apple.com> On Jun 8, 2011, at 3:58 PM, Eli Friedman wrote: > On Wed, Jun 8, 2011 at 3:08 PM, Cameron Zwarich wrote: >> Author: zwarich >> Date: Wed Jun 8 17:08:31 2011 >> New Revision: 132759 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=132759&view=rev >> Log: >> Fix an assymmetry between ConvertScalar_ExtractValue and ConvertScalar_InsertValue. The >> former was using the size of the entire alloca, whereas the latter was correctly using >> the allocated size of the immediate type being converted (which may differ from the size >> of the alloca). This fixes PR10082. > [...] >> +define float @test2() uwtable ssp { >> +entry: >> + %ref.tmp2 = alloca {<2 x float>, float}, align 16 >> + %tmpcast = bitcast {<2 x float>, float}* %ref.tmp2 to float* >> + %tmpcast2 = getelementptr {<2 x float>, float}* %ref.tmp2, i64 0, i32 1 >> + %0 = getelementptr {<2 x float>, float}* %ref.tmp2, i64 0, i32 0 >> + store <2 x float> zeroinitializer, <2 x float>* %0, align 16 >> + store float 1.0, float* %tmpcast2, align 4 >> + %r1 = load float* %tmpcast, align 4 >> + %r2 = load float* %tmpcast2, align 4 >> + %r = fadd float %r1, %r2 >> + ret float %r >> +} > > I forgot to mention: the reason for including this test was to make > sure it doesn't get miscompiled. And with your patch, it does get > miscompiled… I should have checked the output more carefully, but I thought it was just a crasher given the context of the bug. I'll take a look at it. The patch I landed is definitely fixing a real issue, though. Cameron From echristo at apple.com Wed Jun 8 16:55:35 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 08 Jun 2011 23:55:35 -0000 Subject: [llvm-commits] [llvm] r132763 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/ lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ lib/Target/XCore/ Message-ID: <20110608235536.B3E832A6C12C@llvm.org> Author: echristo Date: Wed Jun 8 18:55:35 2011 New Revision: 132763 URL: http://llvm.org/viewvc/llvm-project?rev=132763&view=rev Log: Add a parameter to CCState so that it can access the MachineFunction. No functional change. Part of PR6965 Modified: llvm/trunk/include/llvm/CodeGen/CallingConvLower.h llvm/trunk/include/llvm/Target/TargetLowering.h llvm/trunk/lib/CodeGen/CallingConvLower.cpp llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/Target/ARM/ARMFastISel.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp llvm/trunk/lib/Target/X86/X86FastISel.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp llvm/trunk/lib/Target/XCore/XCoreISelLowering.h Modified: llvm/trunk/include/llvm/CodeGen/CallingConvLower.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/CallingConvLower.h?rev=132763&r1=132762&r2=132763&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/CallingConvLower.h (original) +++ llvm/trunk/include/llvm/CodeGen/CallingConvLower.h Wed Jun 8 18:55:35 2011 @@ -16,6 +16,7 @@ #define LLVM_CODEGEN_CALLINGCONVLOWER_H #include "llvm/ADT/SmallVector.h" +#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/ValueTypes.h" #include "llvm/Target/TargetCallingConv.h" #include "llvm/CallingConv.h" @@ -149,6 +150,7 @@ class CCState { CallingConv::ID CallingConv; bool IsVarArg; + MachineFunction &MF; const TargetMachine &TM; const TargetRegisterInfo &TRI; SmallVector &Locs; @@ -160,7 +162,8 @@ bool FirstByValRegValid; ParmContext CallOrPrologue; public: - CCState(CallingConv::ID CC, bool isVarArg, const TargetMachine &TM, + CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF, + const TargetMachine &TM, SmallVector &locs, LLVMContext &C); void addLoc(const CCValAssign &V) { @@ -169,6 +172,7 @@ LLVMContext &getContext() const { return Context; } const TargetMachine &getTarget() const { return TM; } + MachineFunction &getMachineFunction() const { return MF; } CallingConv::ID getCallingConv() const { return CallingConv; } bool isVarArg() const { return IsVarArg; } Modified: llvm/trunk/include/llvm/Target/TargetLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=132763&r1=132762&r2=132763&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetLowering.h Wed Jun 8 18:55:35 2011 @@ -254,7 +254,7 @@ /// to get to the smaller register. For illegal floating point types, this /// returns the integer type to transform to. EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const { - return getTypeConversion(Context, VT).second; + return getTypeConversion(Context, VT).second; } /// getTypeToExpandTo - For types supported by the target, this is an @@ -1211,7 +1211,8 @@ /// return values described by the Outs array can fit into the return /// registers. If false is returned, an sret-demotion is performed. /// - virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, + virtual bool CanLowerReturn(CallingConv::ID CallConv, + MachineFunction &MF, bool isVarArg, const SmallVectorImpl &Outs, LLVMContext &Context) const { Modified: llvm/trunk/lib/CodeGen/CallingConvLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CallingConvLower.cpp?rev=132763&r1=132762&r2=132763&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CallingConvLower.cpp (original) +++ llvm/trunk/lib/CodeGen/CallingConvLower.cpp Wed Jun 8 18:55:35 2011 @@ -13,6 +13,7 @@ //===----------------------------------------------------------------------===// #include "llvm/CodeGen/CallingConvLower.h" +#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" @@ -22,21 +23,22 @@ #include "llvm/Target/TargetLowering.h" using namespace llvm; -CCState::CCState(CallingConv::ID CC, bool isVarArg, const TargetMachine &tm, +CCState::CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &mf, + const TargetMachine &tm, SmallVector &locs, LLVMContext &C) - : CallingConv(CC), IsVarArg(isVarArg), TM(tm), + : CallingConv(CC), IsVarArg(isVarArg), MF(mf), TM(tm), TRI(*TM.getRegisterInfo()), Locs(locs), Context(C), CallOrPrologue(Invalid) { // No stack is used. StackOffset = 0; - + clearFirstByValReg(); UsedRegs.resize((TRI.getNumRegs()+31)/32); } -// HandleByVal - Allocate a stack slot large enough to pass an argument by -// value. The size and alignment information of the argument is encoded in its -// parameter attribute. +// HandleByVal - Allocate space on the stack large enough to pass an argument +// by value. The size and alignment information of the argument is encoded in +// its parameter attribute. void CCState::HandleByVal(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, int MinSize, int MinAlign, Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp?rev=132763&r1=132762&r2=132763&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp Wed Jun 8 18:55:35 2011 @@ -67,7 +67,8 @@ SmallVector Outs; GetReturnInfo(Fn->getReturnType(), Fn->getAttributes().getRetAttributes(), Outs, TLI); - CanLowerReturn = TLI.CanLowerReturn(Fn->getCallingConv(), Fn->isVarArg(), + CanLowerReturn = TLI.CanLowerReturn(Fn->getCallingConv(), *MF, + Fn->isVarArg(), Outs, Fn->getContext()); // Initialize the mapping of values to registers. This is only set up for @@ -321,7 +322,7 @@ APInt Zero(BitWidth, 0); DestLOI.KnownZero = Zero; DestLOI.KnownOne = Zero; - return; + return; } if (ConstantInt *CI = dyn_cast(V)) { @@ -353,18 +354,18 @@ /// setByValArgumentFrameIndex - Record frame index for the byval /// argument. This overrides previous frame index entry for this argument, /// if any. -void FunctionLoweringInfo::setByValArgumentFrameIndex(const Argument *A, +void FunctionLoweringInfo::setByValArgumentFrameIndex(const Argument *A, int FI) { assert (A->hasByValAttr() && "Argument does not have byval attribute!"); ByValArgFrameIndexMap[A] = FI; } - + /// getByValArgumentFrameIndex - Get frame index for the byval argument. /// If the argument does not have any assigned frame index then 0 is /// returned. int FunctionLoweringInfo::getByValArgumentFrameIndex(const Argument *A) { assert (A->hasByValAttr() && "Argument does not have byval attribute!"); - DenseMap::iterator I = + DenseMap::iterator I = ByValArgFrameIndexMap.find(A); if (I != ByValArgFrameIndexMap.end()) return I->second; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=132763&r1=132762&r2=132763&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Jun 8 18:55:35 2011 @@ -303,7 +303,7 @@ return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, &NewOps[0], NewOps.size()); } - + // Trivial bitcast if the types are the same size and the destination // vector type is legal. if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() && @@ -4884,7 +4884,9 @@ Outs, TLI, &Offsets); bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), - FTy->isVarArg(), Outs, FTy->getContext()); + DAG.getMachineFunction(), + FTy->isVarArg(), Outs, + FTy->getContext()); SDValue DemoteStackSlot; int DemoteStackIdx = -100; @@ -5777,7 +5779,7 @@ // the addressing mode that the constraint wants. Also, this may take // an additional register for the computation and we don't want that // either. - + // If the operand is a float, integer, or vector constant, spill to a // constant pool entry to get its address. const Value *OpVal = OpInfo.CallOperandVal; Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=132763&r1=132762&r2=132763&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Jun 8 18:55:35 2011 @@ -443,14 +443,14 @@ uint64_t Imm1, uint64_t Imm2) { unsigned ResultReg = createResultReg(RC); const TargetInstrDesc &II = TII.get(MachineInstOpcode); - + if (II.getNumDefs() >= 1) AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) .addImm(Imm1).addImm(Imm2)); else { AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) .addImm(Imm1).addImm(Imm2)); - AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), ResultReg) .addReg(II.ImplicitDefs[0])); @@ -1542,7 +1542,7 @@ CallingConv::ID CC, unsigned &NumBytes) { SmallVector ArgLocs; - CCState CCInfo(CC, false, TM, ArgLocs, *Context); + CCState CCInfo(CC, false, *FuncInfo.MF, TM, ArgLocs, *Context); CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false)); // Get a count of how many bytes are to be pushed on the stack. @@ -1655,7 +1655,7 @@ // Now the return value. if (RetVT != MVT::isVoid) { SmallVector RVLocs; - CCState CCInfo(CC, false, TM, RVLocs, *Context); + CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context); CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true)); // Copy all of the result registers out of their specified physreg. @@ -1711,7 +1711,7 @@ // Analyze operands of the call, assigning locations to each operand. SmallVector ValLocs; - CCState CCInfo(CC, F.isVarArg(), TM, ValLocs, I->getContext()); + CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs, I->getContext()); CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */)); const Value *RV = Ret->getOperand(0); @@ -1990,7 +1990,7 @@ // any code. UpdateValueMap(I, SrcReg); return true; - } + } if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8) return false; Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=132763&r1=132762&r2=132763&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Jun 8 18:55:35 2011 @@ -1071,8 +1071,8 @@ // Assign locations to each value returned by this call. SmallVector RVLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), - RVLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), RVLocs, *DAG.getContext()); CCInfo.AnalyzeCallResult(Ins, CCAssignFnForNode(CallConv, /* Return*/ true, isVarArg)); @@ -1206,8 +1206,8 @@ // Analyze operands of the call, assigning locations to each operand. SmallVector ArgLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, - *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), ArgLocs, *DAG.getContext()); CCInfo.setCallOrPrologue(Call); CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv, /* Return*/ false, @@ -1638,13 +1638,13 @@ // results are returned in the same way as what the caller expects. if (!CCMatch) { SmallVector RVLocs1; - CCState CCInfo1(CalleeCC, false, getTargetMachine(), - RVLocs1, *DAG.getContext()); + CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), + getTargetMachine(), RVLocs1, *DAG.getContext()); CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg)); SmallVector RVLocs2; - CCState CCInfo2(CallerCC, false, getTargetMachine(), - RVLocs2, *DAG.getContext()); + CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), + getTargetMachine(), RVLocs2, *DAG.getContext()); CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg)); if (RVLocs1.size() != RVLocs2.size()) @@ -1670,8 +1670,8 @@ // Check if stack adjustment is needed. For now, do not do this if any // argument is passed on the stack. SmallVector ArgLocs; - CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(), - ArgLocs, *DAG.getContext()); + CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), ArgLocs, *DAG.getContext()); CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC, false, isVarArg)); if (CCInfo.getNextStackOffset()) { @@ -1730,8 +1730,8 @@ SmallVector RVLocs; // CCState - Info about the registers and stack slots. - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs, - *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), RVLocs, *DAG.getContext()); // Analyze outgoing return values. CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true, @@ -2424,8 +2424,8 @@ // Assign locations to all of the incoming arguments. SmallVector ArgLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, - *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), ArgLocs, *DAG.getContext()); CCInfo.setCallOrPrologue(Prologue); CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv, /* Return*/ false, @@ -2524,7 +2524,7 @@ if (index != lastInsIndex) { ISD::ArgFlagsTy Flags = Ins[index].Flags; - // FIXME: For now, all byval parameter objects are marked mutable. + // FIXME: For now, all byval parameter objects are marked mutable. // This can be changed with more analysis. // In case of tail call optimization mark all arguments mutable. // Since they could be overwritten by lowering of arguments in case of @@ -7386,7 +7386,7 @@ // Currently only support length 1 constraints. if (Constraint.length() != 1) return; - + char ConstraintLetter = Constraint[0]; switch (ConstraintLetter) { default: break; Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=132763&r1=132762&r2=132763&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Wed Jun 8 18:55:35 2011 @@ -230,8 +230,8 @@ // Analyze operands of the call, assigning locations to each operand. SmallVector ArgLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), - ArgLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), ArgLocs, *DAG.getContext()); CCInfo.AnalyzeCallOperands(Outs, CC_Alpha); @@ -344,8 +344,8 @@ // Assign locations to each value returned by this call. SmallVector RVLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs, - *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), RVLocs, *DAG.getContext()); CCInfo.AnalyzeCallResult(Ins, RetCC_Alpha); Modified: llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp?rev=132763&r1=132762&r2=132763&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp Wed Jun 8 18:55:35 2011 @@ -171,8 +171,8 @@ MachineFrameInfo *MFI = MF.getFrameInfo(); SmallVector ArgLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), - ArgLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), ArgLocs, *DAG.getContext()); CCInfo.AllocateStack(12, 4); // ABI requires 12 bytes stack space CCInfo.AnalyzeFormalArguments(Ins, CC_Blackfin); @@ -229,8 +229,8 @@ SmallVector RVLocs; // CCState - Info about the registers and stack slot. - CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), - RVLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + DAG.getTarget(), RVLocs, *DAG.getContext()); // Analize return values. CCInfo.AnalyzeReturn(Outs, RetCC_Blackfin); @@ -290,8 +290,8 @@ // Analyze operands of the call, assigning locations to each operand. SmallVector ArgLocs; - CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), ArgLocs, - *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + DAG.getTarget(), ArgLocs, *DAG.getContext()); CCInfo.AllocateStack(12, 4); // ABI requires 12 bytes stack space CCInfo.AnalyzeCallOperands(Outs, CC_Blackfin); @@ -378,8 +378,8 @@ // Assign locations to each value returned by this call. SmallVector RVLocs; - CCState RVInfo(CallConv, isVarArg, DAG.getTarget(), RVLocs, - *DAG.getContext()); + CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), + DAG.getTarget(), RVLocs, *DAG.getContext()); RVInfo.AnalyzeCallResult(Ins, RetCC_Blackfin); Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=132763&r1=132762&r2=132763&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Wed Jun 8 18:55:35 2011 @@ -1117,8 +1117,8 @@ EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); SmallVector ArgLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, - *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), ArgLocs, *DAG.getContext()); // FIXME: allow for other calling conventions CCInfo.AnalyzeFormalArguments(Ins, CCC_SPU); @@ -1264,8 +1264,8 @@ unsigned StackSlotSize = SPUFrameLowering::stackSlotSize(); SmallVector ArgLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, - *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), ArgLocs, *DAG.getContext()); // FIXME: allow for other calling conventions CCInfo.AnalyzeCallOperands(Outs, CCC_SPU); @@ -1425,8 +1425,8 @@ // Now handle the return value(s) SmallVector RVLocs; - CCState CCRetInfo(CallConv, isVarArg, getTargetMachine(), - RVLocs, *DAG.getContext()); + CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), RVLocs, *DAG.getContext()); CCRetInfo.AnalyzeCallResult(Ins, CCC_SPU); @@ -1452,8 +1452,8 @@ DebugLoc dl, SelectionDAG &DAG) const { SmallVector RVLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), - RVLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), RVLocs, *DAG.getContext()); CCInfo.AnalyzeReturn(Outs, RetCC_SPU); // If this is the first return lowered for this function, add the regs to the Modified: llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp?rev=132763&r1=132762&r2=132763&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp Wed Jun 8 18:55:35 2011 @@ -417,7 +417,7 @@ // All atomic instructions on the Microblaze are implemented using the // load-linked / store-conditional style atomic instruction sequences. // Thus, all operations will look something like the following: - // + // // start: // lwx RV, RP, 0 // @@ -698,8 +698,8 @@ // Analyze operands of the call, assigning locations to each operand. SmallVector ArgLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, - *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), ArgLocs, *DAG.getContext()); CCInfo.AnalyzeCallOperands(Outs, CC_MBlaze); // Get a count of how many bytes are to be pushed on the stack. @@ -837,8 +837,8 @@ SmallVectorImpl &InVals) const { // Assign locations to each value returned by this call. SmallVector RVLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), - RVLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), RVLocs, *DAG.getContext()); CCInfo.AnalyzeCallResult(Ins, RetCC_MBlaze); @@ -880,8 +880,8 @@ // Assign locations to all of the incoming arguments. SmallVector ArgLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), - ArgLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), ArgLocs, *DAG.getContext()); CCInfo.AnalyzeFormalArguments(Ins, CC_MBlaze); SDValue StackPtr; @@ -1012,8 +1012,8 @@ SmallVector RVLocs; // CCState - Info about the registers and stack slot. - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), - RVLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), RVLocs, *DAG.getContext()); // Analize return values. CCInfo.AnalyzeReturn(Outs, RetCC_MBlaze); @@ -1043,9 +1043,9 @@ // If this function is using the interrupt_handler calling convention // then use "rtid r14, 0" otherwise use "rtsd r15, 8" - unsigned Ret = (CallConv == llvm::CallingConv::MBLAZE_INTR) ? MBlazeISD::IRet + unsigned Ret = (CallConv == llvm::CallingConv::MBLAZE_INTR) ? MBlazeISD::IRet : MBlazeISD::Ret; - unsigned Reg = (CallConv == llvm::CallingConv::MBLAZE_INTR) ? MBlaze::R14 + unsigned Reg = (CallConv == llvm::CallingConv::MBLAZE_INTR) ? MBlaze::R14 : MBlaze::R15; SDValue DReg = DAG.getRegister(Reg, MVT::i32); Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp?rev=132763&r1=132762&r2=132763&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp Wed Jun 8 18:55:35 2011 @@ -312,8 +312,8 @@ // Assign locations to all of the incoming arguments. SmallVector ArgLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), - ArgLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), ArgLocs, *DAG.getContext()); CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430); assert(!isVarArg && "Varargs not supported yet"); @@ -395,8 +395,8 @@ } // CCState - Info about the registers and stack slot. - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), - RVLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), RVLocs, *DAG.getContext()); // Analize return values. CCInfo.AnalyzeReturn(Outs, RetCC_MSP430); @@ -449,8 +449,8 @@ SmallVectorImpl &InVals) const { // Analyze operands of the call, assigning locations to each operand. SmallVector ArgLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), - ArgLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), ArgLocs, *DAG.getContext()); CCInfo.AnalyzeCallOperands(Outs, CC_MSP430); @@ -572,8 +572,8 @@ // Assign locations to each value returned by this call. SmallVector RVLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), - RVLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), RVLocs, *DAG.getContext()); CCInfo.AnalyzeCallResult(Ins, RetCC_MSP430); Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=132763&r1=132762&r2=132763&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Jun 8 18:55:35 2011 @@ -148,7 +148,7 @@ setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); - + setOperationAction(ISD::VAARG, MVT::Other, Expand); setOperationAction(ISD::VACOPY, MVT::Other, Expand); setOperationAction(ISD::VAEND, MVT::Other, Expand); @@ -720,7 +720,7 @@ // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) MachineBasicBlock * MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, - unsigned Size, unsigned BinOpcode, + unsigned Size, unsigned BinOpcode, bool Nand) const { assert(Size == 4 && "Unsupported size for EmitAtomicBinary."); @@ -1502,11 +1502,11 @@ } static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool isLittle) { - // FIXME: + // FIXME: // Use ext/ins instructions if target architecture is Mips32r2. // Eliminate redundant mfc1 and mtc1 instructions. unsigned LoIdx = 0, HiIdx = 1; - + if (!isLittle) std::swap(LoIdx, HiIdx); @@ -1707,7 +1707,7 @@ // copy remaining part of byval arg to stack. if (CurWord < LastWord) { - unsigned SizeInBytes = (LastWord - CurWord) * 4; + unsigned SizeInBytes = (LastWord - CurWord) * 4; SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, DAG.getConstant((CurWord - FirstWord) * 4, MVT::i32)); @@ -1745,8 +1745,8 @@ // Analyze operands of the call, assigning locations to each operand. SmallVector ArgLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, - *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), ArgLocs, *DAG.getContext()); if (Subtarget->isABI_O32()) CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32); @@ -1767,7 +1767,7 @@ // Get the frame index of the stack frame object that points to the location // of dynamically allocated area on the stack. int DynAllocFI = MipsFI->getDynAllocFI(); - + // Update size of the maximum argument space. // For O32, a minimum of four words (16 bytes) of argument space is // allocated. @@ -1781,14 +1781,14 @@ // Set the offsets relative to $sp of the $gp restore slot and dynamically // allocated stack space. These offsets must be aligned to a boundary - // determined by the stack alignment of the ABI. + // determined by the stack alignment of the ABI. unsigned StackAlignment = TFL->getStackAlignment(); - NextStackOffset = (NextStackOffset + StackAlignment - 1) / + NextStackOffset = (NextStackOffset + StackAlignment - 1) / StackAlignment * StackAlignment; if (IsPIC) MFI->setObjectOffset(MipsFI->getGPFI(), NextStackOffset); - + MFI->setObjectOffset(DynAllocFI, NextStackOffset); } @@ -1796,7 +1796,7 @@ SmallVector, 16> RegsToPass; SmallVector MemOpChains; - int FirstFI = -MFI->getNumFixedObjects() - 1, LastFI = 0; + int FirstFI = -MFI->getNumFixedObjects() - 1, LastFI = 0; // Walk the register/memloc assignments, inserting copies/loads. for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { @@ -1844,7 +1844,7 @@ // Register can't get to this point... assert(VA.isMemLoc()); - // ByVal Arg. + // ByVal Arg. ISD::ArgFlagsTy Flags = Outs[i].Flags; if (Flags.isByVal()) { assert(Subtarget->isABI_O32() && @@ -1857,7 +1857,7 @@ } // Create the frame index object for this incoming parameter - LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, + LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, VA.getLocMemOffset(), true); SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy()); @@ -1924,7 +1924,7 @@ } else Callee = LoadValue; - // Use chain output from LoadValue + // Use chain output from LoadValue Chain = LoadValue.getValue(1); } @@ -1986,8 +1986,8 @@ SmallVectorImpl &InVals) const { // Assign locations to each value returned by this call. SmallVector RVLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), - RVLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), RVLocs, *DAG.getContext()); CCInfo.AnalyzeCallResult(Ins, RetCC_Mips); @@ -2051,8 +2051,8 @@ // Assign locations to all of the incoming arguments. SmallVector ArgLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), - ArgLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), ArgLocs, *DAG.getContext()); if (Subtarget->isABI_O32()) CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32); @@ -2165,7 +2165,7 @@ if (isVarArg && Subtarget->isABI_O32()) { // Record the frame index of the first variable argument - // which is a value necessary to VASTART. + // which is a value necessary to VASTART. unsigned NextStackOffset = CCInfo.getNextStackOffset(); assert(NextStackOffset % 4 == 0 && "NextStackOffset must be aligned to 4-byte boundaries."); @@ -2217,8 +2217,8 @@ SmallVector RVLocs; // CCState - Info about the registers and stack slot. - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), - RVLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), RVLocs, *DAG.getContext()); // Analize return values. CCInfo.AnalyzeReturn(Outs, RetCC_Mips); Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=132763&r1=132762&r2=132763&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Wed Jun 8 18:55:35 2011 @@ -1558,8 +1558,8 @@ // Assign locations to all of the incoming arguments. SmallVector ArgLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, - *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), ArgLocs, *DAG.getContext()); // Reserve space for the linkage area on the stack. CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize); @@ -1619,8 +1619,8 @@ // Aggregates passed by value are stored in the local variable space of the // caller's stack frame, right above the parameter list area. SmallVector ByValArgLocs; - CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(), - ByValArgLocs, *DAG.getContext()); + CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), ByValArgLocs, *DAG.getContext()); // Reserve stack space for the allocations in CCInfo. CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); @@ -2591,8 +2591,8 @@ SmallVectorImpl &InVals) const { SmallVector RVLocs; - CCState CCRetInfo(CallConv, isVarArg, getTargetMachine(), - RVLocs, *DAG.getContext()); + CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), RVLocs, *DAG.getContext()); CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC); // Copy all of the result registers out of their specified physreg. @@ -2641,8 +2641,8 @@ // to the liveout set for the function. if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { SmallVector RVLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs, - *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), RVLocs, *DAG.getContext()); CCInfo.AnalyzeCallResult(Ins, RetCC_PPC); for (unsigned i = 0; i != RVLocs.size(); ++i) DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); @@ -2755,8 +2755,8 @@ // Assign locations to all of the outgoing arguments. SmallVector ArgLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), - ArgLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), ArgLocs, *DAG.getContext()); // Reserve space for the linkage area on the stack. CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize); @@ -2795,8 +2795,8 @@ // Assign locations to all of the outgoing aggregate by value arguments. SmallVector ByValArgLocs; - CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(), ByValArgLocs, - *DAG.getContext()); + CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), ByValArgLocs, *DAG.getContext()); // Reserve stack space for the allocations in CCInfo. CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); @@ -3303,8 +3303,8 @@ DebugLoc dl, SelectionDAG &DAG) const { SmallVector RVLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), - RVLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), RVLocs, *DAG.getContext()); CCInfo.AnalyzeReturn(Outs, RetCC_PPC); // If this is the first return lowered for this function, add the regs to the @@ -5439,15 +5439,15 @@ /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops /// vector. If it is invalid, don't add anything to Ops. -void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, +void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector&Ops, SelectionDAG &DAG) const { SDValue Result(0,0); - + // Only support length 1 constraints. if (Constraint.length() > 1) return; - + char Letter = Constraint[0]; switch (Letter) { default: break; Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=132763&r1=132762&r2=132763&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Wed Jun 8 18:55:35 2011 @@ -91,8 +91,8 @@ SmallVector RVLocs; // CCState - Info about the registers and stack slot. - CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), - RVLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + DAG.getTarget(), RVLocs, *DAG.getContext()); // Analize return values. CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32); @@ -139,7 +139,7 @@ if (Flag.getNode()) return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, RetAddrOffsetNode, Flag); - return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, + return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, RetAddrOffsetNode); } @@ -161,8 +161,8 @@ // Assign locations to all of the incoming arguments. SmallVector ArgLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), - ArgLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), ArgLocs, *DAG.getContext()); CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32); const unsigned StackOffset = 92; @@ -360,8 +360,8 @@ // Analyze operands of the call, assigning locations to each operand. SmallVector ArgLocs; - CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), ArgLocs, - *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + DAG.getTarget(), ArgLocs, *DAG.getContext()); CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32); // Get the size of the outgoing arguments stack space requirement. @@ -591,8 +591,8 @@ // Assign locations to each value returned by this call. SmallVector RVLocs; - CCState RVInfo(CallConv, isVarArg, DAG.getTarget(), - RVLocs, *DAG.getContext()); + CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), + DAG.getTarget(), RVLocs, *DAG.getContext()); RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32); Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp?rev=132763&r1=132762&r2=132763&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp Wed Jun 8 18:55:35 2011 @@ -291,8 +291,8 @@ // Assign locations to all of the incoming arguments. SmallVector ArgLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), - ArgLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), ArgLocs, *DAG.getContext()); CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ); if (isVarArg) @@ -384,8 +384,8 @@ // Analyze operands of the call, assigning locations to each operand. SmallVector ArgLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), - ArgLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), ArgLocs, *DAG.getContext()); CCInfo.AnalyzeCallOperands(Outs, CC_SystemZ); @@ -513,8 +513,8 @@ // Assign locations to each value returned by this call. SmallVector RVLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs, - *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), RVLocs, *DAG.getContext()); CCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ); @@ -558,8 +558,8 @@ SmallVector RVLocs; // CCState - Info about the registers and stack slot. - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), - RVLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), RVLocs, *DAG.getContext()); // Analize return values. CCInfo.AnalyzeReturn(Outs, RetCC_SystemZ); Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=132763&r1=132762&r2=132763&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Wed Jun 8 18:55:35 2011 @@ -401,7 +401,7 @@ Disp += SL->getElementOffset(cast(Op)->getZExtValue()); continue; } - + // A array/variable index is always of the form i*S where S is the // constant scale size. See if we can push the scale into immediates. uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType()); @@ -469,7 +469,7 @@ if (const GlobalVariable *GVar = dyn_cast(GV)) if (GVar->isThreadLocal()) return false; - + // RIP-relative addresses can't have additional register operands, so if // we've already folded stuff into the addressing mode, just force the // global value into its own register, which we can use as the basereg. @@ -704,7 +704,8 @@ // Analyze operands of the call, assigning locations to each operand. SmallVector ValLocs; - CCState CCInfo(CC, F.isVarArg(), TM, ValLocs, I->getContext()); + CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs, + I->getContext()); CCInfo.AnalyzeReturn(Outs, RetCC_X86); const Value *RV = Ret->getOperand(0); @@ -936,7 +937,7 @@ bool X86FastISel::X86SelectZExt(const Instruction *I) { // Handle zero-extension from i1 to i8, which is common. - if (!I->getOperand(0)->getType()->isIntegerTy(1)) + if (!I->getOperand(0)->getType()->isIntegerTy(1)) return false; EVT DstVT = TLI.getValueType(I->getType()); @@ -1062,13 +1063,13 @@ if (OpReg == 0) return false; BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TestOpc)) .addReg(OpReg).addImm(1); - + unsigned JmpOpc = X86::JNE_4; if (FuncInfo.MBB->isLayoutSuccessor(TrueMBB)) { std::swap(TrueMBB, FalseMBB); JmpOpc = X86::JE_4; } - + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(JmpOpc)) .addMBB(TrueMBB); FastEmitBranch(FalseMBB, DL); @@ -1336,7 +1337,7 @@ return false; uint64_t Len = cast(MCI.getLength())->getZExtValue(); - + // Get the address of the dest and source addresses. X86AddressMode DestAM, SrcAM; if (!X86SelectAddress(MCI.getRawDest(), DestAM) || @@ -1345,7 +1346,7 @@ return TryEmitSmallMemcpy(DestAM, SrcAM, Len); } - + case Intrinsic::stackprotector: { // Emit code inline code to store the stack guard onto the stack. EVT PtrTy = TLI.getPointerTy(); @@ -1379,7 +1380,7 @@ case Intrinsic::sadd_with_overflow: case Intrinsic::uadd_with_overflow: { // FIXME: Should fold immediates. - + // Replace "add with overflow" intrinsics with an "add" instruction followed // by a seto/setc instruction. const Function *Callee = I.getCalledFunction(); @@ -1467,7 +1468,8 @@ GetReturnInfo(I->getType(), CS.getAttributes().getRetAttributes(), Outs, TLI, &Offsets); bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), - FTy->isVarArg(), Outs, FTy->getContext()); + *FuncInfo.MF, FTy->isVarArg(), + Outs, FTy->getContext()); if (!CanLowerReturn) return false; @@ -1535,9 +1537,9 @@ ArgVal = ConstantExpr::getZExt(CI,Type::getInt32Ty(CI->getContext())); } } - + unsigned ArgReg; - + // Passing bools around ends up doing a trunc to i1 and passing it. // Codegen this as an argument + "and 1". if (ArgVal->getType()->isIntegerTy(1) && isa(ArgVal) && @@ -1546,10 +1548,10 @@ ArgVal = cast(ArgVal)->getOperand(0); ArgReg = getRegForValue(ArgVal); if (ArgReg == 0) return false; - + MVT ArgVT; if (!isTypeLegal(ArgVal->getType(), ArgVT)) return false; - + ArgReg = FastEmit_ri(ArgVT, ArgVT, ISD::AND, ArgReg, ArgVal->hasOneUse(), 1); } else { @@ -1575,7 +1577,8 @@ // Analyze operands of the call, assigning locations to each operand. SmallVector ArgLocs; - CCState CCInfo(CC, isVarArg, TM, ArgLocs, I->getParent()->getContext()); + CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, ArgLocs, + I->getParent()->getContext()); // Allocate shadow area for Win64 if (Subtarget->isTargetWin64()) @@ -1790,7 +1793,8 @@ // Now handle call return values. SmallVector UsedRegs; SmallVector RVLocs; - CCState CCRetInfo(CC, false, TM, RVLocs, I->getParent()->getContext()); + CCState CCRetInfo(CC, false, *FuncInfo.MF, TM, RVLocs, + I->getParent()->getContext()); unsigned ResultReg = FuncInfo.CreateRegs(I->getType()); CCRetInfo.AnalyzeCallResult(Ins, RetCC_X86); for (unsigned i = 0; i != RVLocs.size(); ++i) { @@ -1946,7 +1950,7 @@ if (AM.BaseType == X86AddressMode::RegBase && AM.IndexReg == 0 && AM.Disp == 0 && AM.GV == 0) return AM.Base.Reg; - + Opc = TLI.getPointerTy() == MVT::i32 ? X86::LEA32r : X86::LEA64r; unsigned ResultReg = createResultReg(RC); addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=132763&r1=132762&r2=132763&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jun 8 18:55:35 2011 @@ -222,7 +222,7 @@ // X86 is weird, it always uses i8 for shift amounts and setcc results. setBooleanContents(ZeroOrOneBooleanContent); - + // For 64-bit since we have so many registers use the ILP scheduler, for // 32-bit code use the register pressure specific scheduling. if (Subtarget->is64Bit()) @@ -1320,11 +1320,12 @@ #include "X86GenCallingConv.inc" bool -X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, +X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, + MachineFunction &MF, bool isVarArg, const SmallVectorImpl &Outs, LLVMContext &Context) const { SmallVector RVLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), + CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context); return CCInfo.CheckReturn(Outs, RetCC_X86); } @@ -1339,7 +1340,7 @@ X86MachineFunctionInfo *FuncInfo = MF.getInfo(); SmallVector RVLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), + CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, *DAG.getContext()); CCInfo.AnalyzeReturn(Outs, RetCC_X86); @@ -1490,8 +1491,8 @@ // Assign locations to each value returned by this call. SmallVector RVLocs; bool Is64Bit = Subtarget->is64Bit(); - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), - RVLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), RVLocs, *DAG.getContext()); CCInfo.AnalyzeCallResult(Ins, RetCC_X86); // Copy all of the result registers out of their specified physreg. @@ -1680,7 +1681,7 @@ // Assign locations to all of the incoming arguments. SmallVector ArgLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), + CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), ArgLocs, *DAG.getContext()); // Allocate shadow area for Win64 @@ -2007,7 +2008,7 @@ // Analyze operands of the call, assigning locations to each operand. SmallVector ArgLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), + CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), ArgLocs, *DAG.getContext()); // Allocate shadow area for Win64 @@ -2545,8 +2546,8 @@ return false; SmallVector ArgLocs; - CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(), - ArgLocs, *DAG.getContext()); + CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), ArgLocs, *DAG.getContext()); CCInfo.AnalyzeCallOperands(Outs, CC_X86); for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) @@ -2566,8 +2567,8 @@ } if (Unused) { SmallVector RVLocs; - CCState CCInfo(CalleeCC, false, getTargetMachine(), - RVLocs, *DAG.getContext()); + CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), + getTargetMachine(), RVLocs, *DAG.getContext()); CCInfo.AnalyzeCallResult(Ins, RetCC_X86); for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { CCValAssign &VA = RVLocs[i]; @@ -2580,13 +2581,13 @@ // results are returned in the same way as what the caller expects. if (!CCMatch) { SmallVector RVLocs1; - CCState CCInfo1(CalleeCC, false, getTargetMachine(), - RVLocs1, *DAG.getContext()); + CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), + getTargetMachine(), RVLocs1, *DAG.getContext()); CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); SmallVector RVLocs2; - CCState CCInfo2(CallerCC, false, getTargetMachine(), - RVLocs2, *DAG.getContext()); + CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), + getTargetMachine(), RVLocs2, *DAG.getContext()); CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); if (RVLocs1.size() != RVLocs2.size()) @@ -2612,8 +2613,8 @@ // Check if stack adjustment is needed. For now, do not do this if any // argument is passed on the stack. SmallVector ArgLocs; - CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(), - ArgLocs, *DAG.getContext()); + CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), ArgLocs, *DAG.getContext()); // Allocate shadow area for Win64 if (Subtarget->isTargetWin64()) { @@ -12706,7 +12707,7 @@ // Only support length 1 constraints for now. if (Constraint.length() > 1) return; - + char ConstraintLetter = Constraint[0]; switch (ConstraintLetter) { default: break; Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=132763&r1=132762&r2=132763&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Wed Jun 8 18:55:35 2011 @@ -858,9 +858,10 @@ ISD::NodeType ExtendKind) const; virtual bool - CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, - const SmallVectorImpl &Outs, - LLVMContext &Context) const; + CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, + bool isVarArg, + const SmallVectorImpl &Outs, + LLVMContext &Context) const; void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl &Results, SelectionDAG &DAG, unsigned NewOp) const; Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=132763&r1=132762&r2=132763&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Wed Jun 8 18:55:35 2011 @@ -897,8 +897,8 @@ // Analyze operands of the call, assigning locations to each operand. SmallVector ArgLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), - ArgLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), ArgLocs, *DAG.getContext()); // The ABI dictates there should be one stack slot available to the callee // on function entry (for saving lr). @@ -1020,8 +1020,8 @@ // Assign locations to each value returned by this call. SmallVector RVLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), - RVLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), RVLocs, *DAG.getContext()); CCInfo.AnalyzeCallResult(Ins, RetCC_XCore); @@ -1080,8 +1080,8 @@ // Assign locations to all of the incoming arguments. SmallVector ArgLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), - ArgLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), ArgLocs, *DAG.getContext()); CCInfo.AnalyzeFormalArguments(Ins, CC_XCore); @@ -1185,12 +1185,12 @@ //===----------------------------------------------------------------------===// bool XCoreTargetLowering:: -CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, +CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, + bool isVarArg, const SmallVectorImpl &Outs, LLVMContext &Context) const { SmallVector RVLocs; - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), - RVLocs, Context); + CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context); return CCInfo.CheckReturn(Outs, RetCC_XCore); } @@ -1206,10 +1206,10 @@ SmallVector RVLocs; // CCState - Info about the registers and stack slot. - CCState CCInfo(CallConv, isVarArg, getTargetMachine(), - RVLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), RVLocs, *DAG.getContext()); - // Analize return values. + // Analyze return values. CCInfo.AnalyzeReturn(Outs, RetCC_XCore); // If this is the first return lowered for this function, add Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.h?rev=132763&r1=132762&r2=132763&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreISelLowering.h (original) +++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.h Wed Jun 8 18:55:35 2011 @@ -191,7 +191,8 @@ DebugLoc dl, SelectionDAG &DAG) const; virtual bool - CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, + CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, + bool isVarArg, const SmallVectorImpl &ArgsFlags, LLVMContext &Context) const; }; From echristo at apple.com Wed Jun 8 17:15:19 2011 From: echristo at apple.com (Eric Christopher) Date: Thu, 09 Jun 2011 00:15:19 -0000 Subject: [llvm-commits] [llvm] r132764 - in /llvm/trunk: lib/CodeGen/CallingConvLower.cpp test/CodeGen/X86/byval-align.ll Message-ID: <20110609001519.857642A6C12C@llvm.org> Author: echristo Date: Wed Jun 8 19:15:19 2011 New Revision: 132764 URL: http://llvm.org/viewvc/llvm-project?rev=132764&view=rev Log: If the alignment of the byval argument is greater than the alignment of the frame then increase the maximum alignment of the frame to match. Fixes PR6965 Added: llvm/trunk/test/CodeGen/X86/byval-align.ll Modified: llvm/trunk/lib/CodeGen/CallingConvLower.cpp Modified: llvm/trunk/lib/CodeGen/CallingConvLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CallingConvLower.cpp?rev=132764&r1=132763&r2=132764&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CallingConvLower.cpp (original) +++ llvm/trunk/lib/CodeGen/CallingConvLower.cpp Wed Jun 8 19:15:19 2011 @@ -49,6 +49,8 @@ Size = MinSize; if (MinAlign > (int)Align) Align = MinAlign; + if (MF.getFrameInfo()->getMaxAlignment() < Align) + MF.getFrameInfo()->setMaxAlignment(Align); TM.getTargetLowering()->HandleByVal(const_cast(this), Size); unsigned Offset = AllocateStack(Size, Align); addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); Added: llvm/trunk/test/CodeGen/X86/byval-align.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/byval-align.ll?rev=132764&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/byval-align.ll (added) +++ llvm/trunk/test/CodeGen/X86/byval-align.ll Wed Jun 8 19:15:19 2011 @@ -0,0 +1,59 @@ +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +%struct.S = type { i32} + + at .str = private constant [10 x i8] c"ptr = %p\0A\00", align 1 ; <[10 x i8]*> [#uses=1] + at .str1 = private constant [8 x i8] c"Failed \00", align 1 ; <[8 x i8]*> [#uses=1] + at .str2 = private constant [2 x i8] c"0\00", align 1 ; <[2 x i8]*> [#uses=1] + at .str3 = private constant [7 x i8] c"test.c\00", align 1 ; <[7 x i8]*> [#uses=1] + at __PRETTY_FUNCTION__.2067 = internal constant [13 x i8] c"aligned_func\00" ; <[13 x i8]*> [#uses=1] + +define void @aligned_func(%struct.S* byval align 64 %obj) nounwind { +entry: + %ptr = alloca i8* ; [#uses=3] + %p = alloca i64 ; [#uses=3] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + %obj1 = bitcast %struct.S* %obj to i8* ; [#uses=1] + store i8* %obj1, i8** %ptr, align 8 + %0 = load i8** %ptr, align 8 ; [#uses=1] + %1 = ptrtoint i8* %0 to i64 ; [#uses=1] + store i64 %1, i64* %p, align 8 + %2 = load i8** %ptr, align 8 ; [#uses=1] + %3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([10 x i8]* @.str, i64 0, i64 0), i8* %2) nounwind ; [#uses=0] + %4 = load i64* %p, align 8 ; [#uses=1] + %5 = and i64 %4, 140737488355264 ; [#uses=1] + %6 = load i64* %p, align 8 ; [#uses=1] + %7 = icmp ne i64 %5, %6 ; [#uses=1] + br i1 %7, label %bb, label %bb2 + +bb: ; preds = %entry + %8 = call i32 @puts(i8* getelementptr inbounds ([8 x i8]* @.str1, i64 0, i64 0)) nounwind ; [#uses=0] + call void @__assert_fail(i8* getelementptr inbounds ([2 x i8]* @.str2, i64 0, i64 0), i8* getelementptr inbounds ([7 x i8]* @.str3, i64 0, i64 0), i32 18, i8* getelementptr inbounds ([13 x i8]* @__PRETTY_FUNCTION__.2067, i64 0, i64 0)) noreturn nounwind + unreachable + +bb2: ; preds = %entry + br label %return + +return: ; preds = %bb2 + ret void +} + +declare i32 @printf(i8*, ...) nounwind + +declare i32 @puts(i8*) + +declare void @__assert_fail(i8*, i8*, i32, i8*) noreturn nounwind + +define void @main() nounwind { +entry: +; CHECK: main +; CHECK: andq $-64, %rsp + %s1 = alloca %struct.S ; <%struct.S*> [#uses=4] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + %0 = getelementptr inbounds %struct.S* %s1, i32 0, i32 0 ; [#uses=1] + store i32 1, i32* %0, align 4 + call void @aligned_func(%struct.S* byval align 64 %s1) nounwind + br label %return + +return: ; preds = %entry + ret void +} From zwarich at apple.com Wed Jun 8 18:45:33 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Thu, 09 Jun 2011 01:45:33 -0000 Subject: [llvm-commits] [llvm] r132766 - in /llvm/trunk: lib/Transforms/Scalar/ScalarReplAggregates.cpp test/Transforms/ScalarRepl/2011-06-08-VectorExtractValue.ll Message-ID: <20110609014533.F1B442A6C12C@llvm.org> Author: zwarich Date: Wed Jun 8 20:45:33 2011 New Revision: 132766 URL: http://llvm.org/viewvc/llvm-project?rev=132766&view=rev Log: Fix PR10104 by adding a bounds check on a vector element access check. It was assuming that all offsets are legal vector accesses, and thus trying to access the float member of { <2 x float>, float } as the 3rd element of the first member. Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp llvm/trunk/test/Transforms/ScalarRepl/2011-06-08-VectorExtractValue.ll Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=132766&r1=132765&r2=132766&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Wed Jun 8 20:45:33 2011 @@ -342,7 +342,10 @@ // If we're accessing something that could be an element of a vector, see // if the implied vector agrees with what we already have and if Offset is // compatible with it. - if (Offset % EltSize == 0 && AllocaSize % EltSize == 0) { + if (Offset % EltSize == 0 && AllocaSize % EltSize == 0 && + Offset * 8 < + (VectorTy ? VectorTy->getPrimitiveSizeInBits() + : (AllocaSize / EltSize) * In->getPrimitiveSizeInBits())) { if (!VectorTy) { VectorTy = VectorType::get(In, AllocaSize/EltSize); return; Modified: llvm/trunk/test/Transforms/ScalarRepl/2011-06-08-VectorExtractValue.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/2011-06-08-VectorExtractValue.ll?rev=132766&r1=132765&r2=132766&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/2011-06-08-VectorExtractValue.ll (original) +++ llvm/trunk/test/Transforms/ScalarRepl/2011-06-08-VectorExtractValue.ll Wed Jun 8 20:45:33 2011 @@ -41,9 +41,11 @@ ; CHECK: test2 ; CHECK-NOT: alloca -; CHECK: insertelement <2 x float> zeroinitializer -; CHECK: extractelement <2 x float> %tmp2 -; CHECK: extractelement <2 x float> %tmp2 +; CHECK: and i128 +; CHECK: or i128 +; CHECK: trunc i128 +; CHECK-NOT: insertelement +; CHECK-NOT: extractelement define float @test2() uwtable ssp { entry: From zwarich at apple.com Wed Jun 8 18:51:58 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Wed, 08 Jun 2011 18:51:58 -0700 Subject: [llvm-commits] [llvm] r132759 - in /llvm/trunk: lib/Transforms/Scalar/ScalarReplAggregates.cpp test/Transforms/ScalarRepl/2011-06-08-VectorExtractValue.ll In-Reply-To: References: <20110608220831.688BC2A6C12C@llvm.org> Message-ID: <84B014E4-2CB5-4E08-B91B-9AA0922ABD05@apple.com> On Jun 8, 2011, at 3:58 PM, Eli Friedman wrote: > On Wed, Jun 8, 2011 at 3:08 PM, Cameron Zwarich wrote: >> Author: zwarich >> Date: Wed Jun 8 17:08:31 2011 >> New Revision: 132759 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=132759&view=rev >> Log: >> Fix an assymmetry between ConvertScalar_ExtractValue and ConvertScalar_InsertValue. The >> former was using the size of the entire alloca, whereas the latter was correctly using >> the allocated size of the immediate type being converted (which may differ from the size >> of the alloca). This fixes PR10082. > [...] >> +define float @test2() uwtable ssp { >> +entry: >> + %ref.tmp2 = alloca {<2 x float>, float}, align 16 >> + %tmpcast = bitcast {<2 x float>, float}* %ref.tmp2 to float* >> + %tmpcast2 = getelementptr {<2 x float>, float}* %ref.tmp2, i64 0, i32 1 >> + %0 = getelementptr {<2 x float>, float}* %ref.tmp2, i64 0, i32 0 >> + store <2 x float> zeroinitializer, <2 x float>* %0, align 16 >> + store float 1.0, float* %tmpcast2, align 4 >> + %r1 = load float* %tmpcast, align 4 >> + %r2 = load float* %tmpcast2, align 4 >> + %r = fadd float %r1, %r2 >> + ret float %r >> +} > > I forgot to mention: the reason for including this test was to make > sure it doesn't get miscompiled. And with your patch, it does get > miscompiled... Fixed in r132766. Nice test case! Cameron From zwarich at apple.com Wed Jun 8 18:52:44 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Thu, 09 Jun 2011 01:52:44 -0000 Subject: [llvm-commits] [llvm] r132767 - /llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Message-ID: <20110609015244.E449B2A6C12C@llvm.org> Author: zwarich Date: Wed Jun 8 20:52:44 2011 New Revision: 132767 URL: http://llvm.org/viewvc/llvm-project?rev=132767&view=rev Log: Remove a vacuous condition. Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=132767&r1=132766&r2=132767&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Wed Jun 8 20:52:44 2011 @@ -343,9 +343,7 @@ // if the implied vector agrees with what we already have and if Offset is // compatible with it. if (Offset % EltSize == 0 && AllocaSize % EltSize == 0 && - Offset * 8 < - (VectorTy ? VectorTy->getPrimitiveSizeInBits() - : (AllocaSize / EltSize) * In->getPrimitiveSizeInBits())) { + (!VectorTy || Offset * 8 < VectorTy->getPrimitiveSizeInBits())) { if (!VectorTy) { VectorTy = VectorType::get(In, AllocaSize/EltSize); return; From ahatanak at gmail.com Wed Jun 8 20:31:05 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Thu, 09 Jun 2011 03:31:05 -0000 Subject: [llvm-commits] [llvm] r132768 - in /llvm/trunk: lib/Target/Mips/MipsAsmPrinter.cpp lib/Target/Mips/MipsISelDAGToDAG.cpp test/CodeGen/Mips/inlineasmmemop.ll Message-ID: <20110609033105.B60A82A6C12C@llvm.org> Author: ahatanak Date: Wed Jun 8 22:31:05 2011 New Revision: 132768 URL: http://llvm.org/viewvc/llvm-project?rev=132768&view=rev Log: Initial support for inline asm memory operand constraints. Added: llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=132768&r1=132767&r2=132768&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Wed Jun 8 22:31:05 2011 @@ -56,6 +56,9 @@ bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O); + bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, + unsigned AsmVariant, const char *ExtraCode, + raw_ostream &O); void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O); void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O); void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O, @@ -304,6 +307,19 @@ return false; } +bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, + unsigned OpNum, unsigned AsmVariant, + const char *ExtraCode, + raw_ostream &O) { + if (ExtraCode && ExtraCode[0]) + return true; // Unknown modifier. + + const MachineOperand &MO = MI->getOperand(OpNum); + assert(MO.isReg() && "unexpected inline asm memory operand"); + O << "0($" << MipsAsmPrinter::getRegisterName(MO.getReg()) << ")"; + return false; +} + void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum, raw_ostream &O) { const MachineOperand &MO = MI->getOperand(opNum); Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=132768&r1=132767&r2=132768&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Wed Jun 8 22:31:05 2011 @@ -94,6 +94,10 @@ inline SDValue getI32Imm(unsigned Imm) { return CurDAG->getTargetConstant(Imm, MVT::i32); } + + virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, + char ConstraintCode, + std::vector &OutOps); }; } @@ -462,6 +466,14 @@ return ResNode; } +bool MipsDAGToDAGISel:: +SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, + std::vector &OutOps) { + assert(ConstraintCode == 'm' && "unexpected asm memory constraint"); + OutOps.push_back(Op); + return false; +} + /// createMipsISelDag - This pass converts a legalized DAG into a /// MIPS-specific DAG, ready for instruction scheduling. FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) { Added: llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll?rev=132768&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll (added) +++ llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll Wed Jun 8 22:31:05 2011 @@ -0,0 +1,23 @@ +; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s + + at g1 = external global i32 + +define i32 @f1(i32 %x) nounwind { +entry: +; CHECK: addiu $[[T0:[0-9]+]], $sp +; CHECK: #APP +; CHECK: sw $4, 0($[[T0]]) +; CHECK: #NO_APP +; CHECK: lw $[[T1:[0-9]+]], %got(g1)($gp) +; CHECK: #APP +; CHECK: lw $[[T3:[0-9]+]], 0($[[T0]]) +; CHECK: #NO_APP +; CHECK: sw $[[T3]], 0($[[T1]]) + + %l1 = alloca i32, align 4 + call void asm "sw $1, $0", "=*m,r"(i32* %l1, i32 %x) nounwind + %0 = call i32 asm "lw $0, $1", "=r,*m"(i32* %l1) nounwind + store i32 %0, i32* @g1, align 4 + ret i32 %0 +} + From jstaszak at apple.com Wed Jun 8 20:39:54 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Wed, 08 Jun 2011 20:39:54 -0700 Subject: [llvm-commits] unsigned to uint32_t patch Message-ID: <2B6497C2-1D29-424C-AAA7-6681D540AD52@apple.com> Hi, This patch changes unsigned (int) to uint32_t in BranchProbabilityInfo. Andy: Can you commit this patch? Thanks! -Kuba -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: unsigned_to_uint32_t.patch Type: application/octet-stream Size: 7349 bytes Desc: not available URL: -------------- next part -------------- An HTML attachment was scrubbed... URL: From stoklund at 2pi.dk Wed Jun 8 21:04:22 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 8 Jun 2011 21:04:22 -0700 Subject: [llvm-commits] unsigned to uint32_t patch In-Reply-To: <2B6497C2-1D29-424C-AAA7-6681D540AD52@apple.com> References: <2B6497C2-1D29-424C-AAA7-6681D540AD52@apple.com> Message-ID: On Jun 8, 2011, at 8:39 PM, Jakub Staszak wrote: > Hi, > > This patch changes unsigned (int) to uint32_t in BranchProbabilityInfo. > Andy: Can you commit this patch? Remember to use UINT32_MAX instead of UINT_MAX. That's the important part ;-) /jakob From jstaszak at apple.com Wed Jun 8 21:16:04 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Wed, 08 Jun 2011 21:16:04 -0700 Subject: [llvm-commits] unsigned to uint32_t patch In-Reply-To: References: <2B6497C2-1D29-424C-AAA7-6681D540AD52@apple.com> Message-ID: Right :) Fixed patch attached. - Kuba On Jun 8, 2011, at 9:04 PM, Jakob Stoklund Olesen wrote: -------------- next part -------------- A non-text attachment was scrubbed... Name: unsigned_to_uint32_t.2.patch Type: application/octet-stream Size: 7556 bytes Desc: not available URL: -------------- next part -------------- > > On Jun 8, 2011, at 8:39 PM, Jakub Staszak wrote: > >> Hi, >> >> This patch changes unsigned (int) to uint32_t in BranchProbabilityInfo. >> Andy: Can you commit this patch? > > Remember to use UINT32_MAX instead of UINT_MAX. That's the important part ;-) > > /jakob > From echristo at apple.com Wed Jun 8 22:58:50 2011 From: echristo at apple.com (Eric Christopher) Date: Thu, 09 Jun 2011 05:58:50 -0000 Subject: [llvm-commits] [llvm] r132770 - /llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp Message-ID: <20110609055850.A455D2A6C12C@llvm.org> Author: echristo Date: Thu Jun 9 00:58:50 2011 New Revision: 132770 URL: http://llvm.org/viewvc/llvm-project?rev=132770&view=rev Log: Have the JIT tutorial use IRBuilder for the IR. Patch by Jake Waskett! Modified: llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp Modified: llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp?rev=132770&r1=132769&r2=132770&view=diff ============================================================================== --- llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp (original) +++ llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp Thu Jun 9 00:58:50 2011 @@ -45,6 +45,8 @@ #include "llvm/Target/TargetSelect.h" #include "llvm/Support/ManagedStatic.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/Support/IRBuilder.h" + using namespace llvm; int main() { @@ -68,8 +70,12 @@ // because of the last argument. BasicBlock *BB = BasicBlock::Create(Context, "EntryBlock", Add1F); + // Create a basic block builder with default parameters. The builder will + // automatically append instructions to the basic block `BB'. + IRBuilder<> builder(BB); + // Get pointers to the constant `1'. - Value *One = ConstantInt::get(Type::getInt32Ty(Context), 1); + Value *One = builder.getInt32(1); // Get pointers to the integer argument of the add1 function... assert(Add1F->arg_begin() != Add1F->arg_end()); // Make sure there's an arg @@ -77,10 +83,10 @@ ArgX->setName("AnArg"); // Give it a nice symbolic name for fun. // Create the add instruction, inserting it into the end of BB. - Instruction *Add = BinaryOperator::CreateAdd(One, ArgX, "addresult", BB); + Value *Add = builder.CreateAdd(One, ArgX); // Create the return instruction and add it to the basic block - ReturnInst::Create(Context, Add, BB); + builder.CreateRet(Add); // Now, function add1 is ready. @@ -94,15 +100,18 @@ // Add a basic block to the FooF function. BB = BasicBlock::Create(Context, "EntryBlock", FooF); - // Get pointers to the constant `10'. - Value *Ten = ConstantInt::get(Type::getInt32Ty(Context), 10); + // Tell the basic block builder to attach itself to the new basic block + builder.SetInsertPoint(BB); + + // Get pointer to the constant `10'. + Value *Ten = builder.getInt32(10); - // Pass Ten to the call call: - CallInst *Add1CallRes = CallInst::Create(Add1F, Ten, "add1", BB); + // Pass Ten to the call to Add1F + CallInst *Add1CallRes = builder.CreateCall(Add1F, Ten); Add1CallRes->setTailCall(true); // Create the return instruction and add it to the basic block. - ReturnInst::Create(Context, Add1CallRes, BB); + builder.CreateRet(Add1CallRes); // Now we create the JIT. ExecutionEngine* EE = EngineBuilder(M).create(); From echristo at apple.com Wed Jun 8 23:04:43 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 08 Jun 2011 23:04:43 -0700 Subject: [llvm-commits] Tweaks to HowToUseJIT.cpp In-Reply-To: <1307565190.1989.14.camel@jake-desktop> References: <1307565190.1989.14.camel@jake-desktop> Message-ID: <8DEC81E8-710B-407B-9F3A-9C0DB9BC58A8@apple.com> On Jun 8, 2011, at 1:33 PM, Jake Waskett wrote: > Recently I've been developing some code that uses LLVM's JIT > functionality. Quite late in the process, I discovered the IRBuilder > class. My reaction was, "this is so much nicer! Why didn't I find out > about this earlier?" > > That's the purpose of this patch: to make it easier to discover this > simple API. It modifies the HowToUseJIT.cpp example file *only*. Great idea! Committed thusly: [ghostwheel:~/sources/llvm] echristo% svn ci Sending examples/HowToUseJIT/HowToUseJIT.cpp Transmitting file data . Committed revision 132770. -eric From echristo at apple.com Wed Jun 8 23:08:36 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 08 Jun 2011 23:08:36 -0700 Subject: [llvm-commits] [llvm] r132676 - in /llvm/trunk: lib/CodeGen/SelectionDAG/FastISel.cpp test/CodeGen/X86/fast-isel-agg-constant.ll In-Reply-To: <20110606153822.GA6591@freebsd.org> References: <20110606153822.GA6591@freebsd.org> Message-ID: On Jun 6, 2011, at 8:38 AM, Roman Divacky wrote: > OK to commit? Or is there a better way to distinguish those two > asm dialects? Maybe check the Subtarget instead? -eric From eli.friedman at gmail.com Wed Jun 8 23:29:57 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 8 Jun 2011 23:29:57 -0700 Subject: [llvm-commits] [llvm] r132764 - in /llvm/trunk: lib/CodeGen/CallingConvLower.cpp test/CodeGen/X86/byval-align.ll In-Reply-To: <20110609001519.857642A6C12C@llvm.org> References: <20110609001519.857642A6C12C@llvm.org> Message-ID: On Wed, Jun 8, 2011 at 5:15 PM, Eric Christopher wrote: > Author: echristo > Date: Wed Jun  8 19:15:19 2011 > New Revision: 132764 > > URL: http://llvm.org/viewvc/llvm-project?rev=132764&view=rev > Log: > If the alignment of the byval argument is greater than the alignment > of the frame then increase the maximum alignment of the frame to > match. > > Fixes PR6965 I know it seems pretty strange, but this appears to be breaking the http://google1.osuosl.org:8011/builders/llvm-gcc-native-mingw32-win7 buildbot... -Eli > Added: >    llvm/trunk/test/CodeGen/X86/byval-align.ll > Modified: >    llvm/trunk/lib/CodeGen/CallingConvLower.cpp > > Modified: llvm/trunk/lib/CodeGen/CallingConvLower.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CallingConvLower.cpp?rev=132764&r1=132763&r2=132764&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/CallingConvLower.cpp (original) > +++ llvm/trunk/lib/CodeGen/CallingConvLower.cpp Wed Jun  8 19:15:19 2011 > @@ -49,6 +49,8 @@ >     Size = MinSize; >   if (MinAlign > (int)Align) >     Align = MinAlign; > +  if (MF.getFrameInfo()->getMaxAlignment() < Align) > +    MF.getFrameInfo()->setMaxAlignment(Align); >   TM.getTargetLowering()->HandleByVal(const_cast(this), Size); >   unsigned Offset = AllocateStack(Size, Align); >   addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); > > Added: llvm/trunk/test/CodeGen/X86/byval-align.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/byval-align.ll?rev=132764&view=auto > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/byval-align.ll (added) > +++ llvm/trunk/test/CodeGen/X86/byval-align.ll Wed Jun  8 19:15:19 2011 > @@ -0,0 +1,59 @@ > +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s > +%struct.S = type { i32} > + > + at .str = private constant [10 x i8] c"ptr = %p\0A\00", align 1 ; <[10 x i8]*> [#uses=1] > + at .str1 = private constant [8 x i8] c"Failed \00", align 1 ; <[8 x i8]*> [#uses=1] > + at .str2 = private constant [2 x i8] c"0\00", align 1 ; <[2 x i8]*> [#uses=1] > + at .str3 = private constant [7 x i8] c"test.c\00", align 1 ; <[7 x i8]*> [#uses=1] > + at __PRETTY_FUNCTION__.2067 = internal constant [13 x i8] c"aligned_func\00" ; <[13 x i8]*> [#uses=1] > + > +define void @aligned_func(%struct.S* byval align 64 %obj) nounwind { > +entry: > +  %ptr = alloca i8*                               ; [#uses=3] > +  %p = alloca i64                                 ; [#uses=3] > +  %"alloca point" = bitcast i32 0 to i32          ; [#uses=0] > +  %obj1 = bitcast %struct.S* %obj to i8*          ; [#uses=1] > +  store i8* %obj1, i8** %ptr, align 8 > +  %0 = load i8** %ptr, align 8                    ; [#uses=1] > +  %1 = ptrtoint i8* %0 to i64                     ; [#uses=1] > +  store i64 %1, i64* %p, align 8 > +  %2 = load i8** %ptr, align 8                    ; [#uses=1] > +  %3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([10 x i8]* @.str, i64 0, i64 0), i8* %2) nounwind ; [#uses=0] > +  %4 = load i64* %p, align 8                      ; [#uses=1] > +  %5 = and i64 %4, 140737488355264                ; [#uses=1] > +  %6 = load i64* %p, align 8                      ; [#uses=1] > +  %7 = icmp ne i64 %5, %6                         ; [#uses=1] > +  br i1 %7, label %bb, label %bb2 > + > +bb:                                               ; preds = %entry > +  %8 = call i32 @puts(i8* getelementptr inbounds ([8 x i8]* @.str1, i64 0, i64 0)) nounwind ; [#uses=0] > +  call void @__assert_fail(i8* getelementptr inbounds ([2 x i8]* @.str2, i64 0, i64 0), i8* getelementptr inbounds ([7 x i8]* @.str3, i64 0, i64 0), i32 18, i8* getelementptr inbounds ([13 x i8]* @__PRETTY_FUNCTION__.2067, i64 0, i64 0)) noreturn nounwind > +  unreachable > + > +bb2:                                              ; preds = %entry > +  br label %return > + > +return:                                           ; preds = %bb2 > +  ret void > +} > + > +declare i32 @printf(i8*, ...) nounwind > + > +declare i32 @puts(i8*) > + > +declare void @__assert_fail(i8*, i8*, i32, i8*) noreturn nounwind > + > +define void @main() nounwind { > +entry: > +; CHECK: main > +; CHECK: andq    $-64, %rsp > +  %s1 = alloca %struct.S                          ; <%struct.S*> [#uses=4] > +  %"alloca point" = bitcast i32 0 to i32          ; [#uses=0] > +  %0 = getelementptr inbounds %struct.S* %s1, i32 0, i32 0 ; [#uses=1] > +  store i32 1, i32* %0, align 4 > +  call void @aligned_func(%struct.S* byval align 64 %s1) nounwind > +  br label %return > + > +return:                                           ; preds = %entry > +  ret void > +} > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From echristo at apple.com Wed Jun 8 23:33:46 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 08 Jun 2011 23:33:46 -0700 Subject: [llvm-commits] [llvm] r132764 - in /llvm/trunk: lib/CodeGen/CallingConvLower.cpp test/CodeGen/X86/byval-align.ll In-Reply-To: References: <20110609001519.857642A6C12C@llvm.org> Message-ID: On Jun 8, 2011, at 11:29 PM, Eli Friedman wrote: > On Wed, Jun 8, 2011 at 5:15 PM, Eric Christopher wrote: >> Author: echristo >> Date: Wed Jun 8 19:15:19 2011 >> New Revision: 132764 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=132764&view=rev >> Log: >> If the alignment of the byval argument is greater than the alignment >> of the frame then increase the maximum alignment of the frame to >> match. >> >> Fixes PR6965 > > I know it seems pretty strange, but this appears to be breaking the > http://google1.osuosl.org:8011/builders/llvm-gcc-native-mingw32-win7 > buildbot... Hmm.. I'd thought that was Cameron's patch when I saw it. I can revert to check though. -eric From echristo at apple.com Wed Jun 8 23:29:54 2011 From: echristo at apple.com (Eric Christopher) Date: Thu, 09 Jun 2011 06:29:54 -0000 Subject: [llvm-commits] [llvm] r132771 - in /llvm/trunk: lib/CodeGen/CallingConvLower.cpp test/CodeGen/X86/byval-align.ll Message-ID: <20110609062954.BFFCC2A6C12C@llvm.org> Author: echristo Date: Thu Jun 9 01:29:54 2011 New Revision: 132771 URL: http://llvm.org/viewvc/llvm-project?rev=132771&view=rev Log: Temporarily revert 132764 to see if it fixes the Windows buildbot. Removed: llvm/trunk/test/CodeGen/X86/byval-align.ll Modified: llvm/trunk/lib/CodeGen/CallingConvLower.cpp Modified: llvm/trunk/lib/CodeGen/CallingConvLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CallingConvLower.cpp?rev=132771&r1=132770&r2=132771&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CallingConvLower.cpp (original) +++ llvm/trunk/lib/CodeGen/CallingConvLower.cpp Thu Jun 9 01:29:54 2011 @@ -49,8 +49,6 @@ Size = MinSize; if (MinAlign > (int)Align) Align = MinAlign; - if (MF.getFrameInfo()->getMaxAlignment() < Align) - MF.getFrameInfo()->setMaxAlignment(Align); TM.getTargetLowering()->HandleByVal(const_cast(this), Size); unsigned Offset = AllocateStack(Size, Align); addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); Removed: llvm/trunk/test/CodeGen/X86/byval-align.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/byval-align.ll?rev=132770&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/byval-align.ll (original) +++ llvm/trunk/test/CodeGen/X86/byval-align.ll (removed) @@ -1,59 +0,0 @@ -; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -%struct.S = type { i32} - - at .str = private constant [10 x i8] c"ptr = %p\0A\00", align 1 ; <[10 x i8]*> [#uses=1] - at .str1 = private constant [8 x i8] c"Failed \00", align 1 ; <[8 x i8]*> [#uses=1] - at .str2 = private constant [2 x i8] c"0\00", align 1 ; <[2 x i8]*> [#uses=1] - at .str3 = private constant [7 x i8] c"test.c\00", align 1 ; <[7 x i8]*> [#uses=1] - at __PRETTY_FUNCTION__.2067 = internal constant [13 x i8] c"aligned_func\00" ; <[13 x i8]*> [#uses=1] - -define void @aligned_func(%struct.S* byval align 64 %obj) nounwind { -entry: - %ptr = alloca i8* ; [#uses=3] - %p = alloca i64 ; [#uses=3] - %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] - %obj1 = bitcast %struct.S* %obj to i8* ; [#uses=1] - store i8* %obj1, i8** %ptr, align 8 - %0 = load i8** %ptr, align 8 ; [#uses=1] - %1 = ptrtoint i8* %0 to i64 ; [#uses=1] - store i64 %1, i64* %p, align 8 - %2 = load i8** %ptr, align 8 ; [#uses=1] - %3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([10 x i8]* @.str, i64 0, i64 0), i8* %2) nounwind ; [#uses=0] - %4 = load i64* %p, align 8 ; [#uses=1] - %5 = and i64 %4, 140737488355264 ; [#uses=1] - %6 = load i64* %p, align 8 ; [#uses=1] - %7 = icmp ne i64 %5, %6 ; [#uses=1] - br i1 %7, label %bb, label %bb2 - -bb: ; preds = %entry - %8 = call i32 @puts(i8* getelementptr inbounds ([8 x i8]* @.str1, i64 0, i64 0)) nounwind ; [#uses=0] - call void @__assert_fail(i8* getelementptr inbounds ([2 x i8]* @.str2, i64 0, i64 0), i8* getelementptr inbounds ([7 x i8]* @.str3, i64 0, i64 0), i32 18, i8* getelementptr inbounds ([13 x i8]* @__PRETTY_FUNCTION__.2067, i64 0, i64 0)) noreturn nounwind - unreachable - -bb2: ; preds = %entry - br label %return - -return: ; preds = %bb2 - ret void -} - -declare i32 @printf(i8*, ...) nounwind - -declare i32 @puts(i8*) - -declare void @__assert_fail(i8*, i8*, i32, i8*) noreturn nounwind - -define void @main() nounwind { -entry: -; CHECK: main -; CHECK: andq $-64, %rsp - %s1 = alloca %struct.S ; <%struct.S*> [#uses=4] - %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] - %0 = getelementptr inbounds %struct.S* %s1, i32 0, i32 0 ; [#uses=1] - store i32 1, i32* %0, align 4 - call void @aligned_func(%struct.S* byval align 64 %s1) nounwind - br label %return - -return: ; preds = %entry - ret void -} From zwarich at apple.com Wed Jun 8 23:37:08 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Wed, 08 Jun 2011 23:37:08 -0700 Subject: [llvm-commits] [llvm] r132764 - in /llvm/trunk: lib/CodeGen/CallingConvLower.cpp test/CodeGen/X86/byval-align.ll In-Reply-To: References: <20110609001519.857642A6C12C@llvm.org> Message-ID: On 2011-06-08, at 11:33 PM, Eric Christopher wrote: > On Jun 8, 2011, at 11:29 PM, Eli Friedman wrote: > >> On Wed, Jun 8, 2011 at 5:15 PM, Eric Christopher wrote: >>> Author: echristo >>> Date: Wed Jun 8 19:15:19 2011 >>> New Revision: 132764 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=132764&view=rev >>> Log: >>> If the alignment of the byval argument is greater than the alignment >>> of the frame then increase the maximum alignment of the frame to >>> match. >>> >>> Fixes PR6965 >> >> I know it seems pretty strange, but this appears to be breaking the >> http://google1.osuosl.org:8011/builders/llvm-gcc-native-mingw32-win7 >> buildbot... > > Hmm.. I'd thought that was Cameron's patch when I saw it. I can revert > to check though. My patch affected opt, not llc, so it would be even more surprising if it caused the failure. :) Cameron From echristo at apple.com Wed Jun 8 23:38:36 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 08 Jun 2011 23:38:36 -0700 Subject: [llvm-commits] [llvm] r132764 - in /llvm/trunk: lib/CodeGen/CallingConvLower.cpp test/CodeGen/X86/byval-align.ll In-Reply-To: References: <20110609001519.857642A6C12C@llvm.org> Message-ID: On Jun 8, 2011, at 11:37 PM, Cameron Zwarich wrote: > On 2011-06-08, at 11:33 PM, Eric Christopher wrote: > >> On Jun 8, 2011, at 11:29 PM, Eli Friedman wrote: >> >>> On Wed, Jun 8, 2011 at 5:15 PM, Eric Christopher wrote: >>>> Author: echristo >>>> Date: Wed Jun 8 19:15:19 2011 >>>> New Revision: 132764 >>>> >>>> URL: http://llvm.org/viewvc/llvm-project?rev=132764&view=rev >>>> Log: >>>> If the alignment of the byval argument is greater than the alignment >>>> of the frame then increase the maximum alignment of the frame to >>>> match. >>>> >>>> Fixes PR6965 >>> >>> I know it seems pretty strange, but this appears to be breaking the >>> http://google1.osuosl.org:8011/builders/llvm-gcc-native-mingw32-win7 >>> buildbot... >> >> Hmm.. I'd thought that was Cameron's patch when I saw it. I can revert >> to check though. > > My patch affected opt, not llc, so it would be even more surprising if it caused the failure. :) Heh. Good point. I was looking on my phone at the time ;) Of course, I have no earthly clue how it could have broken the windows builder... -eric From sabre at nondot.org Wed Jun 8 23:38:17 2011 From: sabre at nondot.org (Chris Lattner) Date: Thu, 09 Jun 2011 06:38:17 -0000 Subject: [llvm-commits] [llvm] r132772 - /llvm/trunk/lib/Support/Host.cpp Message-ID: <20110609063818.03A802A6C12C@llvm.org> Author: lattner Date: Thu Jun 9 01:38:17 2011 New Revision: 132772 URL: http://llvm.org/viewvc/llvm-project?rev=132772&view=rev Log: add another sandybridge alias. Modified: llvm/trunk/lib/Support/Host.cpp Modified: llvm/trunk/lib/Support/Host.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Host.cpp?rev=132772&r1=132771&r2=132772&view=diff ============================================================================== --- llvm/trunk/lib/Support/Host.cpp (original) +++ llvm/trunk/lib/Support/Host.cpp Thu Jun 9 01:38:17 2011 @@ -215,6 +215,7 @@ case 37: // Intel Core i7, laptop version. return "corei7"; case 42: // SandyBridge + case 45: return "corei7-avx"; case 28: // Intel Atom processor. All processors are manufactured using From echristo at apple.com Wed Jun 8 23:51:47 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 08 Jun 2011 23:51:47 -0700 Subject: [llvm-commits] [llvm] r132764 - in /llvm/trunk: lib/CodeGen/CallingConvLower.cpp test/CodeGen/X86/byval-align.ll In-Reply-To: References: <20110609001519.857642A6C12C@llvm.org> Message-ID: <635EA6A3-82FC-4A87-A91C-93D72B11DC3F@apple.com> On Jun 8, 2011, at 11:38 PM, Eric Christopher wrote: > > On Jun 8, 2011, at 11:37 PM, Cameron Zwarich wrote: > >> On 2011-06-08, at 11:33 PM, Eric Christopher wrote: >> >>> On Jun 8, 2011, at 11:29 PM, Eli Friedman wrote: >>> >>>> On Wed, Jun 8, 2011 at 5:15 PM, Eric Christopher wrote: >>>>> Author: echristo >>>>> Date: Wed Jun 8 19:15:19 2011 >>>>> New Revision: 132764 >>>>> >>>>> URL: http://llvm.org/viewvc/llvm-project?rev=132764&view=rev >>>>> Log: >>>>> If the alignment of the byval argument is greater than the alignment >>>>> of the frame then increase the maximum alignment of the frame to >>>>> match. >>>>> >>>>> Fixes PR6965 >>>> >>>> I know it seems pretty strange, but this appears to be breaking the >>>> http://google1.osuosl.org:8011/builders/llvm-gcc-native-mingw32-win7 >>>> buildbot... >>> >>> Hmm.. I'd thought that was Cameron's patch when I saw it. I can revert >>> to check though. >> >> My patch affected opt, not llc, so it would be even more surprising if it caused the failure. :) > > Heh. Good point. I was looking on my phone at the time ;) > > Of course, I have no earthly clue how it could have broken the windows builder... Wondering if it might have been r132758 and the builder was just confused. -eric From baldrick at free.fr Thu Jun 9 00:59:58 2011 From: baldrick at free.fr (Duncan Sands) Date: Thu, 09 Jun 2011 07:59:58 -0000 Subject: [llvm-commits] [dragonegg] r132773 - /dragonegg/trunk/src/Convert.cpp Message-ID: <20110609075959.091BC2A6C12D@llvm.org> Author: baldrick Date: Thu Jun 9 02:59:58 2011 New Revision: 132773 URL: http://llvm.org/viewvc/llvm-project?rev=132773&view=rev Log: Simplify using Builder.getIntXYZ methods. Modified: dragonegg/trunk/src/Convert.cpp Modified: dragonegg/trunk/src/Convert.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=132773&r1=132772&r2=132773&view=diff ============================================================================== --- dragonegg/trunk/src/Convert.cpp (original) +++ dragonegg/trunk/src/Convert.cpp Thu Jun 9 02:59:58 2011 @@ -453,9 +453,8 @@ Builder.CreateCast(Instruction::BitCast, AI, SBP), ConstantInt::get(IntPtr, TREE_INT_CST_LOW(TYPE_SIZE_UNIT(type))), - ConstantInt::get(Type::getInt32Ty(Context), - LLVM_BYVAL_ALIGNMENT(type)), - ConstantInt::get(Type::getInt1Ty(Context), false) + Builder.getInt32(LLVM_BYVAL_ALIGNMENT(type)), + Builder.getFalse() }; const Type *ArgTypes[3] = {SBP, SBP, IntPtr }; Builder.CreateCall(Intrinsic::getDeclaration(TheModule, @@ -943,9 +942,9 @@ Value *R1 = Builder.CreateBitCast(RetVal, STy->getPointerTo()); llvm::Value *Idxs[2]; - Idxs[0] = ConstantInt::get(llvm::Type::getInt32Ty(Context), 0); + Idxs[0] = Builder.getInt32(0); for (unsigned ri = 0; ri < STy->getNumElements(); ++ri) { - Idxs[1] = ConstantInt::get(llvm::Type::getInt32Ty(Context), ri); + Idxs[1] = Builder.getInt32(ri); Value *GEP = Builder.CreateGEP(R1, Idxs, Idxs+2, "mrv_gep"); Value *E = Builder.CreateLoad(GEP, "mrv"); RetVals.push_back(E); @@ -1628,7 +1627,7 @@ } } - EmitMemSet(DestLoc.Ptr, ConstantInt::get(Type::getInt8Ty(Context), 0), + EmitMemSet(DestLoc.Ptr, Builder.getInt8(0), EmitRegister(TYPE_SIZE_UNIT(type)), DestLoc.getAlignment()); } @@ -1640,8 +1639,8 @@ Builder.CreateBitCast(DestPtr, SBP), Builder.CreateBitCast(SrcPtr, SBP), Builder.CreateIntCast(Size, IntPtr, /*isSigned*/true), - ConstantInt::get(Type::getInt32Ty(Context), Align), - ConstantInt::get(Type::getInt1Ty(Context), false) + Builder.getInt32(Align), + Builder.getFalse() }; const Type *ArgTypes[3] = { SBP, SBP, IntPtr }; @@ -1658,8 +1657,8 @@ Builder.CreateBitCast(DestPtr, SBP), Builder.CreateBitCast(SrcPtr, SBP), Builder.CreateIntCast(Size, IntPtr, /*isSigned*/true), - ConstantInt::get(Type::getInt32Ty(Context), Align), - ConstantInt::get(Type::getInt1Ty(Context), false) + Builder.getInt32(Align), + Builder.getFalse() }; const Type *ArgTypes[3] = { SBP, SBP, IntPtr }; @@ -1676,8 +1675,8 @@ Builder.CreateBitCast(DestPtr, SBP), Builder.CreateIntCast(SrcVal, Type::getInt8Ty(Context), /*isSigned*/true), Builder.CreateIntCast(Size, IntPtr, /*isSigned*/true), - ConstantInt::get(Type::getInt32Ty(Context), Align), - ConstantInt::get(Type::getInt1Ty(Context), false) + Builder.getInt32(Align), + Builder.getFalse() }; const Type *ArgTypes[2] = { SBP, IntPtr }; @@ -2084,8 +2083,7 @@ } // The length is one more than the number of typeinfos. - Args[LengthIndex] = ConstantInt::get(Type::getInt32Ty(Context), - Args.size() - LengthIndex); + Args[LengthIndex] = Builder.getInt32(Args.size() - LengthIndex); break; } case ERT_CLEANUP: @@ -2094,7 +2092,7 @@ case ERT_MUST_NOT_THROW: // Same as a zero-length filter. AllCaught = true; - Args.push_back(ConstantInt::get(Type::getInt32Ty(Context), 1)); + Args.push_back(Builder.getInt32(1)); break; case ERT_TRY: // Catches. @@ -2122,7 +2120,7 @@ if (HasCleanup) { if (Args.size() == 2) // Insert a sentinel indicating that this is a cleanup-only selector. - Args.push_back(ConstantInt::get(Type::getInt32Ty(Context), 0)); + Args.push_back(Builder.getInt32(0)); else if (!AllCaught) // Some exceptions from this region may not be caught by any handler. // Since invokes are required to branch to the unwind label no matter @@ -2204,7 +2202,7 @@ Args[1] = Builder.CreateBitCast(DECL_LLVM(personality), Type::getInt8PtrTy(Context)); // One more than the filter length. - Args[2] = ConstantInt::get(Type::getInt32Ty(Context), 1); + Args[2] = Builder.getInt32(1); // Create the selector call. Builder.CreateCall(SlctrIntr, Args, Args + 3, "filter"); @@ -2340,9 +2338,7 @@ ThisLastBitPlusOne = LV.BitStart+LV.BitSize; Value *Ptr = Index ? - Builder.CreateGEP(LV.Ptr, - ConstantInt::get(Type::getInt32Ty(Context), Index)) : - LV.Ptr; + Builder.CreateGEP(LV.Ptr, Builder.getInt32(Index)) : LV.Ptr; LoadInst *LI = Builder.CreateLoad(Ptr, LV.Volatile); LI->setAlignment(Alignment); Value *Val = LI; @@ -2443,7 +2439,7 @@ // GCC allows vectors to be built up from vectors. Extract all of the // vector elements and add them to the list of build vector operands. for (unsigned i = 0, e = EltTy->getNumElements(); i != e; ++i) { - Value *Index = ConstantInt::get(llvm::Type::getInt32Ty(Context), i); + Value *Index = Builder.getInt32(i); BuildVecOps.push_back(Builder.CreateExtractElement(Elt, Index)); } } else { @@ -3590,8 +3586,7 @@ UndefValue::get(VectorType::get(Ops[0]->getType(), Ops.size())); for (unsigned i = 0, e = Ops.size(); i != e; ++i) - Result = Builder.CreateInsertElement(Result, Ops[i], - ConstantInt::get(Type::getInt32Ty(Context), i)); + Result = Builder.CreateInsertElement(Result, Ops[i], Builder.getInt32(i)); return Result; } @@ -3634,7 +3629,7 @@ Idxs.push_back(UndefValue::get(Type::getInt32Ty(Context))); else { assert((unsigned)idx < 2*NumElements && "Element index out of range!"); - Idxs.push_back(ConstantInt::get(Type::getInt32Ty(Context), idx)); + Idxs.push_back(Builder.getInt32(idx)); } } va_end(VA); @@ -3685,11 +3680,11 @@ void TreeToLLVM::EmitMemoryBarrier(bool ll, bool ls, bool sl, bool ss, bool device) { Value* C[5]; - C[0] = ConstantInt::get(Type::getInt1Ty(Context), ll); - C[1] = ConstantInt::get(Type::getInt1Ty(Context), ls); - C[2] = ConstantInt::get(Type::getInt1Ty(Context), sl); - C[3] = ConstantInt::get(Type::getInt1Ty(Context), ss); - C[4] = ConstantInt::get(Type::getInt1Ty(Context), device); + C[0] = Builder.getInt1(ll); + C[1] = Builder.getInt1(ls); + C[2] = Builder.getInt1(sl); + C[3] = Builder.getInt1(ss); + C[4] = Builder.getInt1(device); Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Intrinsic::memory_barrier), @@ -4165,8 +4160,8 @@ case BUILT_IN_SYNCHRONIZE: { // We assume like gcc appears to, that this only applies to cached memory. Value* C[5]; - C[0] = C[1] = C[2] = C[3] = ConstantInt::get(Type::getInt1Ty(Context), 1); - C[4] = ConstantInt::get(Type::getInt1Ty(Context), 0); + C[0] = C[1] = C[2] = C[3] = Builder.getTrue(); + C[4] = Builder.getFalse(); Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Intrinsic::memory_barrier), @@ -5067,9 +5062,9 @@ // Default to highly local read. if (ReadWrite == 0) - ReadWrite = Constant::getNullValue(Type::getInt32Ty(Context)); + ReadWrite = Builder.getInt32(0); if (Locality == 0) - Locality = ConstantInt::get(Type::getInt32Ty(Context), 3); + Locality = Builder.getInt32(3); Ptr = Builder.CreateBitCast(Ptr, Type::getInt8PtrTy(Context)); @@ -5194,7 +5189,7 @@ Result = Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Intrinsic::eh_dwarf_cfa), - ConstantInt::get(Type::getInt32Ty(Context), cfa_offset)); + Builder.getInt32(cfa_offset)); return true; } @@ -5295,25 +5290,21 @@ if (rnum < 0) continue; - Size = ConstantInt::get(Type::getInt8Ty(Context), size); - Idx = ConstantInt::get(Type::getInt32Ty(Context), rnum); + Size = Builder.getInt8(size); + Idx = Builder.getInt32(rnum); Builder.CreateStore(Size, Builder.CreateGEP(Addr, Idx), false); } } if (!wrote_return_column) { - Size = ConstantInt::get(Type::getInt8Ty(Context), - GET_MODE_SIZE (Pmode)); - Idx = ConstantInt::get(Type::getInt32Ty(Context), - DWARF_FRAME_RETURN_COLUMN); + Size = Builder.getInt8(GET_MODE_SIZE (Pmode)); + Idx = Builder.getInt32(DWARF_FRAME_RETURN_COLUMN); Builder.CreateStore(Size, Builder.CreateGEP(Addr, Idx), false); } #ifdef DWARF_ALT_FRAME_RETURN_COLUMN - Size = ConstantInt::get(Type::getInt8Ty(Context), - GET_MODE_SIZE (Pmode)); - Idx = ConstantInt::get(Type::getInt32Ty(Context), - DWARF_ALT_FRAME_RETURN_COLUMN); + Size = Builder.getInt8(GET_MODE_SIZE (Pmode)); + Idx = Builder.getInt32(DWARF_ALT_FRAME_RETURN_COLUMN); Builder.CreateStore(Size, Builder.CreateGEP(Addr, Idx), false); #endif @@ -5497,7 +5488,7 @@ // The GCC trampoline storage is constant from this point on. Tell this to // the optimizers. Intr = Intrinsic::getDeclaration(TheModule, Intrinsic::invariant_start); - Ops[0] = ConstantInt::get(Type::getInt64Ty(Context), TRAMPOLINE_SIZE); + Ops[0] = Builder.getInt64(TRAMPOLINE_SIZE); Ops[1] = Builder.CreateBitCast(Tramp, VPTy); Builder.CreateCall(Intr, Ops, Ops + 2); @@ -5695,9 +5686,7 @@ // TODO: If Ptr.Ptr is a struct type or something, we can do much better // than this. e.g. check out when compiling unwind-dw2-fde-darwin.c. Ptr.Ptr = Builder.CreateBitCast(Ptr.Ptr, ValTy->getPointerTo()); - Ptr.Ptr = Builder.CreateGEP(Ptr.Ptr, - ConstantInt::get(Type::getInt32Ty(Context), - UnitOffset)); + Ptr.Ptr = Builder.CreateGEP(Ptr.Ptr, Builder.getInt32(UnitOffset)); BitStart -= UnitOffset*ValueSizeInBits; } @@ -6291,7 +6280,7 @@ Value *V = UndefValue::get(RegTy); unsigned NumElts = TYPE_VECTOR_SUBPARTS(type); for (unsigned i = 0; i != NumElts; ++i) { - Value *Idx = ConstantInt::get(Type::getInt32Ty(Context), i); + Value *Idx = Builder.getInt32(i); Value *Val = Builder.CreateExtractElement(V, Idx); Val = Mem2Reg(Val, TREE_TYPE(type), Builder); V = Builder.CreateInsertElement(V, Val, Idx); @@ -6336,7 +6325,7 @@ Value *V = UndefValue::get(MemTy); unsigned NumElts = TYPE_VECTOR_SUBPARTS(type); for (unsigned i = 0; i != NumElts; ++i) { - Value *Idx = ConstantInt::get(Type::getInt32Ty(Context), i); + Value *Idx = Builder.getInt32(i); Value *Val = Builder.CreateExtractElement(V, Idx); Val = Reg2Mem(Val, TREE_TYPE(type), Builder); V = Builder.CreateInsertElement(V, Val, Idx); @@ -6382,9 +6371,8 @@ unsigned NumElts = Ty->getNumElements() / 2; SmallVector Mask; Mask.reserve(NumElts); - const Type *Int32Ty = Type::getInt32Ty(Context); for (unsigned i = 0; i != NumElts; ++i) - Mask.push_back(ConstantInt::get(Int32Ty, NumElts + i)); + Mask.push_back(Builder.getInt32(NumElts + i)); return Builder.CreateShuffleVector(Vec, UndefValue::get(Ty), ConstantVector::get(Mask)); } @@ -6397,9 +6385,8 @@ unsigned NumElts = Ty->getNumElements() / 2; SmallVector Mask; Mask.reserve(NumElts); - const Type *Int32Ty = Type::getInt32Ty(Context); for (unsigned i = 0; i != NumElts; ++i) - Mask.push_back(ConstantInt::get(Int32Ty, i)); + Mask.push_back(Builder.getInt32(i)); return Builder.CreateShuffleVector(Vec, UndefValue::get(Ty), ConstantVector::get(Mask)); } @@ -6701,20 +6688,19 @@ unsigned Length = TYPE_VECTOR_SUBPARTS(TREE_TYPE(op)); assert(Length > 1 && !(Length & (Length - 1)) && "Length not a power of 2!"); SmallVector Mask(Length); - const Type *Int32Ty = Type::getInt32Ty(Context); - Constant *UndefIndex = UndefValue::get(Int32Ty); + Constant *UndefIndex = UndefValue::get(Type::getInt32Ty(Context)); for (unsigned Elts = Length >> 1; Elts; Elts >>= 1) { // In the extracted vectors, elements with index Elts and on are undefined. for (unsigned i = Elts; i != Length; ++i) Mask[i] = UndefIndex; // Extract elements [0, Elts) from Val. for (unsigned i = 0; i != Elts; ++i) - Mask[i] = ConstantInt::get(Int32Ty, i); + Mask[i] = Builder.getInt32(i); Value *LHS = Builder.CreateShuffleVector(Val, UndefValue::get(Ty), ConstantVector::get(Mask)); // Extract elements [Elts, 2*Elts) from Val. for (unsigned i = 0; i != Elts; ++i) - Mask[i] = ConstantInt::get(Int32Ty, Elts + i); + Mask[i] = Builder.getInt32(Elts + i); Value *RHS = Builder.CreateShuffleVector(Val, UndefValue::get(Ty), ConstantVector::get(Mask)); @@ -6744,20 +6730,19 @@ unsigned Length = TYPE_VECTOR_SUBPARTS(TREE_TYPE(op)); assert(Length > 1 && !(Length & (Length - 1)) && "Length not a power of 2!"); SmallVector Mask(Length); - const Type *Int32Ty = Type::getInt32Ty(Context); - Constant *UndefIndex = UndefValue::get(Int32Ty); + Constant *UndefIndex = UndefValue::get(Type::getInt32Ty(Context)); for (unsigned Elts = Length >> 1; Elts; Elts >>= 1) { // In the extracted vectors, elements with index Elts and on are undefined. for (unsigned i = Elts; i != Length; ++i) Mask[i] = UndefIndex; // Extract elements [0, Elts) from Val. for (unsigned i = 0; i != Elts; ++i) - Mask[i] = ConstantInt::get(Int32Ty, i); + Mask[i] = Builder.getInt32(i); Value *LHS = Builder.CreateShuffleVector(Val, UndefValue::get(Ty), ConstantVector::get(Mask)); // Extract elements [Elts, 2*Elts) from Val. for (unsigned i = 0; i != Elts; ++i) - Mask[i] = ConstantInt::get(Int32Ty, Elts + i); + Mask[i] = Builder.getInt32(Elts + i); Value *RHS = Builder.CreateShuffleVector(Val, UndefValue::get(Ty), ConstantVector::get(Mask)); @@ -6850,19 +6835,19 @@ unsigned Length = VecTy->getNumElements(); SmallVector Mask; Mask.reserve(Length); - const Type *Int32Ty = Type::getInt32Ty(Context); if (isLeftShift) { // shl <4 x i32> %v, 32 -> // shufflevector <4 x i32> %v, <4 x i32> undef, - Mask.append(Length - EltOffset, UndefValue::get(Int32Ty)); + Mask.append(Length - EltOffset, + UndefValue::get(Type::getInt32Ty(Context))); for (unsigned i = 0; i != EltOffset; ++i) - Mask.push_back(ConstantInt::get(Int32Ty, i)); + Mask.push_back(Builder.getInt32(i)); } else { // shr <4 x i32> %v, 32 -> // shufflevector <4 x i32> %v, <4 x i32> undef, <1, 2, 3, undef> for (unsigned i = EltOffset; i != Length; ++i) - Mask.push_back(ConstantInt::get(Int32Ty, i)); - Mask.append(EltOffset, UndefValue::get(Int32Ty)); + Mask.push_back(Builder.getInt32(i)); + Mask.append(EltOffset, UndefValue::get(Type::getInt32Ty(Context))); } return Builder.CreateShuffleVector(LHS, UndefValue::get(VecTy), ConstantVector::get(Mask)); @@ -7331,7 +7316,7 @@ SmallVector Mask; Mask.reserve(Length); for (unsigned i = 0; i != Length; ++i) - Mask.push_back(ConstantInt::get(Type::getInt32Ty(Context), 2*i)); + Mask.push_back(Builder.getInt32(2*i)); return Builder.CreateShuffleVector(LHS, RHS, ConstantVector::get(Mask)); } @@ -7342,7 +7327,7 @@ SmallVector Mask; Mask.reserve(Length); for (unsigned i = 0; i != Length; ++i) - Mask.push_back(ConstantInt::get(Type::getInt32Ty(Context), 2*i+1)); + Mask.push_back(Builder.getInt32(2*i+1)); return Builder.CreateShuffleVector(LHS, RHS, ConstantVector::get(Mask)); } @@ -7354,8 +7339,8 @@ SmallVector Mask; Mask.reserve(Length); for (unsigned i = Length/2; i != Length; ++i) { - Mask.push_back(ConstantInt::get(Type::getInt32Ty(Context), i)); - Mask.push_back(ConstantInt::get(Type::getInt32Ty(Context), Length + i)); + Mask.push_back(Builder.getInt32(i)); + Mask.push_back(Builder.getInt32(Length + i)); } return Builder.CreateShuffleVector(LHS, RHS, ConstantVector::get(Mask)); } @@ -7368,8 +7353,8 @@ SmallVector Mask; Mask.reserve(Length); for (unsigned i = 0, e = Length/2; i != e; ++i) { - Mask.push_back(ConstantInt::get(Type::getInt32Ty(Context), i)); - Mask.push_back(ConstantInt::get(Type::getInt32Ty(Context), Length + i)); + Mask.push_back(Builder.getInt32(i)); + Mask.push_back(Builder.getInt32(Length + i)); } return Builder.CreateShuffleVector(LHS, RHS, ConstantVector::get(Mask)); } @@ -7393,7 +7378,7 @@ SmallVector Mask; Mask.reserve(2*Length); for (unsigned i = 0, e = 2*Length; i != e; ++i) - Mask.push_back(ConstantInt::get(Type::getInt32Ty(Context), i)); + Mask.push_back(Builder.getInt32(i)); return Builder.CreateShuffleVector(LHS, RHS, ConstantVector::get(Mask)); } @@ -8578,9 +8563,7 @@ ThisLastBitPlusOne = LV.BitStart+LV.BitSize; Value *Ptr = Index ? - Builder.CreateGEP(LV.Ptr, - ConstantInt::get(Type::getInt32Ty(Context), Index)) : - LV.Ptr; + Builder.CreateGEP(LV.Ptr, Builder.getInt32(Index)) : LV.Ptr; LoadInst *LI = Builder.CreateLoad(Ptr, LV.Volatile); LI->setAlignment(Alignment); Value *OldVal = LI; @@ -8602,7 +8585,7 @@ // be set in the result. uint64_t MaskVal = 1; MaskVal = ((MaskVal << BitsInVal)-1) << FirstBitInVal; - Constant *Mask = ConstantInt::get(Type::getInt64Ty(Context), MaskVal); + Constant *Mask = Builder.getInt64(MaskVal); Mask = Builder.getFolder().CreateTruncOrBitCast(Mask, ValTy); if (FirstBitInVal+BitsInVal != ValSizeInBits) From rdivacky at freebsd.org Thu Jun 9 01:08:19 2011 From: rdivacky at freebsd.org (Roman Divacky) Date: Thu, 9 Jun 2011 10:08:19 +0200 Subject: [llvm-commits] [llvm] r132676 - in /llvm/trunk: lib/CodeGen/SelectionDAG/FastISel.cpp test/CodeGen/X86/fast-isel-agg-constant.ll In-Reply-To: References: <20110606153822.GA6591@freebsd.org> Message-ID: <20110609080819.GA4929@freebsd.org> On Wed, Jun 08, 2011 at 11:08:36PM -0700, Eric Christopher wrote: > > On Jun 6, 2011, at 8:38 AM, Roman Divacky wrote: > > > OK to commit? Or is there a better way to distinguish those two > > asm dialects? > > Maybe check the Subtarget instead? Where do I get it in MCExpr? From fvbommel at gmail.com Thu Jun 9 02:50:37 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Thu, 9 Jun 2011 11:50:37 +0200 Subject: [llvm-commits] unsigned to uint32_t patch In-Reply-To: References: <2B6497C2-1D29-424C-AAA7-6681D540AD52@apple.com> Message-ID: On 9 June 2011 06:16, Jakub Staszak wrote: > Right :) Fixed patch attached. You need to #include "llvm/Support/DataTypes.h" in the header. Currently it's indirectly #included via this path: llvm/Analysis/BranchProbabilityInfo.h:18 llvm/Analysis/LoopInfo.h:34 llvm/Pass.h:368 llvm/PassSupport.h:27 llvm/Support/Atomic.h:17 llvm/Support/DataTypes.h but I don't think you should rely on that. From baldrick at free.fr Thu Jun 9 04:14:37 2011 From: baldrick at free.fr (Duncan Sands) Date: Thu, 09 Jun 2011 13:14:37 +0200 Subject: [llvm-commits] [llvm] r132649 - in /llvm/trunk: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp test/CodeGen/Generic/basic-promote-integers.ll In-Reply-To: <20110604205808.6551A2A6C12C@llvm.org> References: <20110604205808.6551A2A6C12C@llvm.org> Message-ID: <4DF0AB1D.8010308@free.fr> Hi Nadav, > TypeLegalizer: Add support for passing of vector-promoted types in registers (copyFromParts/copyToParts). I see several crashes on the attached testcase. > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Sat Jun 4 15:58:08 2011 > @@ -280,7 +280,28 @@ > } > > // Vector/Vector bitcast. > - return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); > + if (ValueVT.getSizeInBits() == PartVT.getSizeInBits()) > + return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); > + > + assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()&& > + "Cannot handle this kind of promotion"); > + // Promoted vector extract > + unsigned NumElts = ValueVT.getVectorNumElements(); > + SmallVector NewOps; > + for (unsigned i = 0; i< NumElts; ++i) { > + SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, > + PartVT.getScalarType(), Val ,DAG.getIntPtrConstant(i)); > + SDValue Cast; > + > + bool Smaller = ValueVT.bitsLE(PartVT); > + > + Cast = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), > + DL, ValueVT.getScalarType(), Ext); > + > + NewOps.push_back(Cast); > + } > + return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, > +&NewOps[0], NewOps.size()); > } Instead of scalarizing, and doing an element-by-element truncate, can't you just do a vector truncate (which should result in better code)? > @@ -452,7 +473,24 @@ > > //SDValue UndefElts = DAG.getUNDEF(VectorTy); > //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); > - } else { > + } else if (PartVT.isVector()&& > + PartVT.getVectorElementType().bitsGE( > + ValueVT.getVectorElementType())&& Missing space before && > + PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) { The code preceding this "if" is also for vectors. How about having an if (PartVT.isVector()) { // all the vector code goes here } and concentrate all the vector code inside it, set up the same way as in getCopyFromParts. Making the getCopyFromParts and getCopyToPartsVector code more similar makes them easier to compare. > + > + // Promoted vector extract > + unsigned NumElts = ValueVT.getVectorNumElements(); > + SmallVector NewOps; > + for (unsigned i = 0; i< NumElts; ++i) { > + SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, > + ValueVT.getScalarType(), Val ,DAG.getIntPtrConstant(i)); > + SDValue Cast = DAG.getNode(ISD::ANY_EXTEND, > + DL, PartVT.getScalarType(), Ext); > + NewOps.push_back(Cast); > + } > + Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, > +&NewOps[0], NewOps.size()); > + } else{ This could also be done with a vector any_extend, rather than scalarizing. Also, I don't know if a vector parameter can have the "zext" or "sext" attribute, but if they can then you should do the appropriate kind of extension here. Ciao, Duncan. -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: vparam.ll URL: From baldrick at free.fr Thu Jun 9 04:11:45 2011 From: baldrick at free.fr (Duncan Sands) Date: Thu, 09 Jun 2011 11:11:45 -0000 Subject: [llvm-commits] [llvm] r132774 - /llvm/trunk/lib/Target/TargetLibraryInfo.cpp Message-ID: <20110609111145.533572A6C12C@llvm.org> Author: baldrick Date: Thu Jun 9 06:11:45 2011 New Revision: 132774 URL: http://llvm.org/viewvc/llvm-project?rev=132774&view=rev Log: Enable printf() to iprintf() optimization for the TCE target. Patch by Pekka Jaaskelainen. Modified: llvm/trunk/lib/Target/TargetLibraryInfo.cpp Modified: llvm/trunk/lib/Target/TargetLibraryInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetLibraryInfo.cpp?rev=132774&r1=132773&r2=132774&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetLibraryInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetLibraryInfo.cpp Thu Jun 9 06:11:45 2011 @@ -38,8 +38,8 @@ TLI.setUnavailable(LibFunc::memset_pattern16); } - // iprintf and friends are only available on XCore. - if (T.getArch() != Triple::xcore) { + // iprintf and friends are only available on XCore and TCE. + if (T.getArch() != Triple::xcore && T.getArch() != Triple::tce) { TLI.setUnavailable(LibFunc::iprintf); TLI.setUnavailable(LibFunc::siprintf); TLI.setUnavailable(LibFunc::fiprintf); From baldrick at free.fr Thu Jun 9 04:17:40 2011 From: baldrick at free.fr (Duncan Sands) Date: Thu, 09 Jun 2011 13:17:40 +0200 Subject: [llvm-commits] [PATCH] enable printf() -> iprintf() optimization for TCE In-Reply-To: <4DECE20E.6010801@tut.fi> References: <4DECE20E.6010801@tut.fi> Message-ID: <4DF0ABD4.1090008@free.fr> > Attached trivial patch (applies both to 2.9 and trunk) enables printf() > to iprintf() optimization for the TCE target which uses Newlib and > benefits greatly from this optimization. Thanks - applied in commit 132774. Ciao, Duncan. From baldrick at free.fr Thu Jun 9 05:01:38 2011 From: baldrick at free.fr (Duncan Sands) Date: Thu, 09 Jun 2011 14:01:38 +0200 Subject: [llvm-commits] [llvm] r132689 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp lib/CodeGen/SelectionDAG/LegalizeTypes.h lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp test/CodeGen/Generic/basic-promote-integers.ll In-Reply-To: <20110606205557.1172E2A6C12C@llvm.org> References: <20110606205557.1172E2A6C12C@llvm.org> Message-ID: <4DF0B622.8030506@free.fr> Hi Nadav, > Add methods to support the integer-promotion of vector types. Methods to > legalize SDNodes such as BUILD_VECTOR, EXTRACT_VECTOR_ELT, etc. > --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Mon Jun 6 15:55:56 2011 > @@ -180,6 +191,10 @@ > if (NOutVT.bitsEq(NInVT)) > // The input promotes to the same size. Convert the promoted value. > return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); > + if (NInVT.isVector()) > + // Promote vector element via memory load/store. > + return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, > + CreateStackStoreLoad(InOp, OutVT)); What is this for? The break on the next line results in exactly this logic being executed (see the line after the end of the switch). > break; > +SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) { > + SDValue InOp0 = N->getOperand(0); > + EVT InVT = InOp0.getValueType(); > + EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); > + > + EVT OutVT = N->getValueType(0); > + EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); > + assert(NOutVT.isVector()&& "This type must be promoted to a vector type"); > + unsigned OutNumElems = N->getValueType(0).getVectorNumElements(); N->getValueType(0) -> OutVT > + EVT NOutVTElem = NOutVT.getVectorElementType(); > + > + DebugLoc dl = N->getDebugLoc(); > + SDValue BaseIdx = N->getOperand(1); > + > + SmallVector Ops; You know how many elements are going to be added, so you could reserve that much space here. > + for (unsigned i = 0; i != OutNumElems; ++i) { > + > + // Extract the element from the original vector. > + SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(), > + BaseIdx, DAG.getIntPtrConstant(i)); If BaseIdx.getValueType() is not the same as IntPtr type than this will crash. You should get "i" as a constant of type BaseIdx.getValueType(). > + SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, > + InVT.getVectorElementType(), N->getOperand(0), Index); > + > + SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext); > + // Insert the converted element to the new vector. > + Ops.push_back(Op); > + } > + > + return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT,&Ops[0], Ops.size()); > +} Another possible approach is to enhance EXTRACT_SUBVECTOR to allow the extracted subvector to have a wider element type than the original vector. I think this is useful because the processor may support that. For example I think on x86 you can do <4 x i32> -> <2 x i64> (grab first two elements) as one processor instruction. > +SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) { > + Pointless blank line. > + ShuffleVectorSDNode *SV = cast(N); > + EVT VT = N->getValueType(0); > + DebugLoc dl = N->getDebugLoc(); > + > + unsigned NumElts = VT.getVectorNumElements(); > + SmallVector NewMask; > + for (unsigned i = 0; i != NumElts; ++i) { > + NewMask.push_back(SV->getMaskElt(i)); > + } The mask doesn't change, so is there any point to this? Can't you just reuse the existing mask? If you can't access it (I don't recall how this works) then: (1) you can reserve space in NewMask because you know how many elements are going to be added; (2) no need for curly brackets in one-line "if". > + > + SDValue V0 = GetPromotedInteger(N->getOperand(0)); > + SDValue V1 = GetPromotedInteger(N->getOperand(1)); > + EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); There is no need to compute OutVT, since it is necessarily the type of V0 and V1, so you can just use V0.getValueType(). > + return DAG.getVectorShuffle(OutVT, dl, V0,V1,&NewMask[0]); Missing space after comma. > +SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) { > + Pointless blank line. > + SDValue InOp0 = N->getOperand(0); > + EVT InVT = InOp0.getValueType(); > + EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); > + > + EVT OutVT = N->getValueType(0); > + EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); > + assert(NOutVT.isVector()&& "This type must be promoted to a vector type"); > + unsigned NumElems = N->getNumOperands(); > + EVT NOutVTElem = NOutVT.getVectorElementType(); > + > + DebugLoc dl = N->getDebugLoc(); > + > + SmallVector Ops; You can reserve space here. > + for (unsigned i = 0; i != NumElems; ++i) { > + SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i)); > + Ops.push_back(Op); > + } > + > + return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT,&Ops[0], Ops.size()); Missing space after comma. > +} I'm wondering if this will always work correctly. Consider the case where the new vector type is (say) <2 x i128>, on a machine where i128 is not legal. Can this happen (maybe with AVX on x86?)? If so, probably BUILD_VECTOR needs to be generalized so that the input type can be smaller than the output element type. That said, I think your code is good enough for now. > +SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) { > + Pointless blank line. > + DebugLoc dl = N->getDebugLoc(); > + > + SDValue InOp0 = N->getOperand(0); > + EVT InVT = InOp0.getValueType(); > + EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); > + assert(!InVT.isVector()&& "Input must not be a scalar"); must not be a scalar -> must not be a vector > + > + EVT OutVT = N->getValueType(0); > + EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); > + assert(NOutVT.isVector()&& "This type must be promoted to a vector type"); > + EVT NOutVTElem = NOutVT.getVectorElementType(); > + > + SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0)); > + > + return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op); > +} This has the same potential problem as BUILD_VECTOR. > +SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) { > + Pointless blank line. > + SDValue InOp0 = N->getOperand(0); > + EVT InVT = InOp0.getValueType(); > + EVT InElVT = InVT.getVectorElementType(); > + EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); > + > + EVT OutVT = N->getValueType(0); > + EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); > + assert(NOutVT.isVector()&& "This type must be promoted to a vector type"); > + > + EVT NOutVTElem = NOutVT.getVectorElementType(); > + > + DebugLoc dl = N->getDebugLoc(); > + > + SDValue ConvertedVector = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, InOp0); Since the input vector is necessarily going to be promoted too, you should use GetPromotedInteger here. > + SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl, > + NOutVTElem, N->getOperand(1)); > + return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,NOutVT, Missing space after comma. > + ConvertedVector, ConvElem, N->getOperand(2)); > +} This may have a similar problem to BUILD_VECTOR (vector element type bigger than largest legal integer type). > +SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) { > + DebugLoc dl = N->getDebugLoc(); > + SDValue V0 = GetPromotedInteger(N->getOperand(0)); > + SDValue V1 = N->getOperand(1); > + SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, > + V0->getValueType(0).getScalarType(), V0, V1); > + > + return DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), Ext); In theory, the return type could be larger than the element type of the new vector (see the definition of EXTRACT_VECTOR_ELT), in which case this truncate would assert. > + > +} > + > +SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) { > + Pointless blank line. > + DebugLoc dl = N->getDebugLoc(); > + > + EVT RetSclrTy = N->getValueType(0).getVectorElementType(); > + > + SmallVector NewOps; You could reserve space here. > + > + // For each incoming vector > + for (unsigned VecIdx = 0, E = N->getNumOperands(); VecIdx!= E; ++VecIdx) { Missing space after VecIdx. > + SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx)); > + EVT SclrTy = Incoming->getValueType(0).getVectorElementType(); > + unsigned NumElem = Incoming->getValueType(0).getVectorNumElements(); > + > + for (unsigned i=0; i + // Extract element from incoming vector > + SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, > + Incoming, DAG.getIntPtrConstant(i)); > + SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex); > + NewOps.push_back(Tr); > + } > + } > + > + return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0), > +&NewOps[0], NewOps.size()); > + } Rather than scalarizing, the definition of CONCAT_VECTORS could be enhanced to allow the input vectors to have wider elements than the output vectors. This would probably result in better code for, eg, concat <2 x i32>, <2 x i32> on x86, since I think you can get pretty nice vector code on x86 that combines and truncates two <2 x i64> into one <4 x i32>. > --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Mon Jun 6 15:55:56 2011 > @@ -783,6 +783,17 @@ > DAG.getIntPtrConstant(InNVT.getVectorNumElements())); > break; > } > + case TargetLowering::TypePromoteInteger: { > + SDValue InOp = GetPromotedInteger(N->getOperand(0)); > + EVT InNVT = EVT::getVectorVT(*DAG.getContext(), > + InOp.getValueType().getVectorElementType(), > + LoVT.getVectorNumElements()); > + Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, > + DAG.getIntPtrConstant(0)); > + Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, > + DAG.getIntPtrConstant(InNVT.getVectorNumElements())); > + break; > + } > case TargetLowering::TypeSplitVector: > GetSplitVector(N->getOperand(0), Lo, Hi); > break; The entire switch here is kind of pointless. The code for the TypeLegal case should always work (the legalizer will then need to legalize the created EXTRACT_SUBVECTOR, but that's OK), so this is at best a small compile time speedup, which I don't think it is worth all the extra code. Ciao, Duncan. From rafael.espindola at gmail.com Thu Jun 9 07:38:09 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 09 Jun 2011 14:38:09 -0000 Subject: [llvm-commits] [llvm] r132775 - /llvm/trunk/lib/Transforms/IPO/ExtractGV.cpp Message-ID: <20110609143809.AB6A62A6C12C@llvm.org> Author: rafael Date: Thu Jun 9 09:38:09 2011 New Revision: 132775 URL: http://llvm.org/viewvc/llvm-project?rev=132775&view=rev Log: Improve the handling of available_externally and llvm.global_ctors. Modified: llvm/trunk/lib/Transforms/IPO/ExtractGV.cpp Modified: llvm/trunk/lib/Transforms/IPO/ExtractGV.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/ExtractGV.cpp?rev=132775&r1=132774&r2=132775&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/ExtractGV.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/ExtractGV.cpp Thu Jun 9 09:38:09 2011 @@ -51,20 +51,32 @@ // Visit the GlobalVariables. for (Module::global_iterator I = M.global_begin(), E = M.global_end(); I != E; ++I) { + if (deleteStuff == (bool)Named.count(I) && !I->isDeclaration()) { + I->setInitializer(0); + } else { + if (I->hasAvailableExternallyLinkage()) + continue; + if (I->getName() == "llvm.global_ctors") + continue; + } + if (I->hasLocalLinkage()) I->setVisibility(GlobalValue::HiddenVisibility); I->setLinkage(GlobalValue::ExternalLinkage); - if (deleteStuff == (bool)Named.count(I) && !I->isDeclaration()) - I->setInitializer(0); } // Visit the Functions. for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) { + if (deleteStuff == (bool)Named.count(I) && !I->isDeclaration()) { + I->deleteBody(); + } else { + if (I->hasAvailableExternallyLinkage()) + continue; + } + if (I->hasLocalLinkage()) I->setVisibility(GlobalValue::HiddenVisibility); I->setLinkage(GlobalValue::ExternalLinkage); - if (deleteStuff == (bool)Named.count(I) && !I->isDeclaration()) - I->deleteBody(); } return true; From echristo at apple.com Thu Jun 9 08:39:01 2011 From: echristo at apple.com (Eric Christopher) Date: Thu, 09 Jun 2011 15:39:01 -0000 Subject: [llvm-commits] [llvm] r132776 - in /llvm/trunk: lib/CodeGen/CallingConvLower.cpp test/CodeGen/X86/byval-align.ll Message-ID: <20110609153901.613812A6C12C@llvm.org> Author: echristo Date: Thu Jun 9 10:39:01 2011 New Revision: 132776 URL: http://llvm.org/viewvc/llvm-project?rev=132776&view=rev Log: Recommit r132764 since it didn't cause the windows buildbot failures. Added: llvm/trunk/test/CodeGen/X86/byval-align.ll - copied unchanged from r132770, llvm/trunk/test/CodeGen/X86/byval-align.ll Modified: llvm/trunk/lib/CodeGen/CallingConvLower.cpp Modified: llvm/trunk/lib/CodeGen/CallingConvLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CallingConvLower.cpp?rev=132776&r1=132775&r2=132776&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CallingConvLower.cpp (original) +++ llvm/trunk/lib/CodeGen/CallingConvLower.cpp Thu Jun 9 10:39:01 2011 @@ -49,6 +49,8 @@ Size = MinSize; if (MinAlign > (int)Align) Align = MinAlign; + if (MF.getFrameInfo()->getMaxAlignment() < Align) + MF.getFrameInfo()->setMaxAlignment(Align); TM.getTargetLowering()->HandleByVal(const_cast(this), Size); unsigned Offset = AllocateStack(Size, Align); addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); From echristo at apple.com Thu Jun 9 09:03:20 2011 From: echristo at apple.com (Eric Christopher) Date: Thu, 09 Jun 2011 16:03:20 -0000 Subject: [llvm-commits] [llvm] r132777 - in /llvm/trunk: lib/Target/Mips/MipsAsmPrinter.cpp lib/Target/Mips/MipsISelDAGToDAG.cpp lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsISelLowering.h lib/Target/Mips/MipsInstrInfo.td lib/Target/Mips/MipsMachineFunction.h lib/Target/Mips/MipsRegisterInfo.cpp test/CodeGen/Mips/alloca.ll test/CodeGen/Mips/inlineasmmemop.ll Message-ID: <20110609160320.2F9EA2A6C12C@llvm.org> Author: echristo Date: Thu Jun 9 11:03:19 2011 New Revision: 132777 URL: http://llvm.org/viewvc/llvm-project?rev=132777&view=rev Log: Speculatively revert 132758 and 132768 to try to fix the Windows buildbots. Removed: llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.h llvm/trunk/lib/Target/Mips/MipsInstrInfo.td llvm/trunk/lib/Target/Mips/MipsMachineFunction.h llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp llvm/trunk/test/CodeGen/Mips/alloca.ll Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=132777&r1=132776&r2=132777&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Thu Jun 9 11:03:19 2011 @@ -56,9 +56,6 @@ bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O); - bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, - unsigned AsmVariant, const char *ExtraCode, - raw_ostream &O); void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O); void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O); void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O, @@ -307,19 +304,6 @@ return false; } -bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, - unsigned OpNum, unsigned AsmVariant, - const char *ExtraCode, - raw_ostream &O) { - if (ExtraCode && ExtraCode[0]) - return true; // Unknown modifier. - - const MachineOperand &MO = MI->getOperand(OpNum); - assert(MO.isReg() && "unexpected inline asm memory operand"); - O << "0($" << MipsAsmPrinter::getRegisterName(MO.getReg()) << ")"; - return false; -} - void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum, raw_ostream &O) { const MachineOperand &MO = MI->getOperand(opNum); Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=132777&r1=132776&r2=132777&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Thu Jun 9 11:03:19 2011 @@ -94,10 +94,6 @@ inline SDValue getI32Imm(unsigned Imm) { return CurDAG->getTargetConstant(Imm, MVT::i32); } - - virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, - char ConstraintCode, - std::vector &OutOps); }; } @@ -466,14 +462,6 @@ return ResNode; } -bool MipsDAGToDAGISel:: -SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, - std::vector &OutOps) { - assert(ConstraintCode == 'm' && "unexpected asm memory constraint"); - OutOps.push_back(Op); - return false; -} - /// createMipsISelDag - This pass converts a legalized DAG into a /// MIPS-specific DAG, ready for instruction scheduling. FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) { Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=132777&r1=132776&r2=132777&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Thu Jun 9 11:03:19 2011 @@ -59,7 +59,6 @@ case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; case MipsISD::WrapperPIC: return "MipsISD::WrapperPIC"; - case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; default: return NULL; } } @@ -1190,9 +1189,6 @@ SDValue MipsTargetLowering:: LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const { - MachineFunction &MF = DAG.getMachineFunction(); - MipsFunctionInfo *MipsFI = MF.getInfo(); - unsigned StackAlignment = getTargetMachine().getFrameLowering()->getStackAlignment(); assert(StackAlignment >= @@ -1215,14 +1211,24 @@ // must be placed in the stack pointer register. Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub, SDValue()); + // Retrieve updated $sp. There is a glue input to prevent instructions that + // clobber $sp from being inserted between copytoreg and copyfromreg. + SDValue NewSP = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32, + Chain.getValue(1)); + + // The stack space reserved by alloca is located right above the argument + // area. It is aligned on a boundary that is a multiple of StackAlignment. + MachineFunction &MF = DAG.getMachineFunction(); + MipsFunctionInfo *MipsFI = MF.getInfo(); + unsigned SPOffset = (MipsFI->getMaxCallFrameSize() + StackAlignment - 1) / + StackAlignment * StackAlignment; + SDValue AllocPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP, + DAG.getConstant(SPOffset, MVT::i32)); // This node always has two return values: a new stack pointer // value and a chain - SDVTList VTLs = DAG.getVTList(MVT::i32, MVT::Other); - SDValue Ptr = DAG.getFrameIndex(MipsFI->getDynAllocFI(), getPointerTy()); - SDValue Ops[] = { Chain, Ptr, Chain.getValue(1) }; - - return DAG.getNode(MipsISD::DynAlloc, dl, VTLs, Ops, 3); + SDValue Ops[2] = { AllocPtr, NewSP.getValue(1) }; + return DAG.getMergeValues(Ops, 2, dl); } SDValue MipsTargetLowering:: @@ -1764,10 +1770,6 @@ if (IsPIC && !MipsFI->getGPFI()) MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true)); - // Get the frame index of the stack frame object that points to the location - // of dynamically allocated area on the stack. - int DynAllocFI = MipsFI->getDynAllocFI(); - // Update size of the maximum argument space. // For O32, a minimum of four words (16 bytes) of argument space is // allocated. @@ -1779,17 +1781,14 @@ if (MaxCallFrameSize < NextStackOffset) { MipsFI->setMaxCallFrameSize(NextStackOffset); - // Set the offsets relative to $sp of the $gp restore slot and dynamically - // allocated stack space. These offsets must be aligned to a boundary - // determined by the stack alignment of the ABI. - unsigned StackAlignment = TFL->getStackAlignment(); - NextStackOffset = (NextStackOffset + StackAlignment - 1) / - StackAlignment * StackAlignment; - - if (IsPIC) - MFI->setObjectOffset(MipsFI->getGPFI(), NextStackOffset); - - MFI->setObjectOffset(DynAllocFI, NextStackOffset); + if (IsPIC) { + // $gp restore slot must be aligned. + unsigned StackAlignment = TFL->getStackAlignment(); + NextStackOffset = (NextStackOffset + StackAlignment - 1) / + StackAlignment * StackAlignment; + int GPFI = MipsFI->getGPFI(); + MFI->setObjectOffset(GPFI, NextStackOffset); + } } // With EABI is it possible to have 16 args on registers. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=132777&r1=132776&r2=132777&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Thu Jun 9 11:03:19 2011 @@ -79,9 +79,7 @@ BuildPairF64, ExtractElementF64, - WrapperPIC, - - DynAlloc + WrapperPIC }; } Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=132777&r1=132776&r2=132777&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Thu Jun 9 11:03:19 2011 @@ -39,9 +39,6 @@ def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; -def SDT_MipsDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, - SDTCisVT<1, iPTR>]>; - // Call def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, @@ -102,10 +99,6 @@ def MipsWrapperPIC : SDNode<"MipsISD::WrapperPIC", SDTIntUnaryOp>; -// Pointer to dynamically allocated stack area. -def MipsDynAlloc : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc, - [SDNPHasChain, SDNPInGlue]>; - //===----------------------------------------------------------------------===// // Mips Instruction Predicate Definitions. //===----------------------------------------------------------------------===// @@ -682,12 +675,6 @@ // can be matched. It's similar to Sparc LEA_ADDRi def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">; -// DynAlloc node points to dynamically allocated stack space. -// $sp is added to the list of implicitly used registers to prevent dead code -// elimination from removing instructions that modify $sp. -let Uses = [SP] in -def DynAlloc : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">; - // MADD*/MSUB* def MADD : MArithR<0, "madd", MipsMAdd, 1>; def MADDU : MArithR<1, "maddu", MipsMAddu, 1>; @@ -865,9 +852,6 @@ def : Pat<(setuge CPURegs:$lhs, immSExt16:$rhs), (XORi (SLTiu CPURegs:$lhs, immSExt16:$rhs), 1)>; -// select MipsDynAlloc -def : Pat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>; - //===----------------------------------------------------------------------===// // Floating Point Support //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/Mips/MipsMachineFunction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMachineFunction.h?rev=132777&r1=132776&r2=132777&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsMachineFunction.h (original) +++ llvm/trunk/lib/Target/Mips/MipsMachineFunction.h Thu Jun 9 11:03:19 2011 @@ -27,7 +27,6 @@ class MipsFunctionInfo : public MachineFunctionInfo { private: - MachineFunction& MF; /// SRetReturnReg - Some subtargets require that sret lowering includes /// returning the value of the returned struct in a register. This field /// holds the virtual register into which the sret argument is passed. @@ -48,7 +47,6 @@ // LowerCall except for the frame object for restoring $gp. std::pair InArgFIRange, OutArgFIRange; int GPFI; // Index of the frame object for restoring $gp - mutable int DynAllocFI; // Frame index of dynamically allocated stack area. unsigned MaxCallFrameSize; /// AtomicFrameIndex - To implement atomic.swap and atomic.cmp.swap @@ -57,10 +55,10 @@ int AtomicFrameIndex; public: MipsFunctionInfo(MachineFunction& MF) - : MF(MF), SRetReturnReg(0), GlobalBaseReg(0), + : SRetReturnReg(0), GlobalBaseReg(0), VarArgsFrameIndex(0), InArgFIRange(std::make_pair(-1, 0)), - OutArgFIRange(std::make_pair(-1, 0)), GPFI(0), DynAllocFI(0), - MaxCallFrameSize(0), AtomicFrameIndex(-1) + OutArgFIRange(std::make_pair(-1, 0)), GPFI(0), MaxCallFrameSize(0), + AtomicFrameIndex(-1) {} bool isInArgFI(int FI) const { @@ -83,16 +81,6 @@ bool needGPSaveRestore() const { return getGPFI(); } bool isGPFI(int FI) const { return GPFI && GPFI == FI; } - // The first call to this function creates a frame object for dynamically - // allocated stack area. - int getDynAllocFI() const { - if (!DynAllocFI) - DynAllocFI = MF.getFrameInfo()->CreateFixedObject(4, 0, true); - - return DynAllocFI; - } - bool isDynAllocFI(int FI) const { return DynAllocFI && DynAllocFI == FI; } - unsigned getSRetReturnReg() const { return SRetReturnReg; } void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=132777&r1=132776&r2=132777&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Thu Jun 9 11:03:19 2011 @@ -177,14 +177,12 @@ int Offset; // Calculate final offset. - // - There is no need to change the offset if the frame object is one of the - // following: an outgoing argument, pointer to a dynamically allocated - // stack space or a $gp restore location, + // - There is no need to change the offset if the frame object is an outgoing + // argument or a $gp restore location, // - If the frame object is any of the following, its offset must be adjusted // by adding the size of the stack: // incoming argument, callee-saved register location or local variable. - if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isGPFI(FrameIndex) || - MipsFI->isDynAllocFI(FrameIndex)) + if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isGPFI(FrameIndex)) Offset = spOffset; else Offset = spOffset + stackSize; @@ -213,7 +211,7 @@ // 3. Locations for callee-saved registers. // Everything else is referenced relative to whatever register // getFrameRegister() returns. - if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isDynAllocFI(FrameIndex) || + if (MipsFI->isOutArgFI(FrameIndex) || (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI)) FrameReg = Mips::SP; else Modified: llvm/trunk/test/CodeGen/Mips/alloca.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/alloca.ll?rev=132777&r1=132776&r2=132777&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/alloca.ll (original) +++ llvm/trunk/test/CodeGen/Mips/alloca.ll Thu Jun 9 11:03:19 2011 @@ -4,15 +4,15 @@ entry: ; CHECK: subu $[[T0:[0-9]+]], $sp, $[[SZ:[0-9]+]] ; CHECK: addu $sp, $zero, $[[T0]] -; CHECK: addiu $[[T1:[0-9]+]], $sp, [[OFF:[0-9]+]] -; CHECK: subu $[[T2:[0-9]+]], $sp, $[[SZ]] -; CHECK: addu $sp, $zero, $[[T2]] -; CHECK: addiu $[[T3:[0-9]+]], $sp, [[OFF]] +; CHECK: addu $[[SP1:[0-9]+]], $zero, $sp +; CHECK: subu $[[T1:[0-9]+]], $sp, $[[SZ]] +; CHECK: addu $sp, $zero, $[[T1]] +; CHECK: addu $[[SP2:[0-9]+]], $zero, $sp ; CHECK: lw $25, %call16(foo)($gp) -; CHECK: addu $4, $zero, $[[T1]] +; CHECK: addiu $4, $[[SP1]], 24 ; CHECK: jalr $25 ; CHECK: lw $25, %call16(foo)($gp) -; CHECK: addu $4, $zero, $[[T3]] +; CHECK: addiu $4, $[[SP2]], 24 ; CHECK: jalr $25 %tmp1 = alloca i8, i32 %size, align 4 %add.ptr = getelementptr inbounds i8* %tmp1, i32 5 @@ -29,72 +29,3 @@ declare i32 @foo(i8*) - at .str = private unnamed_addr constant [22 x i8] c"%d %d %d %d %d %d %d\0A\00", align 1 - -define i32 @alloca2(i32 %size) nounwind { -entry: -; dynamic allocated stack area and $gp restore slot have the same offsets -; relative to $sp. -; -; CHECK: alloca2 -; CHECK: .cprestore [[OFF:[0-9]+]] -; CHECK: subu $[[T0:[0-9]+]], $sp, $[[SZ:[0-9]+]] -; CHECK: addu $sp, $zero, $[[T0]] -; CHECK: addiu $[[T1:[0-9]+]], $sp, [[OFF]] - - %tmp1 = alloca i8, i32 %size, align 4 - %0 = bitcast i8* %tmp1 to i32* - %cmp = icmp sgt i32 %size, 10 - br i1 %cmp, label %if.then, label %if.else - -if.then: ; preds = %entry -; CHECK: addiu $4, $[[T1]], 40 - - %add.ptr = getelementptr inbounds i8* %tmp1, i32 40 - %1 = bitcast i8* %add.ptr to i32* - call void @foo3(i32* %1) nounwind - %arrayidx15.pre = getelementptr inbounds i8* %tmp1, i32 12 - %.pre = bitcast i8* %arrayidx15.pre to i32* - br label %if.end - -if.else: ; preds = %entry -; CHECK: addiu $4, $[[T1]], 12 - - %add.ptr5 = getelementptr inbounds i8* %tmp1, i32 12 - %2 = bitcast i8* %add.ptr5 to i32* - call void @foo3(i32* %2) nounwind - br label %if.end - -if.end: ; preds = %if.else, %if.then -; CHECK: lw $5, 0($[[T1]]) -; CHECK: lw $25, %call16(printf) - - %.pre-phi = phi i32* [ %2, %if.else ], [ %.pre, %if.then ] - %tmp7 = load i32* %0, align 4, !tbaa !0 - %arrayidx9 = getelementptr inbounds i8* %tmp1, i32 4 - %3 = bitcast i8* %arrayidx9 to i32* - %tmp10 = load i32* %3, align 4, !tbaa !0 - %arrayidx12 = getelementptr inbounds i8* %tmp1, i32 8 - %4 = bitcast i8* %arrayidx12 to i32* - %tmp13 = load i32* %4, align 4, !tbaa !0 - %tmp16 = load i32* %.pre-phi, align 4, !tbaa !0 - %arrayidx18 = getelementptr inbounds i8* %tmp1, i32 16 - %5 = bitcast i8* %arrayidx18 to i32* - %tmp19 = load i32* %5, align 4, !tbaa !0 - %arrayidx21 = getelementptr inbounds i8* %tmp1, i32 20 - %6 = bitcast i8* %arrayidx21 to i32* - %tmp22 = load i32* %6, align 4, !tbaa !0 - %arrayidx24 = getelementptr inbounds i8* %tmp1, i32 24 - %7 = bitcast i8* %arrayidx24 to i32* - %tmp25 = load i32* %7, align 4, !tbaa !0 - %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([22 x i8]* @.str, i32 0, i32 0), i32 %tmp7, i32 %tmp10, i32 %tmp13, i32 %tmp16, i32 %tmp19, i32 %tmp22, i32 %tmp25) nounwind - ret i32 0 -} - -declare void @foo3(i32*) - -declare i32 @printf(i8* nocapture, ...) nounwind - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} Removed: llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll?rev=132776&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll (original) +++ llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll (removed) @@ -1,23 +0,0 @@ -; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s - - at g1 = external global i32 - -define i32 @f1(i32 %x) nounwind { -entry: -; CHECK: addiu $[[T0:[0-9]+]], $sp -; CHECK: #APP -; CHECK: sw $4, 0($[[T0]]) -; CHECK: #NO_APP -; CHECK: lw $[[T1:[0-9]+]], %got(g1)($gp) -; CHECK: #APP -; CHECK: lw $[[T3:[0-9]+]], 0($[[T0]]) -; CHECK: #NO_APP -; CHECK: sw $[[T3]], 0($[[T1]]) - - %l1 = alloca i32, align 4 - call void asm "sw $1, $0", "=*m,r"(i32* %l1, i32 %x) nounwind - %0 = call i32 asm "lw $0, $1", "=r,*m"(i32* %l1) nounwind - store i32 %0, i32* @g1, align 4 - ret i32 %0 -} - From aggarwa4 at illinois.edu Thu Jun 9 09:20:21 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Thu, 09 Jun 2011 16:20:21 -0000 Subject: [llvm-commits] [poolalloc] r132779 - /poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Message-ID: <20110609162021.488CB2A6C12C@llvm.org> Author: aggarwa4 Date: Thu Jun 9 11:20:21 2011 New Revision: 132779 URL: http://llvm.org/viewvc/llvm-project?rev=132779&view=rev Log: Make sure the debug messages are before a return statement. Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c?rev=132779&r1=132778&r2=132779&view=diff ============================================================================== --- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c (original) +++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Thu Jun 9 11:20:21 2011 @@ -146,6 +146,10 @@ uintptr_t p = maskAddress(ptr); assert(p + size < SIZE); +#if DEBUG + printf("Load: %p, %p = actual: %u, expect: %u | %lu bytes %d \n", ptr, (void *)p, typeNumber, shadow_begin[p], size, tag); +#endif + /* Check if this an initialized but untyped memory.*/ if (typeNumber != shadow_begin[p]) { if (shadow_begin[p] != 0xFF) { @@ -171,10 +175,6 @@ break; } } -#if DEBUG - printf("Load: %p, %p = actual: %u, expect: %u | %lu bytes %d \n", ptr, (void *)p, typeNumber, shadow_begin[p], size, tag); -#endif - } /** From stoklund at 2pi.dk Thu Jun 9 09:56:59 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 09 Jun 2011 16:56:59 -0000 Subject: [llvm-commits] [llvm] r132781 - in /llvm/trunk/lib/Target: Alpha/AlphaRegisterInfo.td Blackfin/BlackfinRegisterInfo.td CellSPU/SPURegisterInfo.td MBlaze/MBlazeRegisterInfo.td MSP430/MSP430RegisterInfo.cpp MSP430/MSP430RegisterInfo.td Mips/MipsRegisterInfo.cpp Mips/MipsRegisterInfo.td PowerPC/PPCRegisterInfo.td Sparc/SparcRegisterInfo.cpp Sparc/SparcRegisterInfo.td X86/X86RegisterInfo.cpp X86/X86RegisterInfo.td XCore/XCoreRegisterInfo.td Message-ID: <20110609165659.56EAD2A6C12C@llvm.org> Author: stoklund Date: Thu Jun 9 11:56:59 2011 New Revision: 132781 URL: http://llvm.org/viewvc/llvm-project?rev=132781&view=rev Log: Remove custom allocation order boilerplate that is no longer needed. The register allocators automatically filter out reserved registers and place the callee saved registers last in the allocation order, so custom methods are no longer necessary just for that. Some targets still use custom allocation orders: ARM/Thumb: The high registers are removed from GPR in thumb mode. The NEON allocation orders prefer to use non-VFP2 registers first. X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble. SystemZ: Some of the allocation orders are omitting R12 aliases without explanation. I don't understand this target well enough to fix that. It looks like all the boilerplate could be removed by reserving the right registers. Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.td llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.td llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.td llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.td llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp llvm/trunk/lib/Target/X86/X86RegisterInfo.td llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.td Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.td?rev=132781&r1=132780&r2=132781&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.td (original) +++ llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.td Thu Jun 9 11:56:59 2011 @@ -121,51 +121,18 @@ // Non-volatile R9, R10, R11, R12, R13, R14, // Don't allocate 15, 30, 31 - R15, R30, R31 ]> //zero -{ - let MethodProtos = [{ - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - GPRCClass::iterator - GPRCClass::allocation_order_end(const MachineFunction &MF) const { - return end()-3; - } - }]; -} + R15, R30, R31 ]>; //zero def F4RC : RegisterClass<"Alpha", [f32], 64, [F0, F1, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, // Saved: F2, F3, F4, F5, F6, F7, F8, F9, - F31 ]> //zero -{ - let MethodProtos = [{ - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - F4RCClass::iterator - F4RCClass::allocation_order_end(const MachineFunction &MF) const { - return end()-1; - } - }]; -} + F31 ]>; //zero def F8RC : RegisterClass<"Alpha", [f64], 64, [F0, F1, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, // Saved: F2, F3, F4, F5, F6, F7, F8, F9, - F31 ]> //zero -{ - let MethodProtos = [{ - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - F8RCClass::iterator - F8RCClass::allocation_order_end(const MachineFunction &MF) const { - return end()-1; - } - }]; -} + F31 ]>; //zero Modified: llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td?rev=132781&r1=132780&r2=132781&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td Thu Jun 9 11:56:59 2011 @@ -245,18 +245,6 @@ def P : RegisterClass<"BF", [i32], 32, [P0, P1, P2, P3, P4, P5, FP, SP]> { let SubRegClasses = [(P16L lo16), (P16H hi16)]; - let MethodProtos = [{ - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - PClass::iterator - PClass::allocation_order_end(const MachineFunction &MF) const { - const TargetMachine &TM = MF.getTarget(); - const TargetFrameLowering *TFI = TM.getFrameLowering(); - return allocation_order_begin(MF) - + (TFI->hasFP(MF) ? 7 : 6); - } - }]; } def I : RegisterClass<"BF", [i32], 32, [I0, I1, I2, I3]>; @@ -268,18 +256,6 @@ [R0, R1, R2, R3, R4, R5, R6, R7, P0, P1, P2, P3, P4, P5, FP, SP]> { let SubRegClasses = [(DP16L lo16), (DP16H hi16)]; - let MethodProtos = [{ - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - DPClass::iterator - DPClass::allocation_order_end(const MachineFunction &MF) const { - const TargetMachine &TM = MF.getTarget(); - const TargetFrameLowering *TFI = TM.getFrameLowering(); - return allocation_order_begin(MF) - + (TFI->hasFP(MF) ? 15 : 14); - } - }]; } def GR : RegisterClass<"BF", [i32], 32, @@ -287,20 +263,7 @@ P0, P1, P2, P3, P4, P5, I0, I1, I2, I3, M0, M1, M2, M3, B0, B1, B2, B3, L0, L1, L2, L3, - FP, SP]> { - let MethodProtos = [{ - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - GRClass::iterator - GRClass::allocation_order_end(const MachineFunction &MF) const { - const TargetMachine &TM = MF.getTarget(); - const TargetFrameLowering *TFI = TM.getFrameLowering(); - return allocation_order_begin(MF) - + (TFI->hasFP(MF) ? 31 : 30); - } - }]; -} + FP, SP]>; def ALL : RegisterClass<"BF", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, R7, @@ -310,36 +273,10 @@ FP, SP, A0X, A0W, A1X, A1W, ASTAT, RETS, LC0, LT0, LB0, LC1, LT1, LB1, CYCLES, CYCLES2, - USP, SEQSTAT, SYSCFG, RETI, RETX, RETN, RETE, EMUDAT]> { - let MethodProtos = [{ - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - ALLClass::iterator - ALLClass::allocation_order_end(const MachineFunction &MF) const { - const TargetMachine &TM = MF.getTarget(); - const TargetFrameLowering *TFI = TM.getFrameLowering(); - return allocation_order_begin(MF) - + (TFI->hasFP(MF) ? 31 : 30); - } - }]; -} + USP, SEQSTAT, SYSCFG, RETI, RETX, RETN, RETE, EMUDAT]>; def PI : RegisterClass<"BF", [i32], 32, - [P0, P1, P2, P3, P4, P5, I0, I1, I2, I3, FP, SP]> { - let MethodProtos = [{ - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - PIClass::iterator - PIClass::allocation_order_end(const MachineFunction &MF) const { - const TargetMachine &TM = MF.getTarget(); - const TargetFrameLowering *TFI = TM.getFrameLowering(); - return allocation_order_begin(MF) - + (TFI->hasFP(MF) ? 11 : 10); - } - }]; -} + [P0, P1, P2, P3, P4, P5, I0, I1, I2, I3, FP, SP]>; // We are going to pretend that CC and !CC are 32-bit registers, even though // they only can hold 1 bit. Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.td?rev=132781&r1=132780&r2=132781&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.td (original) +++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.td Thu Jun 9 11:56:59 2011 @@ -170,23 +170,7 @@ R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87, R86, R85, R84, R83, R82, R81, R80, /* environment ptr, SP, LR */ - R2, R1, R0 ]> -{ - let MethodProtos = [{ - iterator allocation_order_begin(const MachineFunction &MF) const; - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - GPRCClass::iterator - GPRCClass::allocation_order_begin(const MachineFunction &MF) const { - return begin(); - } - GPRCClass::iterator - GPRCClass::allocation_order_end(const MachineFunction &MF) const { - return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr) - } - }]; -} + R2, R1, R0 ]>; // The SPU's registers as 64-bit wide (double word integer) "preferred slot": def R64C : RegisterClass<"SPU", [i64], 128, @@ -204,23 +188,7 @@ R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87, R86, R85, R84, R83, R82, R81, R80, /* environment ptr, SP, LR */ - R2, R1, R0 ]> -{ - let MethodProtos = [{ - iterator allocation_order_begin(const MachineFunction &MF) const; - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - R64CClass::iterator - R64CClass::allocation_order_begin(const MachineFunction &MF) const { - return begin(); - } - R64CClass::iterator - R64CClass::allocation_order_end(const MachineFunction &MF) const { - return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr) - } - }]; -} + R2, R1, R0 ]>; // The SPU's registers as 64-bit wide (double word) FP "preferred slot": def R64FP : RegisterClass<"SPU", [f64], 128, @@ -238,23 +206,7 @@ R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87, R86, R85, R84, R83, R82, R81, R80, /* environment ptr, SP, LR */ - R2, R1, R0 ]> -{ - let MethodProtos = [{ - iterator allocation_order_begin(const MachineFunction &MF) const; - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - R64FPClass::iterator - R64FPClass::allocation_order_begin(const MachineFunction &MF) const { - return begin(); - } - R64FPClass::iterator - R64FPClass::allocation_order_end(const MachineFunction &MF) const { - return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr) - } - }]; -} + R2, R1, R0 ]>; // The SPU's registers as 32-bit wide (word) "preferred slot": def R32C : RegisterClass<"SPU", [i32], 128, @@ -272,23 +224,7 @@ R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87, R86, R85, R84, R83, R82, R81, R80, /* environment ptr, SP, LR */ - R2, R1, R0 ]> -{ - let MethodProtos = [{ - iterator allocation_order_begin(const MachineFunction &MF) const; - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - R32CClass::iterator - R32CClass::allocation_order_begin(const MachineFunction &MF) const { - return begin(); - } - R32CClass::iterator - R32CClass::allocation_order_end(const MachineFunction &MF) const { - return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr) - } - }]; -} + R2, R1, R0 ]>; // The SPU's registers as single precision floating point "preferred slot": def R32FP : RegisterClass<"SPU", [f32], 128, @@ -306,23 +242,7 @@ R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87, R86, R85, R84, R83, R82, R81, R80, /* environment ptr, SP, LR */ - R2, R1, R0 ]> -{ - let MethodProtos = [{ - iterator allocation_order_begin(const MachineFunction &MF) const; - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - R32FPClass::iterator - R32FPClass::allocation_order_begin(const MachineFunction &MF) const { - return begin(); - } - R32FPClass::iterator - R32FPClass::allocation_order_end(const MachineFunction &MF) const { - return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr) - } - }]; -} + R2, R1, R0 ]>; // The SPU's registers as 16-bit wide (halfword) "preferred slot": def R16C : RegisterClass<"SPU", [i16], 128, @@ -340,23 +260,7 @@ R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87, R86, R85, R84, R83, R82, R81, R80, /* environment ptr, SP, LR */ - R2, R1, R0 ]> -{ - let MethodProtos = [{ - iterator allocation_order_begin(const MachineFunction &MF) const; - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - R16CClass::iterator - R16CClass::allocation_order_begin(const MachineFunction &MF) const { - return begin(); - } - R16CClass::iterator - R16CClass::allocation_order_end(const MachineFunction &MF) const { - return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr) - } - }]; -} + R2, R1, R0 ]>; // The SPU's registers as 8-bit wide (byte) "preferred slot": def R8C : RegisterClass<"SPU", [i8], 128, @@ -374,23 +278,7 @@ R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87, R86, R85, R84, R83, R82, R81, R80, /* environment ptr, SP, LR */ - R2, R1, R0 ]> -{ - let MethodProtos = [{ - iterator allocation_order_begin(const MachineFunction &MF) const; - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - R8CClass::iterator - R8CClass::allocation_order_begin(const MachineFunction &MF) const { - return begin(); - } - R8CClass::iterator - R8CClass::allocation_order_end(const MachineFunction &MF) const { - return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr) - } - }]; -} + R2, R1, R0 ]>; // The SPU's registers as vector registers: def VECREG : RegisterClass<"SPU", @@ -410,20 +298,4 @@ R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87, R86, R85, R84, R83, R82, R81, R80, /* environment ptr, SP, LR */ - R2, R1, R0 ]> -{ - let MethodProtos = [{ - iterator allocation_order_begin(const MachineFunction &MF) const; - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - VECREGClass::iterator - VECREGClass::allocation_order_begin(const MachineFunction &MF) const { - return begin(); - } - VECREGClass::iterator - VECREGClass::allocation_order_end(const MachineFunction &MF) const { - return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr) - } - }]; -} + R2, R1, R0 ]>; Modified: llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.td?rev=132781&r1=132780&r2=132781&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.td (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.td Thu Jun 9 11:56:59 2011 @@ -131,19 +131,7 @@ R17, // Return address for exceptions R18, // Reserved for assembler R19 // The frame-pointer - ]> -{ - let MethodProtos = [{ - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - GPRClass::iterator - GPRClass::allocation_order_end(const MachineFunction &MF) const { - // The last 10 registers on the list above are reserved - return end()-10; - } - }]; -} + ]>; def SPR : RegisterClass<"MBlaze", [i32], 32, [ @@ -174,16 +162,8 @@ RPVR11 ]> { - let MethodProtos = [{ - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - SPRClass::iterator - SPRClass::allocation_order_end(const MachineFunction &MF) const { - // None of the special purpose registers are allocatable. - return end()-24; - } - }]; + // None of the special purpose registers are allocatable. + let isAllocatable = 0; } def CRC : RegisterClass<"MBlaze", [i32], 32, [CARRY]> { Modified: llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp?rev=132781&r1=132780&r2=132781&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp Thu Jun 9 11:56:59 2011 @@ -76,7 +76,11 @@ BitVector Reserved(getNumRegs()); const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); - // Mark 4 special registers as reserved. + // Mark 4 special registers with subregisters as reserved. + Reserved.set(MSP430::PCB); + Reserved.set(MSP430::SPB); + Reserved.set(MSP430::SRB); + Reserved.set(MSP430::CGB); Reserved.set(MSP430::PCW); Reserved.set(MSP430::SPW); Reserved.set(MSP430::SRW); Modified: llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td?rev=132781&r1=132780&r2=132781&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td (original) +++ llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td Thu Jun 9 11:56:59 2011 @@ -70,25 +70,7 @@ // Frame pointer, sometimes allocable FPB, // Volatile, but not allocable - PCB, SPB, SRB, CGB]> -{ - let MethodProtos = [{ - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - GR8Class::iterator - GR8Class::allocation_order_end(const MachineFunction &MF) const { - const TargetMachine &TM = MF.getTarget(); - const TargetFrameLowering *TFI = TM.getFrameLowering(); - // Depending on whether the function uses frame pointer or not, last 5 or 4 - // registers on the list above are reserved - if (TFI->hasFP(MF)) - return end()-5; - else - return end()-4; - } - }]; -} + PCB, SPB, SRB, CGB]>; def GR16 : RegisterClass<"MSP430", [i16], 16, // Volatile registers @@ -99,21 +81,5 @@ PCW, SPW, SRW, CGW]> { let SubRegClasses = [(GR8 subreg_8bit)]; - let MethodProtos = [{ - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - GR16Class::iterator - GR16Class::allocation_order_end(const MachineFunction &MF) const { - const TargetMachine &TM = MF.getTarget(); - const TargetFrameLowering *TFI = TM.getFrameLowering(); - // Depending on whether the function uses frame pointer or not, last 5 or 4 - // registers on the list above are reserved - if (TFI->hasFP(MF)) - return end()-5; - else - return end()-4; - } - }]; } Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=132781&r1=132780&r2=132781&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Thu Jun 9 11:56:59 2011 @@ -127,6 +127,8 @@ Reserved.set(Mips::SP); Reserved.set(Mips::FP); Reserved.set(Mips::RA); + Reserved.set(Mips::F31); + Reserved.set(Mips::D15); // SRV4 requires that odd register can't be used. if (!Subtarget.isSingleFloat() && !Subtarget.isMips32()) Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td?rev=132781&r1=132780&r2=132781&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Thu Jun 9 11:56:59 2011 @@ -165,19 +165,7 @@ // Callee save S0, S1, S2, S3, S4, S5, S6, S7, // Reserved - ZERO, AT, K0, K1, GP, SP, FP, RA]> -{ - let MethodProtos = [{ - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - CPURegsClass::iterator - CPURegsClass::allocation_order_end(const MachineFunction &MF) const { - // The last 8 registers on the list above are reserved - return end()-8; - } - }]; -} + ZERO, AT, K0, K1, GP, SP, FP, RA]>; // 64bit fp: // * FGR64 - 32 64-bit registers @@ -194,52 +182,7 @@ // Callee save F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, // Reserved - F31]> -{ - let MethodProtos = [{ - iterator allocation_order_begin(const MachineFunction &MF) const; - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - - static const unsigned MIPS_FGR32[] = { - Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F12, Mips::F13, - Mips::F14, Mips::F15, Mips::F4, Mips::F5, Mips::F6, Mips::F7, - Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F16, Mips::F17, - Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, - Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, - Mips::F30 - }; - - static const unsigned MIPS_SVR4_FGR32[] = { - Mips::F0, Mips::F2, Mips::F12, Mips::F14, Mips::F4, - Mips::F6, Mips::F8, Mips::F10, Mips::F16, Mips::F18, - Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30, - }; - - FGR32Class::iterator - FGR32Class::allocation_order_begin(const MachineFunction &MF) const { - const TargetMachine &TM = MF.getTarget(); - const MipsSubtarget &Subtarget = TM.getSubtarget(); - - if (Subtarget.isMips32() || Subtarget.isSingleFloat()) - return MIPS_FGR32; - else - return MIPS_SVR4_FGR32; - } - - FGR32Class::iterator - FGR32Class::allocation_order_end(const MachineFunction &MF) const { - const TargetMachine &TM = MF.getTarget(); - const MipsSubtarget &Subtarget = TM.getSubtarget(); - - if (Subtarget.isMips32() || Subtarget.isSingleFloat()) - return MIPS_FGR32 + (sizeof(MIPS_FGR32) / sizeof(unsigned)); - else - return MIPS_SVR4_FGR32 + (sizeof(MIPS_SVR4_FGR32) / sizeof(unsigned)); - } - }]; -} + F31]>; def AFGR64 : RegisterClass<"Mips", [f64], 64, // Return Values and Arguments @@ -249,19 +192,8 @@ // Callee save D10, D11, D12, D13, D14, // Reserved - D15]> -{ + D15]> { let SubRegClasses = [(FGR32 sub_fpeven, sub_fpodd)]; - let MethodProtos = [{ - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - AFGR64Class::iterator - AFGR64Class::allocation_order_end(const MachineFunction &MF) const { - // The last register on the list above is reserved - return end()-1; - } - }]; } // Condition Register for floating point operations Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td?rev=132781&r1=132780&r2=132781&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td (original) +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td Thu Jun 9 11:56:59 2011 @@ -279,68 +279,12 @@ def GPRC : RegisterClass<"PPC", [i32], 32, [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17, - R16, R15, R14, R13, R31, R0, R1, LR]> -{ - let MethodProtos = [{ - iterator allocation_order_begin(const MachineFunction &MF) const; - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - GPRCClass::iterator - GPRCClass::allocation_order_begin(const MachineFunction &MF) const { - // 32-bit SVR4 ABI: r2 is reserved for the OS. - // 64-bit SVR4 ABI: r2 is reserved for the TOC pointer. - // Darwin: R2 is reserved for CR save/restore sequence. - return begin()+1; - } - GPRCClass::iterator - GPRCClass::allocation_order_end(const MachineFunction &MF) const { - // On PPC64, r13 is the thread pointer. Never allocate this register. - // Note that this is overconservative, as it also prevents allocation of - // R31 when the FP is not needed. - // When using the 32-bit SVR4 ABI, r13 is reserved for the Small Data Area - // pointer. - const PPCSubtarget &Subtarget = MF.getTarget().getSubtarget(); - const PPCFrameLowering *PPCFI = - static_cast(MF.getTarget().getFrameLowering()); - - if (Subtarget.isPPC64() || Subtarget.isSVR4ABI()) - return end()-5; // don't allocate R13, R31, R0, R1, LR - - if (PPCFI->needsFP(MF)) - return end()-4; // don't allocate R31, R0, R1, LR - else - return end()-3; // don't allocate R0, R1, LR - } - }]; -} + R16, R15, R14, R13, R31, R0, R1, LR]>; + def G8RC : RegisterClass<"PPC", [i64], 64, [X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X30, X29, X28, X27, X26, X25, X24, X23, X22, X21, X20, X19, X18, X17, - X16, X15, X14, X31, X13, X0, X1, LR8]> -{ - let MethodProtos = [{ - iterator allocation_order_begin(const MachineFunction &MF) const; - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - G8RCClass::iterator - G8RCClass::allocation_order_begin(const MachineFunction &MF) const { - // 64-bit SVR4 ABI: r2 is reserved for the TOC pointer. - // Darwin: r2 is reserved for CR save/restore sequence. - return begin()+1; - } - G8RCClass::iterator - G8RCClass::allocation_order_end(const MachineFunction &MF) const { - const PPCFrameLowering *PPCFI = - static_cast(MF.getTarget().getFrameLowering()); - if (PPCFI->needsFP(MF)) - return end()-5; - else - return end()-4; - } - }]; -} + X16, X15, X14, X31, X13, X0, X1, LR8]>; // Allocate volatiles first, then non-volatiles in reverse order. With the SVR4 // ABI the size of the Floating-point register save area is determined by the Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp?rev=132781&r1=132780&r2=132781&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp Thu Jun 9 11:56:59 2011 @@ -39,6 +39,8 @@ BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const { BitVector Reserved(getNumRegs()); + // FIXME: G1 reserved for now for large imm generation by frame code. + Reserved.set(SP::G1); Reserved.set(SP::G2); Reserved.set(SP::G3); Reserved.set(SP::G4); Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.td?rev=132781&r1=132780&r2=132781&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.td (original) +++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.td Thu Jun 9 11:56:59 2011 @@ -142,8 +142,6 @@ def IntRegs : RegisterClass<"SP", [i32], 32, [L0, L1, L2, L3, L4, L5, L6, L7, I0, I1, I2, I3, I4, I5, O0, O1, O2, O3, O4, O5, O7, - - // FIXME: G1 reserved for now for large imm generation by frame code. G1, // Non-allocatable regs: G2, G3, G4, // FIXME: OK for use only in @@ -153,19 +151,7 @@ I7, // return address G0, // constant zero G5, G6, G7 // reserved for kernel - ]> { - let MethodProtos = [{ - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - IntRegsClass::iterator - IntRegsClass::allocation_order_end(const MachineFunction &MF) const { - // FIXME: These special regs should be taken out of the regclass! - return end()-10 // Don't allocate special registers - -1; // FIXME: G1 reserved for large imm generation by frame code. - } - }]; -} + ]>; def FPRegs : RegisterClass<"SP", [f32], 32, [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22, Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=132781&r1=132780&r2=132781&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Thu Jun 9 11:56:59 2011 @@ -515,6 +515,25 @@ Reserved.set(X86::FS); Reserved.set(X86::GS); + // Reserve the registers that only exist in 64-bit mode. + if (!Is64Bit) { + for (unsigned n = 0; n != 8; ++n) { + const unsigned GPR64[] = { + X86::R8, X86::R9, X86::R10, X86::R11, + X86::R12, X86::R13, X86::R14, X86::R15 + }; + for (const unsigned *AI = getOverlaps(GPR64[n]); unsigned Reg = *AI; + ++AI) + Reserved.set(Reg); + + // XMM8, XMM9, ... + assert(X86::XMM15 == X86::XMM8+7); + for (const unsigned *AI = getOverlaps(X86::XMM8 + n); unsigned Reg = *AI; + ++AI) + Reserved.set(Reg); + } + } + return Reserved; } Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=132781&r1=132780&r2=132781&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Thu Jun 9 11:56:59 2011 @@ -326,104 +326,12 @@ [AX, CX, DX, SI, DI, BX, BP, SP, R8W, R9W, R10W, R11W, R14W, R15W, R12W, R13W]> { let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi)]; - let MethodProtos = [{ - iterator allocation_order_begin(const MachineFunction &MF) const; - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - static const unsigned X86_GR16_AO_64[] = { - X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, - X86::R8W, X86::R9W, X86::R10W, X86::R11W, - X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::BP - }; - - GR16Class::iterator - GR16Class::allocation_order_begin(const MachineFunction &MF) const { - const TargetMachine &TM = MF.getTarget(); - const X86Subtarget &Subtarget = TM.getSubtarget(); - if (Subtarget.is64Bit()) - return X86_GR16_AO_64; - else - return begin(); - } - - GR16Class::iterator - GR16Class::allocation_order_end(const MachineFunction &MF) const { - const TargetMachine &TM = MF.getTarget(); - const TargetFrameLowering *TFI = TM.getFrameLowering(); - const X86Subtarget &Subtarget = TM.getSubtarget(); - const X86MachineFunctionInfo *MFI = MF.getInfo(); - if (Subtarget.is64Bit()) { - // Does the function dedicate RBP to being a frame ptr? - if (TFI->hasFP(MF) || MFI->getReserveFP()) - // If so, don't allocate SP or BP. - return array_endof(X86_GR16_AO_64) - 1; - else - // If not, just don't allocate SP. - return array_endof(X86_GR16_AO_64); - } else { - // Does the function dedicate EBP to being a frame ptr? - if (TFI->hasFP(MF) || MFI->getReserveFP()) - // If so, don't allocate SP or BP. - return begin() + 6; - else - // If not, just don't allocate SP. - return begin() + 7; - } - } - }]; } def GR32 : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP, R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D]> { let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit)]; - let MethodProtos = [{ - iterator allocation_order_begin(const MachineFunction &MF) const; - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - static const unsigned X86_GR32_AO_64[] = { - X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, - X86::R8D, X86::R9D, X86::R10D, X86::R11D, - X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP - }; - - GR32Class::iterator - GR32Class::allocation_order_begin(const MachineFunction &MF) const { - const TargetMachine &TM = MF.getTarget(); - const X86Subtarget &Subtarget = TM.getSubtarget(); - if (Subtarget.is64Bit()) - return X86_GR32_AO_64; - else - return begin(); - } - - GR32Class::iterator - GR32Class::allocation_order_end(const MachineFunction &MF) const { - const TargetMachine &TM = MF.getTarget(); - const TargetFrameLowering *TFI = TM.getFrameLowering(); - const X86Subtarget &Subtarget = TM.getSubtarget(); - const X86MachineFunctionInfo *MFI = MF.getInfo(); - if (Subtarget.is64Bit()) { - // Does the function dedicate RBP to being a frame ptr? - if (TFI->hasFP(MF) || MFI->getReserveFP()) - // If so, don't allocate ESP or EBP. - return array_endof(X86_GR32_AO_64) - 1; - else - // If not, just don't allocate ESP. - return array_endof(X86_GR32_AO_64); - } else { - // Does the function dedicate EBP to being a frame ptr? - if (TFI->hasFP(MF) || MFI->getReserveFP()) - // If so, don't allocate ESP or EBP. - return begin() + 6; - else - // If not, just don't allocate ESP. - return begin() + 7; - } - } - }]; } // GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since @@ -544,52 +452,6 @@ [EAX, ECX, EDX, ESI, EDI, EBX, EBP, R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D]> { let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit)]; - let MethodProtos = [{ - iterator allocation_order_begin(const MachineFunction &MF) const; - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - static const unsigned X86_GR32_NOSP_AO_64[] = { - X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, - X86::R8D, X86::R9D, X86::R10D, X86::R11D, - X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP - }; - - GR32_NOSPClass::iterator - GR32_NOSPClass::allocation_order_begin(const MachineFunction &MF) const { - const TargetMachine &TM = MF.getTarget(); - const X86Subtarget &Subtarget = TM.getSubtarget(); - if (Subtarget.is64Bit()) - return X86_GR32_NOSP_AO_64; - else - return begin(); - } - - GR32_NOSPClass::iterator - GR32_NOSPClass::allocation_order_end(const MachineFunction &MF) const { - const TargetMachine &TM = MF.getTarget(); - const TargetFrameLowering *TFI = TM.getFrameLowering(); - const X86Subtarget &Subtarget = TM.getSubtarget(); - const X86MachineFunctionInfo *MFI = MF.getInfo(); - if (Subtarget.is64Bit()) { - // Does the function dedicate RBP to being a frame ptr? - if (TFI->hasFP(MF) || MFI->getReserveFP()) - // If so, don't allocate EBP. - return array_endof(X86_GR32_NOSP_AO_64) - 1; - else - // If not, any reg in this class is ok. - return array_endof(X86_GR32_NOSP_AO_64); - } else { - // Does the function dedicate EBP to being a frame ptr? - if (TFI->hasFP(MF) || MFI->getReserveFP()) - // If so, don't allocate EBP. - return begin() + 6; - else - // If not, any reg in this class is ok. - return begin() + 7; - } - } - }]; } // GR64_NOSP - GR64 registers except RSP (and RIP). @@ -628,42 +490,12 @@ def FR32 : RegisterClass<"X86", [f32], 32, [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, - XMM12, XMM13, XMM14, XMM15]> { - let MethodProtos = [{ - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - FR32Class::iterator - FR32Class::allocation_order_end(const MachineFunction &MF) const { - const TargetMachine &TM = MF.getTarget(); - const X86Subtarget &Subtarget = TM.getSubtarget(); - if (!Subtarget.is64Bit()) - return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode. - else - return end(); - } - }]; -} + XMM12, XMM13, XMM14, XMM15]>; def FR64 : RegisterClass<"X86", [f64], 64, [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, - XMM12, XMM13, XMM14, XMM15]> { - let MethodProtos = [{ - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - FR64Class::iterator - FR64Class::allocation_order_end(const MachineFunction &MF) const { - const TargetMachine &TM = MF.getTarget(); - const X86Subtarget &Subtarget = TM.getSubtarget(); - if (!Subtarget.is64Bit()) - return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode. - else - return end(); - } - }]; -} + XMM12, XMM13, XMM14, XMM15]>; // FIXME: This sets up the floating point register files as though they are f64 @@ -692,21 +524,6 @@ XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]> { let SubRegClasses = [(FR32 sub_ss), (FR64 sub_sd)]; - - let MethodProtos = [{ - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - VR128Class::iterator - VR128Class::allocation_order_end(const MachineFunction &MF) const { - const TargetMachine &TM = MF.getTarget(); - const X86Subtarget &Subtarget = TM.getSubtarget(); - if (!Subtarget.is64Bit()) - return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode. - else - return end(); - } - }]; } def VR256 : RegisterClass<"X86", [v32i8, v8i32, v4i64, v8f32, v4f64], 256, @@ -714,21 +531,6 @@ YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15]> { let SubRegClasses = [(FR32 sub_ss), (FR64 sub_sd), (VR128 sub_xmm)]; - - let MethodProtos = [{ - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - VR256Class::iterator - VR256Class::allocation_order_end(const MachineFunction &MF) const { - const TargetMachine &TM = MF.getTarget(); - const X86Subtarget &Subtarget = TM.getSubtarget(); - if (!Subtarget.is64Bit()) - return end()-8; // Only YMM0 to YMM7 are available in 32-bit mode. - else - return end(); - } - }]; } // Status flags registers. Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.td?rev=132781&r1=132780&r2=132781&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.td (original) +++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.td Thu Jun 9 11:56:59 2011 @@ -48,27 +48,7 @@ // Not preserved across procedure calls R11, // Callee save - R4, R5, R6, R7, R8, R9, R10]> { - let MethodProtos = [{ - iterator allocation_order_begin(const MachineFunction &MF) const; - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - GRRegsClass::iterator - GRRegsClass::allocation_order_begin(const MachineFunction &MF) const { - return begin(); - } - GRRegsClass::iterator - GRRegsClass::allocation_order_end(const MachineFunction &MF) const { - const TargetMachine &TM = MF.getTarget(); - const TargetFrameLowering *TFI = TM.getFrameLowering(); - if (TFI->hasFP(MF)) - return end()-1; // don't allocate R10 - else - return end(); - } - }]; -} + R4, R5, R6, R7, R8, R9, R10]>; // Reserved def RRegs : RegisterClass<"XCore", [i32], 32, [CP, DP, SP, LR]> { From bob.wilson at apple.com Thu Jun 9 09:57:29 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Thu, 09 Jun 2011 16:57:29 -0000 Subject: [llvm-commits] [llvm] r132782 - /llvm/trunk/utils/TableGen/NeonEmitter.cpp Message-ID: <20110609165729.7A10E2A6C12C@llvm.org> Author: bwilson Date: Thu Jun 9 11:57:29 2011 New Revision: 132782 URL: http://llvm.org/viewvc/llvm-project?rev=132782&view=rev Log: Add special-case range checking for VCVT_N intrinsic immediate operands. Radar 9558930. Modified: llvm/trunk/utils/TableGen/NeonEmitter.cpp Modified: llvm/trunk/utils/TableGen/NeonEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/NeonEmitter.cpp?rev=132782&r1=132781&r2=132782&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/NeonEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/NeonEmitter.cpp Thu Jun 9 11:57:29 2011 @@ -1398,9 +1398,14 @@ for (unsigned ti = 0, te = TypeVec.size(); ti != te; ++ti) { std::string namestr, shiftstr, rangestr; - // Builtins which are overloaded by type will need to have their upper - // bound computed at Sema time based on the type constant. - if (Proto.find('s') == std::string::npos) { + if (R->getValueAsBit("isVCVT_N")) { + // VCVT between floating- and fixed-point values takes an immediate + // in the range 1 to 32. + ck = ClassB; + rangestr = "l = 1; u = 31"; // upper bound = l + u + } else if (Proto.find('s') == std::string::npos) { + // Builtins which are overloaded by type will need to have their upper + // bound computed at Sema time based on the type constant. ck = ClassB; if (R->getValueAsBit("isShift")) { shiftstr = ", true"; From gkistanova at gmail.com Thu Jun 9 10:18:38 2011 From: gkistanova at gmail.com (Galina Kistanova) Date: Thu, 09 Jun 2011 17:18:38 -0000 Subject: [llvm-commits] [llvm] r132785 - in /llvm/trunk/test/FrontendC/ARM: dg.exp inline-asm-multichar.c Message-ID: <20110609171838.1540F2A6C12C@llvm.org> Author: gkistanova Date: Thu Jun 9 12:18:37 2011 New Revision: 132785 URL: http://llvm.org/viewvc/llvm-project?rev=132785&view=rev Log: Added dg.exp to run FrontendC ARM-dependent tests; updated inline-asm-multichar.c test per this change. Added: llvm/trunk/test/FrontendC/ARM/dg.exp Modified: llvm/trunk/test/FrontendC/ARM/inline-asm-multichar.c Added: llvm/trunk/test/FrontendC/ARM/dg.exp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/ARM/dg.exp?rev=132785&view=auto ============================================================================== --- llvm/trunk/test/FrontendC/ARM/dg.exp (added) +++ llvm/trunk/test/FrontendC/ARM/dg.exp Thu Jun 9 12:18:37 2011 @@ -0,0 +1,5 @@ +load_lib llvm.exp + +if { [llvm_supports_target ARM] AND [ llvm_gcc_supports c ] } { + RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp,s}]] +} Modified: llvm/trunk/test/FrontendC/ARM/inline-asm-multichar.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/ARM/inline-asm-multichar.c?rev=132785&r1=132784&r2=132785&view=diff ============================================================================== --- llvm/trunk/test/FrontendC/ARM/inline-asm-multichar.c (original) +++ llvm/trunk/test/FrontendC/ARM/inline-asm-multichar.c Thu Jun 9 12:18:37 2011 @@ -1,11 +1,8 @@ // RUN: %llvmgcc -S -march=armv7a %s -// XFAIL: * -// XTARGET: arm - int t1() { static float k = 1.0f; -CHECK: call void asm sideeffect "flds s15, $0 \0A", "*^Uv,~{s15}" +// CHECK: call void asm sideeffect "flds s15, $0 \0A", "*^Uv,~{s15}" __asm__ volatile ("flds s15, %[k] \n" :: [k] "Uv,m" (k) : "s15"); return 0; } From echristo at apple.com Thu Jun 9 10:25:20 2011 From: echristo at apple.com (Eric Christopher) Date: Thu, 09 Jun 2011 10:25:20 -0700 Subject: [llvm-commits] [llvm] r132785 - in /llvm/trunk/test/FrontendC/ARM: dg.exp inline-asm-multichar.c In-Reply-To: <20110609171838.1540F2A6C12C@llvm.org> References: <20110609171838.1540F2A6C12C@llvm.org> Message-ID: On Jun 9, 2011, at 10:18 AM, Galina Kistanova wrote: > Author: gkistanova > Date: Thu Jun 9 12:18:37 2011 > New Revision: 132785 > > URL: http://llvm.org/viewvc/llvm-project?rev=132785&view=rev > Log: > Added dg.exp to run FrontendC ARM-dependent tests; updated inline-asm-multichar.c test per this change. > Thanks! -eric From gkistanova at gmail.com Thu Jun 9 10:35:15 2011 From: gkistanova at gmail.com (Galina Kistanova) Date: Thu, 9 Jun 2011 10:35:15 -0700 Subject: [llvm-commits] [llvm] r132785 - in /llvm/trunk/test/FrontendC/ARM: dg.exp inline-asm-multichar.c In-Reply-To: References: <20110609171838.1540F2A6C12C@llvm.org> Message-ID: You are welcome, Eric! By the way, if I compile the test with clang (ToT), I get the result quoted below. Please notice that inlined asm call doesn't match your pattern. Is this expected? Thanks Galina ---------------------------------------------------------------------------------------------------- ; ModuleID = '/home/buildslave/zorg/buildbot/osuosl/slave/clang-native-arm-cortex-a9/llvm/test/FrontendC/ARM/inline-asm-multichar.c' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32" target triple = "armv7-unknown-linux-gnueabi" @t1.k = internal global float 1.000000e+00, align 4 define i32 @t1() nounwind { entry: call void asm sideeffect "flds s15, $0 \0A", "*^Uv|m,~{s15}"(float* @t1.k) nounwind, !srcloc !0 ret i32 0 } !0 = metadata !{i32 166} ---------------------------------------------------------------------------------------------------- On Thu, Jun 9, 2011 at 10:25 AM, Eric Christopher wrote: > > On Jun 9, 2011, at 10:18 AM, Galina Kistanova wrote: > >> Author: gkistanova >> Date: Thu Jun  9 12:18:37 2011 >> New Revision: 132785 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=132785&view=rev >> Log: >> Added dg.exp to run FrontendC ARM-dependent tests; updated inline-asm-multichar.c test per this change. >> > > Thanks! > > -eric > From echristo at apple.com Thu Jun 9 10:37:04 2011 From: echristo at apple.com (Eric Christopher) Date: Thu, 09 Jun 2011 10:37:04 -0700 Subject: [llvm-commits] [llvm] r132785 - in /llvm/trunk/test/FrontendC/ARM: dg.exp inline-asm-multichar.c In-Reply-To: References: <20110609171838.1540F2A6C12C@llvm.org> Message-ID: <01A659A3-29A4-4D64-8366-ECD8E4E128A0@apple.com> On Jun 9, 2011, at 10:35 AM, Galina Kistanova wrote: > You are welcome, Eric! > > By the way, if I compile the test with clang (ToT), I get the result > quoted below. > Please notice that inlined asm call doesn't match your pattern. Is > this expected? Well, it's known, I'm not sure it's expected. I noticed it a couple of days ago and haven't had a chance to see why one compiler thinks the operand is indirect and the other one disagrees. -eric From grosbach at apple.com Thu Jun 9 11:22:41 2011 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 09 Jun 2011 11:22:41 -0700 Subject: [llvm-commits] [llvm] r132676 - in /llvm/trunk: lib/CodeGen/SelectionDAG/FastISel.cpp test/CodeGen/X86/fast-isel-agg-constant.ll In-Reply-To: <20110609080819.GA4929@freebsd.org> References: <20110606153822.GA6591@freebsd.org> <20110609080819.GA4929@freebsd.org> Message-ID: <969FF868-AE98-4F22-AABD-D59D3C483793@apple.com> On Jun 9, 2011, at 1:08 AM, Roman Divacky wrote: > On Wed, Jun 08, 2011 at 11:08:36PM -0700, Eric Christopher wrote: >> >> On Jun 6, 2011, at 8:38 AM, Roman Divacky wrote: >> >>> OK to commit? Or is there a better way to distinguish those two >>> asm dialects? >> >> Maybe check the Subtarget instead? > > Where do I get it in MCExpr? If at all possible, we want to avoid the Subtarget in MC layer operations. There are a few places it's done, but it's a layering violation that we're trying very hard to avoid. Long term, we want to refactor the target machine to allow us to decouple it from MC. For purposes of something like this, you would theoretically just use the target triple. That is, if the triple specifies the target is Darwin (or not), behave accordingly. I don't think the triple is explicitly threaded through MC, though, so other than conceptually, I don't think that helps you much. CCing Daniel. He may know some sneaky ways to get the info. -Jim From stoklund at 2pi.dk Thu Jun 9 11:42:07 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 09 Jun 2011 18:42:07 -0000 Subject: [llvm-commits] [llvm] r132788 - in /llvm/trunk/utils/TableGen: CMakeLists.txt CodeGenRegisters.cpp CodeGenTarget.cpp Message-ID: <20110609184207.D3DFA2A6C12C@llvm.org> Author: stoklund Date: Thu Jun 9 13:42:07 2011 New Revision: 132788 URL: http://llvm.org/viewvc/llvm-project?rev=132788&view=rev Log: Move TableGen's register bank classes to their own source file. I'll be moving some more code there to gather all of the register-specific stuff in one place. Currently it is shared between CodeGenTarget and RegisterInfoEmitter. The plan is that CodeGenRegisters can compute the full register bank structure while RegisterInfoEmitter only will handle the printing part. Added: llvm/trunk/utils/TableGen/CodeGenRegisters.cpp Modified: llvm/trunk/utils/TableGen/CMakeLists.txt llvm/trunk/utils/TableGen/CodeGenTarget.cpp Modified: llvm/trunk/utils/TableGen/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CMakeLists.txt?rev=132788&r1=132787&r2=132788&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CMakeLists.txt (original) +++ llvm/trunk/utils/TableGen/CMakeLists.txt Thu Jun 9 13:42:07 2011 @@ -16,6 +16,7 @@ CodeEmitterGen.cpp CodeGenDAGPatterns.cpp CodeGenInstruction.cpp + CodeGenRegisters.cpp CodeGenTarget.cpp DAGISelEmitter.cpp DAGISelMatcherEmitter.cpp Added: llvm/trunk/utils/TableGen/CodeGenRegisters.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.cpp?rev=132788&view=auto ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenRegisters.cpp (added) +++ llvm/trunk/utils/TableGen/CodeGenRegisters.cpp Thu Jun 9 13:42:07 2011 @@ -0,0 +1,101 @@ +//===- CodeGenRegisters.cpp - Register and RegisterClass Info -------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines structures to encapsulate information gleaned from the +// target register and register class definitions. +// +//===----------------------------------------------------------------------===// + +#include "CodeGenRegisters.h" +#include "CodeGenTarget.h" +#include "llvm/ADT/StringExtras.h" + +using namespace llvm; + +//===----------------------------------------------------------------------===// +// CodeGenRegister +//===----------------------------------------------------------------------===// + +CodeGenRegister::CodeGenRegister(Record *R) : TheDef(R) { + CostPerUse = R->getValueAsInt("CostPerUse"); +} + +const std::string &CodeGenRegister::getName() const { + return TheDef->getName(); +} + +//===----------------------------------------------------------------------===// +// CodeGenRegisterClass +//===----------------------------------------------------------------------===// + +CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) { + // Rename anonymous register classes. + if (R->getName().size() > 9 && R->getName()[9] == '.') { + static unsigned AnonCounter = 0; + R->setName("AnonRegClass_"+utostr(AnonCounter++)); + } + + std::vector TypeList = R->getValueAsListOfDefs("RegTypes"); + for (unsigned i = 0, e = TypeList.size(); i != e; ++i) { + Record *Type = TypeList[i]; + if (!Type->isSubClassOf("ValueType")) + throw "RegTypes list member '" + Type->getName() + + "' does not derive from the ValueType class!"; + VTs.push_back(getValueType(Type)); + } + assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!"); + + std::vector RegList = R->getValueAsListOfDefs("MemberList"); + for (unsigned i = 0, e = RegList.size(); i != e; ++i) { + Record *Reg = RegList[i]; + if (!Reg->isSubClassOf("Register")) + throw "Register Class member '" + Reg->getName() + + "' does not derive from the Register class!"; + Elements.push_back(Reg); + } + + // SubRegClasses is a list containing (RC, subregindex, ...) dags. + ListInit *SRC = R->getValueAsListInit("SubRegClasses"); + for (ListInit::const_iterator i = SRC->begin(), e = SRC->end(); i != e; ++i) { + DagInit *DAG = dynamic_cast(*i); + if (!DAG) throw "SubRegClasses must contain DAGs"; + DefInit *DAGOp = dynamic_cast(DAG->getOperator()); + Record *RCRec; + if (!DAGOp || !(RCRec = DAGOp->getDef())->isSubClassOf("RegisterClass")) + throw "Operator '" + DAG->getOperator()->getAsString() + + "' in SubRegClasses is not a RegisterClass"; + // Iterate over args, all SubRegIndex instances. + for (DagInit::const_arg_iterator ai = DAG->arg_begin(), ae = DAG->arg_end(); + ai != ae; ++ai) { + DefInit *Idx = dynamic_cast(*ai); + Record *IdxRec; + if (!Idx || !(IdxRec = Idx->getDef())->isSubClassOf("SubRegIndex")) + throw "Argument '" + (*ai)->getAsString() + + "' in SubRegClasses is not a SubRegIndex"; + if (!SubRegClasses.insert(std::make_pair(IdxRec, RCRec)).second) + throw "SubRegIndex '" + IdxRec->getName() + "' mentioned twice"; + } + } + + // Allow targets to override the size in bits of the RegisterClass. + unsigned Size = R->getValueAsInt("Size"); + + Namespace = R->getValueAsString("Namespace"); + SpillSize = Size ? Size : EVT(VTs[0]).getSizeInBits(); + SpillAlignment = R->getValueAsInt("Alignment"); + CopyCost = R->getValueAsInt("CopyCost"); + Allocatable = R->getValueAsBit("isAllocatable"); + MethodBodies = R->getValueAsCode("MethodBodies"); + MethodProtos = R->getValueAsCode("MethodProtos"); +} + +const std::string &CodeGenRegisterClass::getName() const { + return TheDef->getName(); +} + Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=132788&r1=132787&r2=132788&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Thu Jun 9 13:42:07 2011 @@ -169,14 +169,6 @@ Registers[i].EnumValue = i + 1; } -CodeGenRegister::CodeGenRegister(Record *R) : TheDef(R) { - CostPerUse = R->getValueAsInt("CostPerUse"); -} - -const std::string &CodeGenRegister::getName() const { - return TheDef->getName(); -} - void CodeGenTarget::ReadSubRegIndices() const { SubRegIndices = Records.getAllDerivedDefinitions("SubRegIndex"); std::sort(SubRegIndices.begin(), SubRegIndices.end(), LessRecord()); @@ -233,71 +225,6 @@ } -CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) { - // Rename anonymous register classes. - if (R->getName().size() > 9 && R->getName()[9] == '.') { - static unsigned AnonCounter = 0; - R->setName("AnonRegClass_"+utostr(AnonCounter++)); - } - - std::vector TypeList = R->getValueAsListOfDefs("RegTypes"); - for (unsigned i = 0, e = TypeList.size(); i != e; ++i) { - Record *Type = TypeList[i]; - if (!Type->isSubClassOf("ValueType")) - throw "RegTypes list member '" + Type->getName() + - "' does not derive from the ValueType class!"; - VTs.push_back(getValueType(Type)); - } - assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!"); - - std::vector RegList = R->getValueAsListOfDefs("MemberList"); - for (unsigned i = 0, e = RegList.size(); i != e; ++i) { - Record *Reg = RegList[i]; - if (!Reg->isSubClassOf("Register")) - throw "Register Class member '" + Reg->getName() + - "' does not derive from the Register class!"; - Elements.push_back(Reg); - } - - // SubRegClasses is a list containing (RC, subregindex, ...) dags. - ListInit *SRC = R->getValueAsListInit("SubRegClasses"); - for (ListInit::const_iterator i = SRC->begin(), e = SRC->end(); i != e; ++i) { - DagInit *DAG = dynamic_cast(*i); - if (!DAG) throw "SubRegClasses must contain DAGs"; - DefInit *DAGOp = dynamic_cast(DAG->getOperator()); - Record *RCRec; - if (!DAGOp || !(RCRec = DAGOp->getDef())->isSubClassOf("RegisterClass")) - throw "Operator '" + DAG->getOperator()->getAsString() + - "' in SubRegClasses is not a RegisterClass"; - // Iterate over args, all SubRegIndex instances. - for (DagInit::const_arg_iterator ai = DAG->arg_begin(), ae = DAG->arg_end(); - ai != ae; ++ai) { - DefInit *Idx = dynamic_cast(*ai); - Record *IdxRec; - if (!Idx || !(IdxRec = Idx->getDef())->isSubClassOf("SubRegIndex")) - throw "Argument '" + (*ai)->getAsString() + - "' in SubRegClasses is not a SubRegIndex"; - if (!SubRegClasses.insert(std::make_pair(IdxRec, RCRec)).second) - throw "SubRegIndex '" + IdxRec->getName() + "' mentioned twice"; - } - } - - // Allow targets to override the size in bits of the RegisterClass. - unsigned Size = R->getValueAsInt("Size"); - - Namespace = R->getValueAsString("Namespace"); - SpillSize = Size ? Size : EVT(VTs[0]).getSizeInBits(); - SpillAlignment = R->getValueAsInt("Alignment"); - CopyCost = R->getValueAsInt("CopyCost"); - Allocatable = R->getValueAsBit("isAllocatable"); - MethodBodies = R->getValueAsCode("MethodBodies"); - MethodProtos = R->getValueAsCode("MethodProtos"); -} - -const std::string &CodeGenRegisterClass::getName() const { - return TheDef->getName(); -} - void CodeGenTarget::ReadLegalValueTypes() const { const std::vector &RCs = getRegisterClasses(); for (unsigned i = 0, e = RCs.size(); i != e; ++i) From eli.friedman at gmail.com Thu Jun 9 11:55:00 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Thu, 09 Jun 2011 18:55:00 -0000 Subject: [llvm-commits] [llvm] r132789 - /llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Message-ID: <20110609185500.927342A6C12C@llvm.org> Author: efriedma Date: Thu Jun 9 13:55:00 2011 New Revision: 132789 URL: http://llvm.org/viewvc/llvm-project?rev=132789&view=rev Log: Add a check to make sure we don't crash with strange configurations where we do fast-isel, then try to fold instructions. PR10092. Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=132789&r1=132788&r2=132789&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Thu Jun 9 13:55:00 2011 @@ -2392,6 +2392,10 @@ return 0; } + // Conservatively fail out for loads without a memoperand. + if (LoadMI->memoperands_empty()) + return 0; + // Determine the alignment of the load. unsigned Alignment = 0; if (LoadMI->hasOneMemOperand()) From jason.w.kim.2009 at gmail.com Thu Jun 9 12:13:45 2011 From: jason.w.kim.2009 at gmail.com (Jason W Kim) Date: Thu, 09 Jun 2011 19:13:45 -0000 Subject: [llvm-commits] [llvm] r132790 - /llvm/trunk/lib/MC/ELFObjectWriter.cpp Message-ID: <20110609191345.545752A6C12C@llvm.org> Author: jasonwkim Date: Thu Jun 9 14:13:45 2011 New Revision: 132790 URL: http://llvm.org/viewvc/llvm-project?rev=132790&view=rev Log: Remove an uneeded switch - Turns out reloc results are identical w/o the switch. (face+palm) Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=132790&r1=132789&r2=132790&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Thu Jun 9 14:13:45 2011 @@ -37,17 +37,6 @@ #undef DEBUG_TYPE #define DEBUG_TYPE "reloc-info" -// FIXME: This switch must be removed. Since GNU as does not -// need a command line switch for doing its wierd thing with PIC, -// LLVM should not need it either. -// -- -// Emulate the wierd behavior of GNU-as for relocation types -namespace llvm { -cl::opt -ForceARMElfPIC("arm-elf-force-pic", cl::Hidden, cl::init(false), - cl::desc("Force ELF emitter to emit PIC style relocations")); -} - bool ELFObjectWriter::isFixupKindPCRel(const MCAssembler &Asm, unsigned Kind) { const MCFixupKindInfo &FKI = Asm.getBackend().getFixupKindInfo((MCFixupKind) Kind); @@ -1321,7 +1310,7 @@ << Symbol.isVariable() << "/" << Symbol.isTemporary() << " Counts:" << PCRelCount << "/" << NonPCRelCount << "\n"); - if (IsPCRel || ForceARMElfPIC) { ++PCRelCount; + if (IsPCRel) { ++PCRelCount; switch (RelocType) { default: // Most relocation types are emitted as explicit symbols From rafael.espindola at gmail.com Thu Jun 9 12:30:28 2011 From: rafael.espindola at gmail.com (Rafael Avila de Espindola) Date: Thu, 09 Jun 2011 15:30:28 -0400 Subject: [llvm-commits] [llvm] r132790 - /llvm/trunk/lib/MC/ELFObjectWriter.cpp In-Reply-To: <20110609191345.545752A6C12C@llvm.org> References: <20110609191345.545752A6C12C@llvm.org> Message-ID: <4DF11F54.1020708@gmail.com> On 11-06-09 03:13 PM, Jason W Kim wrote: > Author: jasonwkim > Date: Thu Jun 9 14:13:45 2011 > New Revision: 132790 > > URL: http://llvm.org/viewvc/llvm-project?rev=132790&view=rev > Log: > Remove an uneeded switch - Turns out reloc results are identical w/o the switch. (face+palm) Thanks! > > Modified: > llvm/trunk/lib/MC/ELFObjectWriter.cpp > > Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=132790&r1=132789&r2=132790&view=diff > ============================================================================== > --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) > +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Thu Jun 9 14:13:45 2011 > @@ -37,17 +37,6 @@ > #undef DEBUG_TYPE > #define DEBUG_TYPE "reloc-info" > > -// FIXME: This switch must be removed. Since GNU as does not > -// need a command line switch for doing its wierd thing with PIC, > -// LLVM should not need it either. > -// -- > -// Emulate the wierd behavior of GNU-as for relocation types > -namespace llvm { > -cl::opt > -ForceARMElfPIC("arm-elf-force-pic", cl::Hidden, cl::init(false), > - cl::desc("Force ELF emitter to emit PIC style relocations")); > -} > - > bool ELFObjectWriter::isFixupKindPCRel(const MCAssembler&Asm, unsigned Kind) { > const MCFixupKindInfo&FKI = > Asm.getBackend().getFixupKindInfo((MCFixupKind) Kind); > @@ -1321,7 +1310,7 @@ > << Symbol.isVariable()<< "/"<< Symbol.isTemporary() > << " Counts:"<< PCRelCount<< "/"<< NonPCRelCount<< "\n"); > > - if (IsPCRel || ForceARMElfPIC) { ++PCRelCount; > + if (IsPCRel) { ++PCRelCount; > switch (RelocType) { > default: > // Most relocation types are emitted as explicit symbols > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From aggarwa4 at illinois.edu Thu Jun 9 12:30:46 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Thu, 09 Jun 2011 19:30:46 -0000 Subject: [llvm-commits] [poolalloc] r132792 - in /poolalloc/trunk: include/assistDS/TypeChecks.h lib/AssistDS/TypeChecks.cpp Message-ID: <20110609193046.7536E2A6C12C@llvm.org> Author: aggarwa4 Date: Thu Jun 9 14:30:46 2011 New Revision: 132792 URL: http://llvm.org/viewvc/llvm-project?rev=132792&view=rev Log: When visiting globals, create pretty gep's as against the ugly gep's we were creating earlier. Modified: poolalloc/trunk/include/assistDS/TypeChecks.h poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/include/assistDS/TypeChecks.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/TypeChecks.h?rev=132792&r1=132791&r2=132792&view=diff ============================================================================== --- poolalloc/trunk/include/assistDS/TypeChecks.h (original) +++ poolalloc/trunk/include/assistDS/TypeChecks.h Thu Jun 9 14:30:46 2011 @@ -71,7 +71,7 @@ bool visitAllocaInst(Module &M, AllocaInst &AI); bool visitGlobal(Module &M, GlobalVariable &GV, - Constant *C, Instruction &I, unsigned offset); + Constant *C, Instruction &I, SmallVector); bool visitInternalByValFunction(Module &M, Function &F); bool visitExternalByValFunction(Module &M, Function &F); Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=132792&r1=132791&r2=132792&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Thu Jun 9 14:30:46 2011 @@ -1127,7 +1127,8 @@ } if(!I->hasInitializer()) continue; - visitGlobal(M, *I, I->getInitializer(), *InsertPt, 0); + SmallVectorindex; + visitGlobal(M, *I, I->getInitializer(), *InsertPt, index); } // // Insert the run-time ctor into the ctor list. @@ -1208,13 +1209,13 @@ } bool TypeChecks::visitGlobal(Module &M, GlobalVariable &GV, - Constant *C, Instruction &I, unsigned offset) { + Constant *C, Instruction &I, SmallVector Indices) { if(ConstantArray *CA = dyn_cast(C)) { const Type * ElementType = CA->getType()->getElementType(); // Create the type entry for the first element // using recursive creation till we get to the base types - visitGlobal(M, GV, CA->getOperand(0), I, offset); + visitGlobal(M, GV, CA->getOperand(0), I, Indices); // Copy the type metadata for the first element // over for the rest of the elements. @@ -1233,8 +1234,9 @@ for (unsigned i = 0, e = CS->getNumOperands(); i != e; ++i) { if (SL->getElementOffset(i) < SL->getSizeInBytes()) { Constant * ConstElement = cast(CS->getOperand(i)); - unsigned field_offset = offset + (unsigned)SL->getElementOffset(i); - visitGlobal(M, GV, ConstElement, I, field_offset); + Indices.push_back(ConstantInt::get(Int32Ty, i)); + visitGlobal(M, GV, ConstElement, I, Indices); + Indices.pop_back(); } } } else if(ConstantAggregateZero *CAZ = dyn_cast(C)) { @@ -1243,7 +1245,7 @@ const Type *Ty = CAZ->getType(); if(const ArrayType * ATy = dyn_cast(Ty)) { const Type * ElementType = ATy->getElementType(); - visitGlobal(M, GV, Constant::getNullValue(ElementType), I, offset); + visitGlobal(M, GV, Constant::getNullValue(ElementType), I, Indices); CastInst *BCI = BitCastInst::CreatePointerCast(&GV, VoidPtrTy, "", &I); std::vector Args; Args.push_back(BCI); @@ -1255,20 +1257,19 @@ const StructLayout *SL = TD->getStructLayout(STy); for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { if (SL->getElementOffset(i) < SL->getSizeInBytes()) { - unsigned field_offset = offset + (unsigned)SL->getElementOffset(i); - visitGlobal(M, GV, Constant::getNullValue(STy->getElementType(i)), I, field_offset); + Indices.push_back(ConstantInt::get(Int32Ty, i)); + visitGlobal(M, GV, Constant::getNullValue(STy->getElementType(i)), I, Indices); + Indices.pop_back(); } } } else { // Zeroinitializer of a primitive type - CastInst *BCI = BitCastInst::CreatePointerCast(&GV, VoidPtrTy, "", &I); - SmallVector Indices; - Indices.push_back(ConstantInt::get(Int32Ty, offset)); - GetElementPtrInst *GEP = GetElementPtrInst::CreateInBounds(BCI, Indices.begin(), + GetElementPtrInst *GEP = GetElementPtrInst::CreateInBounds(&GV, Indices.begin(), Indices.end(),"", &I) ; + CastInst *BCI = BitCastInst::CreatePointerCast(GEP, VoidPtrTy, "", &I); std::vector Args; - Args.push_back(GEP); + Args.push_back(BCI); Args.push_back(getTypeMarkerConstant(CAZ)); Args.push_back(getSizeConstant(CAZ->getType())); Args.push_back(getTagCounter()); @@ -1277,20 +1278,17 @@ } else { // Primitive type value - CastInst *BCI = BitCastInst::CreatePointerCast(&GV, VoidPtrTy, "", &I); - SmallVector Indices; - Indices.push_back(ConstantInt::get(Int32Ty, offset)); - GetElementPtrInst *GEP = GetElementPtrInst::CreateInBounds(BCI, Indices.begin(), + GetElementPtrInst *GEP = GetElementPtrInst::CreateInBounds(&GV, Indices.begin(), Indices.end(),"", &I) ; + CastInst *BCI = BitCastInst::CreatePointerCast(GEP, VoidPtrTy, "", &I); std::vector Args; - Args.push_back(GEP); + Args.push_back(BCI); Args.push_back(getTypeMarkerConstant(C)); Args.push_back(getSizeConstant(C->getType())); Args.push_back(getTagCounter()); CallInst::Create(trackGlobal, Args.begin(), Args.end(), "", &I); } - return true; } From aggarwa4 at illinois.edu Thu Jun 9 12:31:45 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Thu, 09 Jun 2011 19:31:45 -0000 Subject: [llvm-commits] [poolalloc] r132793 - /poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Message-ID: <20110609193145.5F9992A6C12C@llvm.org> Author: aggarwa4 Date: Thu Jun 9 14:31:45 2011 New Revision: 132793 URL: http://llvm.org/viewvc/llvm-project?rev=132793&view=rev Log: Fix stat. Modified: poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp?rev=132793&r1=132792&r2=132793&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Thu Jun 9 14:31:45 2011 @@ -171,8 +171,6 @@ } numSafe += toDelete.size(); - - numSafe += toDelete.size(); while(!toDelete.empty()) { Instruction *I = toDelete.back(); From aggarwa4 at illinois.edu Thu Jun 9 12:33:18 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Thu, 09 Jun 2011 19:33:18 -0000 Subject: [llvm-commits] [poolalloc] r132794 - /poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Message-ID: <20110609193318.E112F2A6C12C@llvm.org> Author: aggarwa4 Date: Thu Jun 9 14:33:18 2011 New Revision: 132794 URL: http://llvm.org/viewvc/llvm-project?rev=132794&view=rev Log: Fix painful parantheses mismatch issue. Modified: poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp?rev=132794&r1=132793&r2=132794&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Thu Jun 9 14:33:18 2011 @@ -112,7 +112,7 @@ CallInst *CI = dyn_cast(User); assert(CI); - if(TS->isTypeSafe((CI->getOperand(1)->stripPointerCasts(), CI->getParent()->getParent()))) { + if(TS->isTypeSafe(CI->getOperand(1)->stripPointerCasts(), CI->getParent()->getParent())) { toDelete.push_back(CI); } } From eli.friedman at gmail.com Thu Jun 9 12:33:30 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Thu, 09 Jun 2011 19:33:30 -0000 Subject: [llvm-commits] [llvm] r132795 - /llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Message-ID: <20110609193330.B72272A6C12C@llvm.org> Author: efriedma Date: Thu Jun 9 14:33:30 2011 New Revision: 132795 URL: http://llvm.org/viewvc/llvm-project?rev=132795&view=rev Log: Revert 132789; it breaks tests. My mistake. Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=132795&r1=132794&r2=132795&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Thu Jun 9 14:33:30 2011 @@ -2392,10 +2392,6 @@ return 0; } - // Conservatively fail out for loads without a memoperand. - if (LoadMI->memoperands_empty()) - return 0; - // Determine the alignment of the load. unsigned Alignment = 0; if (LoadMI->hasOneMemOperand()) From aggarwa4 at illinois.edu Thu Jun 9 12:36:41 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Thu, 09 Jun 2011 19:36:41 -0000 Subject: [llvm-commits] [poolalloc] r132796 - /poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Message-ID: <20110609193641.5B5EB2A6C12C@llvm.org> Author: aggarwa4 Date: Thu Jun 9 14:36:41 2011 New Revision: 132796 URL: http://llvm.org/viewvc/llvm-project?rev=132796&view=rev Log: Everytime a new typesafe value is created initialize its metadata to TOP. Modified: poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp?rev=132796&r1=132795&r2=132796&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Thu Jun 9 14:36:41 2011 @@ -46,9 +46,11 @@ static Constant *trackStringInput; static Constant *trackArray; static Constant *trackInitInst; +static Constant *trackUnInitInst; static Constant *trackStoreInst; static Constant *trackLoadInst; static Constant *copyTypeInfo; +static Constant *MallocFunc; bool TypeChecksOpt::runOnModule(Module &M) { bool modified = false; // Flags whether we modified the module. @@ -81,6 +83,12 @@ Int64Ty,/*size*/ Int32Ty,/*tag*/ NULL); + trackUnInitInst = M.getOrInsertFunction("trackUnInitInst", + VoidTy, + VoidPtrTy,/*ptr*/ + Int64Ty,/*size*/ + Int32Ty,/*tag*/ + NULL); trackStoreInst = M.getOrInsertFunction("trackStoreInst", VoidTy, VoidPtrTy,/*ptr*/ @@ -107,12 +115,17 @@ VoidPtrTy, Int32Ty, NULL); + MallocFunc = M.getFunction("malloc"); for(Value::use_iterator User = trackGlobal->use_begin(); User != trackGlobal->use_end(); ++User) { CallInst *CI = dyn_cast(User); assert(CI); - if(TS->isTypeSafe(CI->getOperand(1)->stripPointerCasts(), CI->getParent()->getParent())) { + std::vectorArgs; + Args.push_back(CI->getOperand(1)); + Args.push_back(CI->getOperand(3)); + Args.push_back(CI->getOperand(4)); + CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", CI); toDelete.push_back(CI); } } @@ -123,6 +136,7 @@ if(TS->isTypeSafe(CI->getOperand(1)->stripPointerCasts(), CI->getParent()->getParent())) { toDelete.push_back(CI); + continue; } } @@ -135,32 +149,47 @@ } } - for(Value::use_iterator User = trackInitInst->use_begin(); User != trackInitInst->use_end(); ++User) { - CallInst *CI = dyn_cast(User); + // for alloca's if they are type known + // assume initialized with TOP + for(Value::use_iterator User = trackUnInitInst->use_begin(); User != trackUnInitInst->use_end(); ) { + CallInst *CI = dyn_cast(User++); assert(CI); - + + // check if operand is an alloca inst. if(TS->isTypeSafe(CI->getOperand(1)->stripPointerCasts(), CI->getParent()->getParent())) { + CI->setCalledFunction(trackInitInst); toDelete.push_back(CI); } } - for(Value::use_iterator User = trackArray->use_begin(); User != trackArray->use_end(); ++User) { - CallInst *CI = dyn_cast(User); - assert(CI); - - if(TS->isTypeSafe(CI->getOperand(1)->stripPointerCasts(), CI->getParent()->getParent())) { - toDelete.push_back(CI); + if(MallocFunc) { + for(Value::use_iterator User = MallocFunc->use_begin(); User != MallocFunc->use_end(); User ++) { + CallInst *CI = dyn_cast(User); + if(!CI) + continue; + if(TS->isTypeSafe(CI, CI->getParent()->getParent())){ + CastInst *BCI = BitCastInst::CreatePointerCast(CI, VoidPtrTy); + CastInst *Size = CastInst::CreateSExtOrBitCast(CI->getOperand(1), Int64Ty); + Size->insertAfter(CI); + BCI->insertAfter(Size); + std::vectorArgs; + Args.push_back(BCI); + Args.push_back(Size); + Args.push_back(ConstantInt::get(Int32Ty, 0)); + CallInst *CINew = CallInst::Create(trackInitInst, Args.begin(), Args.end()); + CINew->insertAfter(BCI); + } } } + + // also do for mallocs/calloc/other allocators??? + // other allocators?? + for(Value::use_iterator User = copyTypeInfo->use_begin(); User != copyTypeInfo->use_end(); ++User) { CallInst *CI = dyn_cast(User); assert(CI); - + if(TS->isTypeSafe(CI->getOperand(1)->stripPointerCasts(), CI->getParent()->getParent())) { - toDelete.push_back(CI); - continue; - } - if(TS->isTypeSafe(CI->getOperand(2)->stripPointerCasts(), CI->getParent()->getParent())) { std::vector Args; Args.push_back(CI->getOperand(1)); Args.push_back(CI->getOperand(3)); // size @@ -171,7 +200,7 @@ } numSafe += toDelete.size(); - + while(!toDelete.empty()) { Instruction *I = toDelete.back(); toDelete.pop_back(); From rdivacky at freebsd.org Thu Jun 9 12:48:39 2011 From: rdivacky at freebsd.org (Roman Divacky) Date: Thu, 9 Jun 2011 21:48:39 +0200 Subject: [llvm-commits] [llvm] r132676 - in /llvm/trunk: lib/CodeGen/SelectionDAG/FastISel.cpp test/CodeGen/X86/fast-isel-agg-constant.ll In-Reply-To: <969FF868-AE98-4F22-AABD-D59D3C483793@apple.com> References: <20110606153822.GA6591@freebsd.org> <20110609080819.GA4929@freebsd.org> <969FF868-AE98-4F22-AABD-D59D3C483793@apple.com> Message-ID: <20110609194839.GA45739@freebsd.org> On Thu, Jun 09, 2011 at 11:22:41AM -0700, Jim Grosbach wrote: > > On Jun 9, 2011, at 1:08 AM, Roman Divacky wrote: > > > On Wed, Jun 08, 2011 at 11:08:36PM -0700, Eric Christopher wrote: > >> > >> On Jun 6, 2011, at 8:38 AM, Roman Divacky wrote: > >> > >>> OK to commit? Or is there a better way to distinguish those two > >>> asm dialects? > >> > >> Maybe check the Subtarget instead? > > > > Where do I get it in MCExpr? > > If at all possible, we want to avoid the Subtarget in MC layer operations. There are a few places it's done, but it's a layering violation that we're trying very hard to avoid. Long term, we want to refactor the target machine to allow us to decouple it from MC. > > For purposes of something like this, you would theoretically just use the target triple. That is, if the triple specifies the target is Darwin (or not), behave accordingly. I don't think the triple is explicitly threaded through MC, though, so other than conceptually, I don't think that helps you much. The thing is that in MCExpr there's absolutely nothing related to triples etc. It's just a pure container for an expression. Nothing from the outside world is there :) Thats why I introduced the two new variant kinds, to distinguish the two dialects. From rjmccall at apple.com Thu Jun 9 12:46:27 2011 From: rjmccall at apple.com (John McCall) Date: Thu, 09 Jun 2011 19:46:27 -0000 Subject: [llvm-commits] [llvm] r132797 - in /llvm/trunk: include/llvm/Analysis/CallGraph.h lib/Analysis/IPA/CallGraph.cpp lib/Analysis/IPA/CallGraphSCCPass.cpp lib/Transforms/Utils/InlineFunction.cpp Message-ID: <20110609194627.D56E42A6C12C@llvm.org> Author: rjmccall Date: Thu Jun 9 14:46:27 2011 New Revision: 132797 URL: http://llvm.org/viewvc/llvm-project?rev=132797&view=rev Log: Teach the CallGraph to ignore calls to intrinsics. Modified: llvm/trunk/include/llvm/Analysis/CallGraph.h llvm/trunk/lib/Analysis/IPA/CallGraph.cpp llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Modified: llvm/trunk/include/llvm/Analysis/CallGraph.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/CallGraph.h?rev=132797&r1=132796&r2=132797&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/CallGraph.h (original) +++ llvm/trunk/include/llvm/Analysis/CallGraph.h Thu Jun 9 14:46:27 2011 @@ -259,6 +259,9 @@ /// addCalledFunction - Add a function to the list of functions called by this /// one. void addCalledFunction(CallSite CS, CallGraphNode *M) { + assert(!CS.getInstruction() || + !CS.getCalledFunction() || + !CS.getCalledFunction()->isIntrinsic()); CalledFunctions.push_back(std::make_pair(CS.getInstruction(), M)); M->AddRef(); } Modified: llvm/trunk/lib/Analysis/IPA/CallGraph.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IPA/CallGraph.cpp?rev=132797&r1=132796&r2=132797&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/IPA/CallGraph.cpp (original) +++ llvm/trunk/lib/Analysis/IPA/CallGraph.cpp Thu Jun 9 14:46:27 2011 @@ -148,7 +148,7 @@ for (BasicBlock::iterator II = BB->begin(), IE = BB->end(); II != IE; ++II) { CallSite CS(cast(II)); - if (CS && !isa(II)) { + if (CS && !isa(II)) { const Function *Callee = CS.getCalledFunction(); if (Callee) Node->addCalledFunction(CS, getOrInsertFunction(Callee)); Modified: llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp?rev=132797&r1=132796&r2=132797&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp (original) +++ llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp Thu Jun 9 14:46:27 2011 @@ -245,8 +245,8 @@ for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) { - CallSite CS(cast(I)); - if (!CS || isa(I)) continue; + CallSite CS(cast(I)); + if (!CS || isa(I)) continue; // If this call site already existed in the callgraph, just verify it // matches up to expectations and remove it from CallSites. Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp?rev=132797&r1=132796&r2=132797&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Thu Jun 9 14:46:27 2011 @@ -132,18 +132,6 @@ }; } -/// Replace all the instruction uses of a value with a different value. -/// This has the advantage of not screwing up the CallGraph. -static void replaceAllInsnUsesWith(Instruction *insn, Value *replacement) { - for (Value::use_iterator i = insn->use_begin(), e = insn->use_end(); - i != e; ) { - Use &use = i.getUse(); - ++i; - if (isa(use.getUser())) - use.set(replacement); - } -} - /// Get or create a target for the branch out of rewritten calls to /// llvm.eh.resume. BasicBlock *InvokeInliningInfo::getInnerUnwindDest() { @@ -196,14 +184,14 @@ // Create a phi for the exception value... InnerExceptionPHI = PHINode::Create(exn->getType(), phiCapacity, "exn.lpad-body", insertPoint); - replaceAllInsnUsesWith(exn, InnerExceptionPHI); + exn->replaceAllUsesWith(InnerExceptionPHI); selector->setArgOperand(0, exn); // restore this use InnerExceptionPHI->addIncoming(exn, OuterUnwindDest); // ...and the selector. InnerSelectorPHI = PHINode::Create(selector->getType(), phiCapacity, "selector.lpad-body", insertPoint); - replaceAllInsnUsesWith(selector, InnerSelectorPHI); + selector->replaceAllUsesWith(InnerSelectorPHI); InnerSelectorPHI->addIncoming(selector, OuterUnwindDest); // All done. @@ -547,15 +535,7 @@ ConstantInt::get(Type::getInt32Ty(Context), 1), ConstantInt::getFalse(Context) // isVolatile }; - CallInst *TheMemCpy = - CallInst::Create(MemCpyFn, CallArgs, CallArgs+5, "", TheCall); - - // If we have a call graph, update it. - if (CallGraph *CG = IFI.CG) { - CallGraphNode *MemCpyCGN = CG->getOrInsertFunction(MemCpyFn); - CallGraphNode *CallerNode = (*CG)[Caller]; - CallerNode->addCalledFunction(TheMemCpy, MemCpyCGN); - } + CallInst::Create(MemCpyFn, CallArgs, CallArgs+5, "", TheCall); // Uses of the argument in the function should use our new alloca // instead. @@ -767,12 +747,10 @@ if (hasLifetimeMarkers(AI)) continue; - CallInst *StartCall = builder.CreateLifetimeStart(AI); - if (IFI.CG) CallerNode->addCalledFunction(StartCall, StartCGN); + builder.CreateLifetimeStart(AI); for (unsigned ri = 0, re = Returns.size(); ri != re; ++ri) { IRBuilder<> builder(Returns[ri]); - CallInst *EndCall = builder.CreateLifetimeEnd(AI); - if (IFI.CG) CallerNode->addCalledFunction(EndCall, EndCGN); + builder.CreateLifetimeEnd(AI); } } } @@ -785,25 +763,14 @@ Function *StackSave = Intrinsic::getDeclaration(M, Intrinsic::stacksave); Function *StackRestore=Intrinsic::getDeclaration(M,Intrinsic::stackrestore); - // If we are preserving the callgraph, add edges to the stacksave/restore - // functions for the calls we insert. - CallGraphNode *StackSaveCGN = 0, *StackRestoreCGN = 0, *CallerNode = 0; - if (CallGraph *CG = IFI.CG) { - StackSaveCGN = CG->getOrInsertFunction(StackSave); - StackRestoreCGN = CG->getOrInsertFunction(StackRestore); - CallerNode = (*CG)[Caller]; - } - // Insert the llvm.stacksave. CallInst *SavedPtr = CallInst::Create(StackSave, "savedstack", FirstNewBlock->begin()); - if (IFI.CG) CallerNode->addCalledFunction(SavedPtr, StackSaveCGN); // Insert a call to llvm.stackrestore before any return instructions in the // inlined function. for (unsigned i = 0, e = Returns.size(); i != e; ++i) { - CallInst *CI = CallInst::Create(StackRestore, SavedPtr, "", Returns[i]); - if (IFI.CG) CallerNode->addCalledFunction(CI, StackRestoreCGN); + CallInst::Create(StackRestore, SavedPtr, "", Returns[i]); } // Count the number of StackRestore calls we insert. @@ -815,8 +782,7 @@ for (Function::iterator BB = FirstNewBlock, E = Caller->end(); BB != E; ++BB) if (UnwindInst *UI = dyn_cast(BB->getTerminator())) { - CallInst *CI = CallInst::Create(StackRestore, SavedPtr, "", UI); - if (IFI.CG) CallerNode->addCalledFunction(CI, StackRestoreCGN); + CallInst::Create(StackRestore, SavedPtr, "", UI); ++NumStackRestores; } } From grosbach at apple.com Thu Jun 9 12:52:24 2011 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 09 Jun 2011 12:52:24 -0700 Subject: [llvm-commits] [llvm] r132676 - in /llvm/trunk: lib/CodeGen/SelectionDAG/FastISel.cpp test/CodeGen/X86/fast-isel-agg-constant.ll In-Reply-To: <20110609194839.GA45739@freebsd.org> References: <20110606153822.GA6591@freebsd.org> <20110609080819.GA4929@freebsd.org> <969FF868-AE98-4F22-AABD-D59D3C483793@apple.com> <20110609194839.GA45739@freebsd.org> Message-ID: <85D18316-EFC8-4370-9363-7B0961DE4420@apple.com> On Jun 9, 2011, at 12:48 PM, Roman Divacky wrote: > On Thu, Jun 09, 2011 at 11:22:41AM -0700, Jim Grosbach wrote: >> >> On Jun 9, 2011, at 1:08 AM, Roman Divacky wrote: >> >>> On Wed, Jun 08, 2011 at 11:08:36PM -0700, Eric Christopher wrote: >>>> >>>> On Jun 6, 2011, at 8:38 AM, Roman Divacky wrote: >>>> >>>>> OK to commit? Or is there a better way to distinguish those two >>>>> asm dialects? >>>> >>>> Maybe check the Subtarget instead? >>> >>> Where do I get it in MCExpr? >> >> If at all possible, we want to avoid the Subtarget in MC layer operations. There are a few places it's done, but it's a layering violation that we're trying very hard to avoid. Long term, we want to refactor the target machine to allow us to decouple it from MC. >> >> For purposes of something like this, you would theoretically just use the target triple. That is, if the triple specifies the target is Darwin (or not), behave accordingly. I don't think the triple is explicitly threaded through MC, though, so other than conceptually, I don't think that helps you much. > > The thing is that in MCExpr there's absolutely nothing related to triples etc. > It's just a pure container for an expression. Nothing from the outside world > is there :) > > Thats why I introduced the two new variant kinds, to distinguish the two > dialects. Yeah. It's a bit of an ugly solution, but it's pretty much necessary for now. IIRC, there are precedent examples of the same thing in there. We really need a target-hook that has access to the triple level information for this sort of thing, but there's no such beast right now. -Jim From rafael.espindola at gmail.com Thu Jun 9 12:54:42 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 09 Jun 2011 19:54:42 -0000 Subject: [llvm-commits] [llvm] r132798 - /llvm/trunk/lib/CodeGen/TailDuplication.cpp Message-ID: <20110609195442.42DFB2A6C12C@llvm.org> Author: rafael Date: Thu Jun 9 14:54:42 2011 New Revision: 132798 URL: http://llvm.org/viewvc/llvm-project?rev=132798&view=rev Log: Refactor some checks into shouldTailDuplicate. Update comments. No functionality change. Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=132798&r1=132797&r2=132798&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original) +++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Thu Jun 9 14:54:42 2011 @@ -91,6 +91,8 @@ SmallVector &TDBBs, SmallSetVector &Succs); bool TailDuplicateBlocks(MachineFunction &MF); + bool shouldTailDuplicate(const MachineFunction &MF, + MachineBasicBlock &TailBB); bool TailDuplicate(MachineBasicBlock *TailBB, MachineFunction &MF, SmallVector &TDBBs, SmallVector &Copies); @@ -184,10 +186,6 @@ if (NumTails == TailDupLimit) break; - // Only duplicate blocks that end with unconditional branches. - if (MBB->canFallThrough()) - continue; - // Save the successors list. SmallSetVector Succs(MBB->succ_begin(), MBB->succ_end()); @@ -450,14 +448,15 @@ } } -/// TailDuplicate - If it is profitable, duplicate TailBB's contents in each -/// of its predecessors. +/// shouldTailDuplicate - Determine if it is profitable to duplicate this block. bool -TailDuplicatePass::TailDuplicate(MachineBasicBlock *TailBB, MachineFunction &MF, - SmallVector &TDBBs, - SmallVector &Copies) { - // Set the limit on the number of instructions to duplicate, with a default - // of one less than the tail-merge threshold. When optimizing for size, +TailDuplicatePass::shouldTailDuplicate(const MachineFunction &MF, + MachineBasicBlock &TailBB) { + // Only duplicate blocks that end with unconditional branches. + if (TailBB.canFallThrough()) + return false; + + // Set the limit on the cost to duplicate. When optimizing for size, // duplicate only one, because one branch instruction can be eliminated to // compensate for the duplication. unsigned MaxDuplicateCount; @@ -468,12 +467,12 @@ MaxDuplicateCount = TailDuplicateSize; if (PreRegAlloc) { - if (TailBB->empty()) + if (TailBB.empty()) return false; - const TargetInstrDesc &TID = TailBB->back().getDesc(); + const TargetInstrDesc &TID = TailBB.back().getDesc(); // Pre-regalloc tail duplication hurts compile time and doesn't help - // much except for indirect branches and returns. - if (!TID.isIndirectBranch() && !TID.isReturn()) + // much except for indirect branches. + if (!TID.isIndirectBranch()) return false; // If the target has hardware branch prediction that can handle indirect // branches, duplicating them can often make them predictable when there @@ -484,15 +483,15 @@ } // Don't try to tail-duplicate single-block loops. - if (TailBB->isSuccessor(TailBB)) + if (TailBB.isSuccessor(&TailBB)) return false; // Check the instructions in the block to determine whether tail-duplication // is invalid or unlikely to be profitable. unsigned InstrCount = 0; bool HasCall = false; - for (MachineBasicBlock::iterator I = TailBB->begin(); - I != TailBB->end(); ++I) { + for (MachineBasicBlock::const_iterator I = TailBB.begin(); I != TailBB.end(); + ++I) { // Non-duplicable things shouldn't be tail-duplicated. if (I->getDesc().isNotDuplicable()) return false; // Do not duplicate 'return' instructions if this is a pre-regalloc run. @@ -512,6 +511,18 @@ if (InstrCount > 1 && (PreRegAlloc && HasCall)) return false; + return true; +} + +/// TailDuplicate - If it is profitable, duplicate TailBB's contents in each +/// of its predecessors. +bool +TailDuplicatePass::TailDuplicate(MachineBasicBlock *TailBB, MachineFunction &MF, + SmallVector &TDBBs, + SmallVector &Copies) { + if (!shouldTailDuplicate(MF, *TailBB)) + return false; + DEBUG(dbgs() << "\n*** Tail-duplicating BB#" << TailBB->getNumber() << '\n'); // Iterate through all the unique predecessors and tail-duplicate this From rjmccall at apple.com Thu Jun 9 13:06:24 2011 From: rjmccall at apple.com (John McCall) Date: Thu, 09 Jun 2011 20:06:24 -0000 Subject: [llvm-commits] [llvm] r132799 - in /llvm/trunk: lib/Transforms/Utils/InlineFunction.cpp test/Transforms/Inline/inline_invoke.ll Message-ID: <20110609200624.DCFE42A6C12C@llvm.org> Author: rjmccall Date: Thu Jun 9 15:06:24 2011 New Revision: 132799 URL: http://llvm.org/viewvc/llvm-project?rev=132799&view=rev Log: SplitCriticalEdge can sometimes split the edge from an invoke to a landing pad, separating the exception and selector calls from the new lpad. Teaching it not to do that, or to properly adjust the CFG afterwards, is out of scope because it would require the other edges to the landing pad to be split as well (effectively). Instead, just recover from the most likely cases during inlining. The best long-term solution is to change the exception representation and commit to either requiring or not requiring the more complex edge-splitting logic; this is just a shorter-term hack. Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp llvm/trunk/test/Transforms/Inline/inline_invoke.ll Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp?rev=132799&r1=132798&r2=132799&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Thu Jun 9 15:06:24 2011 @@ -45,31 +45,199 @@ return InlineFunction(CallSite(II), IFI); } -/// [LIBUNWIND] Find the (possibly absent) call to @llvm.eh.selector in -/// the given landing pad. -static EHSelectorInst *findSelectorForLandingPad(BasicBlock *lpad) { - // The llvm.eh.exception call is required to be in the landing pad. - for (BasicBlock::iterator i = lpad->begin(), e = lpad->end(); i != e; i++) { +/// [LIBUNWIND] Look for an llvm.eh.exception call in the given block. +static EHExceptionInst *findExceptionInBlock(BasicBlock *bb) { + for (BasicBlock::iterator i = bb->begin(), e = bb->end(); i != e; i++) { EHExceptionInst *exn = dyn_cast(i); - if (!exn) continue; + if (exn) return exn; + } + + return 0; +} - EHSelectorInst *selector = 0; - for (Instruction::use_iterator - ui = exn->use_begin(), ue = exn->use_end(); ui != ue; ++ui) { - EHSelectorInst *sel = dyn_cast(*ui); - if (!sel) continue; +/// [LIBUNWIND] Look for the 'best' llvm.eh.selector instruction for +/// the given llvm.eh.exception call. +static EHSelectorInst *findSelectorForException(EHExceptionInst *exn) { + BasicBlock *exnBlock = exn->getParent(); + + EHSelectorInst *outOfBlockSelector = 0; + for (Instruction::use_iterator + ui = exn->use_begin(), ue = exn->use_end(); ui != ue; ++ui) { + EHSelectorInst *sel = dyn_cast(*ui); + if (!sel) continue; + + // Immediately accept an eh.selector in the same block as the + // excepton call. + if (sel->getParent() == exnBlock) return sel; - // Immediately accept an eh.selector in the landing pad. - if (sel->getParent() == lpad) return sel; + // Otherwise, use the first selector we see. + if (!outOfBlockSelector) outOfBlockSelector = sel; + } - // Otherwise, use the first selector we see. - if (!selector) selector = sel; - } + return outOfBlockSelector; +} +/// [LIBUNWIND] Find the (possibly absent) call to @llvm.eh.selector +/// in the given landing pad. In principle, llvm.eh.exception is +/// required to be in the landing pad; in practice, SplitCriticalEdge +/// can break that invariant, and then inlining can break it further. +/// There's a real need for a reliable solution here, but until that +/// happens, we have some fragile workarounds here. +static EHSelectorInst *findSelectorForLandingPad(BasicBlock *lpad) { + // Look for an exception call in the actual landing pad. + EHExceptionInst *exn = findExceptionInBlock(lpad); + if (exn) return findSelectorForException(exn); + + // Okay, if that failed, look for one in an obvious successor. If + // we find one, we'll fix the IR by moving things back to the + // landing pad. + + bool dominates = true; // does the lpad dominate the exn call + BasicBlock *nonDominated = 0; // if not, the first non-dominated block + BasicBlock *lastDominated = 0; // and the block which branched to it + + BasicBlock *exnBlock = lpad; + + // We need to protect against lpads that lead into infinite loops. + SmallPtrSet visited; + visited.insert(exnBlock); + + do { + // We're not going to apply this hack to anything more complicated + // than a series of unconditional branches, so if the block + // doesn't terminate in an unconditional branch, just fail. More + // complicated cases can arise when, say, sinking a call into a + // split unwind edge and then inlining it; but that can do almost + // *anything* to the CFG, including leaving the selector + // completely unreachable. The only way to fix that properly is + // to (1) prohibit transforms which move the exception or selector + // values away from the landing pad, e.g. by producing them with + // instructions that are pinned to an edge like a phi, or + // producing them with not-really-instructions, and (2) making + // transforms which split edges deal with that. + BranchInst *branch = dyn_cast(&exnBlock->back()); + if (!branch || branch->isConditional()) return 0; + + BasicBlock *successor = branch->getSuccessor(0); + + // Fail if we found an infinite loop. + if (!visited.insert(successor)) return 0; + + // If the successor isn't dominated by exnBlock: + if (!successor->getSinglePredecessor()) { + // We don't want to have to deal with threading the exception + // through multiple levels of phi, so give up if we've already + // followed a non-dominating edge. + if (!dominates) return 0; + + // Otherwise, remember this as a non-dominating edge. + dominates = false; + nonDominated = successor; + lastDominated = exnBlock; + } + + exnBlock = successor; + + // Can we stop here? + exn = findExceptionInBlock(exnBlock); + } while (!exn); + + // Look for a selector call for the exception we found. + EHSelectorInst *selector = findSelectorForException(exn); + if (!selector) return 0; + + // The easy case is when the landing pad still dominates the + // exception call, in which case we can just move both calls back to + // the landing pad. + if (dominates) { + selector->moveBefore(lpad->getFirstNonPHI()); + exn->moveBefore(selector); return selector; } - return 0; + // Otherwise, we have to split at the first non-dominating block. + // The CFG looks basically like this: + // lpad: + // phis_0 + // insnsAndBranches_1 + // br label %nonDominated + // nonDominated: + // phis_2 + // insns_3 + // %exn = call i8* @llvm.eh.exception() + // insnsAndBranches_4 + // %selector = call @llvm.eh.selector(i8* %exn, ... + // We need to turn this into: + // lpad: + // phis_0 + // %exn0 = call i8* @llvm.eh.exception() + // %selector0 = call @llvm.eh.selector(i8* %exn0, ... + // insnsAndBranches_1 + // br label %split // from lastDominated + // nonDominated: + // phis_2 (without edge from lastDominated) + // %exn1 = call i8* @llvm.eh.exception() + // %selector1 = call i8* @llvm.eh.selector(i8* %exn1, ... + // br label %split + // split: + // phis_2 (edge from lastDominated, edge from split) + // %exn = phi ... + // %selector = phi ... + // insns_3 + // insnsAndBranches_4 + + assert(nonDominated); + assert(lastDominated); + + // First, make clones of the intrinsics to go in lpad. + EHExceptionInst *lpadExn = cast(exn->clone()); + EHSelectorInst *lpadSelector = cast(selector->clone()); + lpadSelector->setArgOperand(0, lpadExn); + lpadSelector->insertBefore(lpad->getFirstNonPHI()); + lpadExn->insertBefore(lpadSelector); + + // Split the non-dominated block. + BasicBlock *split = + nonDominated->splitBasicBlock(nonDominated->getFirstNonPHI(), + nonDominated->getName() + ".lpad-fix"); + + // Redirect the last dominated branch there. + cast(lastDominated->back()).setSuccessor(0, split); + + // Move the existing intrinsics to the end of the old block. + selector->moveBefore(&nonDominated->back()); + exn->moveBefore(selector); + + Instruction *splitIP = &split->front(); + + // For all the phis in nonDominated, make a new phi in split to join + // that phi with the edge from lastDominated. + for (BasicBlock::iterator + i = nonDominated->begin(), e = nonDominated->end(); i != e; ++i) { + PHINode *phi = dyn_cast(i); + if (!phi) break; + + PHINode *splitPhi = PHINode::Create(phi->getType(), 2, phi->getName(), + splitIP); + phi->replaceAllUsesWith(splitPhi); + splitPhi->addIncoming(phi, nonDominated); + splitPhi->addIncoming(phi->removeIncomingValue(lastDominated), + lastDominated); + } + + // Make new phis for the exception and selector. + PHINode *exnPhi = PHINode::Create(exn->getType(), 2, "", splitIP); + exn->replaceAllUsesWith(exnPhi); + selector->setArgOperand(0, exn); // except for this use + exnPhi->addIncoming(exn, nonDominated); + exnPhi->addIncoming(lpadExn, lastDominated); + + PHINode *selectorPhi = PHINode::Create(selector->getType(), 2, "", splitIP); + selector->replaceAllUsesWith(selectorPhi); + selectorPhi->addIncoming(selector, nonDominated); + selectorPhi->addIncoming(lpadSelector, lastDominated); + + return lpadSelector; } namespace { @@ -726,18 +894,6 @@ // Leave lifetime markers for the static alloca's, scoping them to the // function we just inlined. if (!IFI.StaticAllocas.empty()) { - // Also preserve the call graph, if applicable. - CallGraphNode *StartCGN = 0, *EndCGN = 0, *CallerNode = 0; - if (CallGraph *CG = IFI.CG) { - Function *Start = Intrinsic::getDeclaration(Caller->getParent(), - Intrinsic::lifetime_start); - Function *End = Intrinsic::getDeclaration(Caller->getParent(), - Intrinsic::lifetime_end); - StartCGN = CG->getOrInsertFunction(Start); - EndCGN = CG->getOrInsertFunction(End); - CallerNode = (*CG)[Caller]; - } - IRBuilder<> builder(FirstNewBlock->begin()); for (unsigned ai = 0, ae = IFI.StaticAllocas.size(); ai != ae; ++ai) { AllocaInst *AI = IFI.StaticAllocas[ai]; Modified: llvm/trunk/test/Transforms/Inline/inline_invoke.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/Inline/inline_invoke.ll?rev=132799&r1=132798&r2=132799&view=diff ============================================================================== --- llvm/trunk/test/Transforms/Inline/inline_invoke.ll (original) +++ llvm/trunk/test/Transforms/Inline/inline_invoke.ll Thu Jun 9 15:06:24 2011 @@ -16,6 +16,8 @@ declare void @use(i32) nounwind +declare void @opaque() + declare i8* @llvm.eh.exception() nounwind readonly declare i32 @llvm.eh.selector(i8*, i8*, ...) nounwind @@ -217,8 +219,8 @@ ; CHECK: call void @llvm.eh.resume(i8* [[EXNJ1]], i32 [[SELJ1]]) -;; Test 2 - Don't make invalid IR for inlines into landing pads without eh.exception calls +;; Test 2 - Don't make invalid IR for inlines into landing pads without eh.exception calls define void @test2_out() uwtable ssp { entry: invoke void @test0_in() @@ -243,3 +245,92 @@ ; CHECK-NEXT: unwind label %[[LPAD2]] ; CHECK: invoke void @_ZN1AD1Ev(%struct.A* [[A]]) ; CHECK-NEXT: unwind label %[[LPAD]] + + +;; Test 3 - Deal correctly with split unwind edges. +define void @test3_out() uwtable ssp { +entry: + invoke void @test0_in() + to label %ret unwind label %lpad + +ret: + ret void + +lpad: + br label %lpad.cont + +lpad.cont: + %exn = call i8* @llvm.eh.exception() nounwind + %eh.selector = call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exn, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i8* bitcast (i8** @_ZTIi to i8*)) nounwind + call void @_ZSt9terminatev() + unreachable +} + +; CHECK: define void @test3_out() +; CHECK: call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* {{%.*}}, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i32 0, i8* bitcast (i8** @_ZTIi to i8*)) +; CHECK-NEXT: invoke void @_ZN1AD1Ev( +; CHECK-NEXT: to label %[[L:[^\s]+]] unwind +; CHECK: [[L]]: +; CHECK-NEXT: br label %[[JOIN:[^\s]+]] +; CHECK: [[JOIN]]: +; CHECK-NEXT: phi +; CHECK-NEXT: phi +; CHECK-NEXT: br label %lpad.cont +; CHECK: lpad.cont: +; CHECK-NEXT: call void @_ZSt9terminatev() + + +;; Test 4 - Split unwind edges with a dominance problem +define void @test4_out() uwtable ssp { +entry: + invoke void @test0_in() + to label %cont unwind label %lpad.crit + +cont: + invoke void @opaque() + to label %ret unwind label %lpad + +ret: + ret void + +lpad.crit: + call void @opaque() nounwind + br label %lpad + +lpad: + %phi = phi i32 [ 0, %lpad.crit ], [ 1, %cont ] + %exn = call i8* @llvm.eh.exception() nounwind + %eh.selector = call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exn, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i8* bitcast (i8** @_ZTIi to i8*)) nounwind + call void @use(i32 %phi) + call void @_ZSt9terminatev() + unreachable +} + +; CHECK: define void @test4_out() +; CHECK: call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* {{%.*}}, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i32 0, i8* bitcast (i8** @_ZTIi to i8*)) +; CHECK-NEXT: invoke void @_ZN1AD1Ev( +; CHECK-NEXT: to label %[[L:[^\s]+]] unwind +; CHECK: [[L]]: +; CHECK-NEXT: br label %[[JOIN:[^\s]+]] +; CHECK: invoke void @opaque() +; CHECK-NEXT: unwind label %lpad +; CHECK: lpad.crit: +; CHECK-NEXT: call i8* @llvm.eh.exception() +; CHECK-NEXT: call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %4, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i8* bitcast (i8** @_ZTIi to i8*)) +; CHECK-NEXT: br label %[[JOIN]] +; CHECK: [[JOIN]]: +; CHECK-NEXT: phi i8* +; CHECK-NEXT: phi i32 +; CHECK-NEXT: call void @opaque() nounwind +; CHECK-NEXT: br label %[[FIX:[^\s]+]] +; CHECK: lpad: +; CHECK-NEXT: [[T0:%.*]] = phi i32 [ 1, %cont ] +; CHECK-NEXT: call i8* @llvm.eh.exception() nounwind +; CHECK-NEXT: call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exn, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i8* bitcast (i8** @_ZTIi to i8*)) +; CHECK-NEXT: br label %[[FIX]] +; CHECK: [[FIX]]: +; CHECK-NEXT: [[T1:%.*]] = phi i32 [ [[T0]], %lpad ], [ 0, %[[JOIN]] ] +; CHECK-NEXT: phi i8* +; CHECK-NEXT: phi i32 +; CHECK-NEXT: call void @use(i32 [[T1]]) +; CHECK-NEXT: call void @_ZSt9terminatev() From johnny.chen at apple.com Thu Jun 9 13:11:46 2011 From: johnny.chen at apple.com (Johnny Chen) Date: Thu, 09 Jun 2011 20:11:46 -0000 Subject: [llvm-commits] [llvm] r132800 - /llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp Message-ID: <20110609201146.4A8262A6C12C@llvm.org> Author: johnny Date: Thu Jun 9 15:11:46 2011 New Revision: 132800 URL: http://llvm.org/viewvc/llvm-project?rev=132800&view=rev Log: Modify comment. Modified: llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp Modified: llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp?rev=132800&r1=132799&r2=132800&view=diff ============================================================================== --- llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp (original) +++ llvm/trunk/examples/HowToUseJIT/HowToUseJIT.cpp Thu Jun 9 15:11:46 2011 @@ -91,7 +91,7 @@ // Now, function add1 is ready. - // Now we going to create function `foo', which returns an int and takes no + // Now we're going to create function `foo', which returns an int and takes no // arguments. Function *FooF = cast(M->getOrInsertFunction("foo", Type::getInt32Ty(Context), From rdivacky at freebsd.org Thu Jun 9 13:18:22 2011 From: rdivacky at freebsd.org (Roman Divacky) Date: Thu, 9 Jun 2011 22:18:22 +0200 Subject: [llvm-commits] [llvm] r132676 - in /llvm/trunk: lib/CodeGen/SelectionDAG/FastISel.cpp test/CodeGen/X86/fast-isel-agg-constant.ll In-Reply-To: <85D18316-EFC8-4370-9363-7B0961DE4420@apple.com> References: <20110606153822.GA6591@freebsd.org> <20110609080819.GA4929@freebsd.org> <969FF868-AE98-4F22-AABD-D59D3C483793@apple.com> <20110609194839.GA45739@freebsd.org> <85D18316-EFC8-4370-9363-7B0961DE4420@apple.com> Message-ID: <20110609201822.GA48691@freebsd.org> On Thu, Jun 09, 2011 at 12:52:24PM -0700, Jim Grosbach wrote: > > On Jun 9, 2011, at 12:48 PM, Roman Divacky wrote: > > > On Thu, Jun 09, 2011 at 11:22:41AM -0700, Jim Grosbach wrote: > >> > >> On Jun 9, 2011, at 1:08 AM, Roman Divacky wrote: > >> > >>> On Wed, Jun 08, 2011 at 11:08:36PM -0700, Eric Christopher wrote: > >>>> > >>>> On Jun 6, 2011, at 8:38 AM, Roman Divacky wrote: > >>>> > >>>>> OK to commit? Or is there a better way to distinguish those two > >>>>> asm dialects? > >>>> > >>>> Maybe check the Subtarget instead? > >>> > >>> Where do I get it in MCExpr? > >> > >> If at all possible, we want to avoid the Subtarget in MC layer operations. There are a few places it's done, but it's a layering violation that we're trying very hard to avoid. Long term, we want to refactor the target machine to allow us to decouple it from MC. > >> > >> For purposes of something like this, you would theoretically just use the target triple. That is, if the triple specifies the target is Darwin (or not), behave accordingly. I don't think the triple is explicitly threaded through MC, though, so other than conceptually, I don't think that helps you much. > > > > The thing is that in MCExpr there's absolutely nothing related to triples etc. > > It's just a pure container for an expression. Nothing from the outside world > > is there :) > > > > Thats why I introduced the two new variant kinds, to distinguish the two > > dialects. > > Yeah. It's a bit of an ugly solution, but it's pretty much necessary for now. IIRC, there are precedent examples of the same thing in there. We really need a target-hook that has access to the triple level information for this sort of thing, but there's no such beast right now. So is the patch OK to commit? From baldrick at free.fr Thu Jun 9 13:15:01 2011 From: baldrick at free.fr (Duncan Sands) Date: Thu, 09 Jun 2011 20:15:01 -0000 Subject: [llvm-commits] [dragonegg] r132801 - in /dragonegg/trunk: include/dragonegg/Internals.h src/Constants.cpp src/Convert.cpp Message-ID: <20110609201501.E962E2A6C12C@llvm.org> Author: baldrick Date: Thu Jun 9 15:15:01 2011 New Revision: 132801 URL: http://llvm.org/viewvc/llvm-project?rev=132801&view=rev Log: Avoid unused variable compiler warnings when assertions are disabled. Modified: dragonegg/trunk/include/dragonegg/Internals.h dragonegg/trunk/src/Constants.cpp dragonegg/trunk/src/Convert.cpp Modified: dragonegg/trunk/include/dragonegg/Internals.h URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/include/dragonegg/Internals.h?rev=132801&r1=132800&r2=132801&view=diff ============================================================================== --- dragonegg/trunk/include/dragonegg/Internals.h (original) +++ dragonegg/trunk/include/dragonegg/Internals.h Thu Jun 9 15:15:01 2011 @@ -114,6 +114,7 @@ /// give up the ghost, quit miserably. inline void LLVM_ATTRIBUTE_NORETURN DieAbjectly(const char *Message) { llvm_unreachable(Message); + (void)Message; // Avoid unused variable warning when assertions are disabled. } inline void LLVM_ATTRIBUTE_NORETURN DieAbjectly(const char *Message, union gimple_statement_d *stmt){ Modified: dragonegg/trunk/src/Constants.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Constants.cpp?rev=132801&r1=132800&r2=132801&view=diff ============================================================================== --- dragonegg/trunk/src/Constants.cpp (original) +++ dragonegg/trunk/src/Constants.cpp Thu Jun 9 15:15:01 2011 @@ -321,13 +321,12 @@ case Type::ArrayTyID: { const ArrayType *ATy = cast(Ty); const Type *EltTy = ATy->getElementType(); - const unsigned NumElts = ATy->getNumElements(); const unsigned Stride = getTargetData().getTypeAllocSizeInBits(EltTy); assert(Stride > 0 && "Store size smaller than alloc size?"); // Elements with indices in [FirstElt, LastElt) overlap the range. unsigned FirstElt = R.getFirst() / Stride; unsigned LastElt = (R.getLast() + Stride - 1) / Stride; - assert(LastElt <= NumElts && "Store size bigger than array?"); + assert(LastElt <= ATy->getNumElements() && "Store size bigger than array?"); // Visit all elements that overlap the requested range, accumulating their // bits in Bits. BitSlice Bits; @@ -369,13 +368,12 @@ case Type::VectorTyID: { const VectorType *VTy = cast(Ty); const Type *EltTy = VTy->getElementType(); - const unsigned NumElts = VTy->getNumElements(); const unsigned Stride = getTargetData().getTypeAllocSizeInBits(EltTy); assert(Stride > 0 && "Store size smaller than alloc size?"); // Elements with indices in [FirstElt, LastElt) overlap the range. unsigned FirstElt = R.getFirst() / Stride; unsigned LastElt = (R.getLast() + Stride - 1) / Stride; - assert(LastElt <= NumElts && "Store size bigger than vector?"); + assert(LastElt <= VTy->getNumElements() && "Store size bigger than vector?"); // Visit all elements that overlap the requested range, accumulating their // bits in Bits. BitSlice Bits; @@ -711,6 +709,7 @@ std::vector Buffer(SizeInChars); unsigned CharsWritten = native_encode_expr(exp, &Buffer[0], SizeInChars); assert(CharsWritten == SizeInChars && "Failed to fully encode expression!"); + (void)CharsWritten; // Avoid unused variable warning when assertions disabled. // Turn it into an LLVM byte array. return ConstantArray::get(Context, StringRef((char *)&Buffer[0], SizeInChars), /*AddNull*/false); Modified: dragonegg/trunk/src/Convert.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=132801&r1=132800&r2=132801&view=diff ============================================================================== --- dragonegg/trunk/src/Convert.cpp (original) +++ dragonegg/trunk/src/Convert.cpp Thu Jun 9 15:15:01 2011 @@ -7146,13 +7146,13 @@ tree type = TREE_TYPE(op0); if (TREE_CODE(type) == COMPLEX_TYPE) { - tree elt_type = TREE_TYPE(type); Value *LHSr, *LHSi; SplitComplex(LHS, LHSr, LHSi); Value *RHSr, *RHSi; SplitComplex(RHS, RHSr, RHSi); Value *DSTr, *DSTi; // (a+ib) / (c+id) = ((ac+bd)/(cc+dd)) + i((bc-ad)/(cc+dd)) - assert (SCALAR_FLOAT_TYPE_P(elt_type) && "RDIV_EXPR not floating point!"); + assert (SCALAR_FLOAT_TYPE_P(TREE_TYPE(type)) && + "RDIV_EXPR not floating point!"); Value *Tmp1 = Builder.CreateFMul(LHSr, RHSr); // a*c Value *Tmp2 = Builder.CreateFMul(LHSi, RHSi); // b*d Value *Tmp3 = Builder.CreateFAdd(Tmp1, Tmp2); // ac+bd From grosbach at apple.com Thu Jun 9 13:24:38 2011 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 09 Jun 2011 13:24:38 -0700 Subject: [llvm-commits] [llvm] r132676 - in /llvm/trunk: lib/CodeGen/SelectionDAG/FastISel.cpp test/CodeGen/X86/fast-isel-agg-constant.ll In-Reply-To: <20110609201822.GA48691@freebsd.org> References: <20110606153822.GA6591@freebsd.org> <20110609080819.GA4929@freebsd.org> <969FF868-AE98-4F22-AABD-D59D3C483793@apple.com> <20110609194839.GA45739@freebsd.org> <85D18316-EFC8-4370-9363-7B0961DE4420@apple.com> <20110609201822.GA48691@freebsd.org> Message-ID: On Jun 9, 2011, at 1:18 PM, Roman Divacky wrote: > On Thu, Jun 09, 2011 at 12:52:24PM -0700, Jim Grosbach wrote: >> >> On Jun 9, 2011, at 12:48 PM, Roman Divacky wrote: >> >>> On Thu, Jun 09, 2011 at 11:22:41AM -0700, Jim Grosbach wrote: >>>> >>>> On Jun 9, 2011, at 1:08 AM, Roman Divacky wrote: >>>> >>>>> On Wed, Jun 08, 2011 at 11:08:36PM -0700, Eric Christopher wrote: >>>>>> >>>>>> On Jun 6, 2011, at 8:38 AM, Roman Divacky wrote: >>>>>> >>>>>>> OK to commit? Or is there a better way to distinguish those two >>>>>>> asm dialects? >>>>>> >>>>>> Maybe check the Subtarget instead? >>>>> >>>>> Where do I get it in MCExpr? >>>> >>>> If at all possible, we want to avoid the Subtarget in MC layer operations. There are a few places it's done, but it's a layering violation that we're trying very hard to avoid. Long term, we want to refactor the target machine to allow us to decouple it from MC. >>>> >>>> For purposes of something like this, you would theoretically just use the target triple. That is, if the triple specifies the target is Darwin (or not), behave accordingly. I don't think the triple is explicitly threaded through MC, though, so other than conceptually, I don't think that helps you much. >>> >>> The thing is that in MCExpr there's absolutely nothing related to triples etc. >>> It's just a pure container for an expression. Nothing from the outside world >>> is there :) >>> >>> Thats why I introduced the two new variant kinds, to distinguish the two >>> dialects. >> >> Yeah. It's a bit of an ugly solution, but it's pretty much necessary for now. IIRC, there are precedent examples of the same thing in there. We really need a target-hook that has access to the triple level information for this sort of thing, but there's no such beast right now. > > So is the patch OK to commit? Yes. Sorry, should have said that explicitly before. As a minor detail, the comments here should be updated to reflect the different output. If I read things right: + VK_PPC_DARWIN_HA16, // ha16(symbol) + VK_PPC_DARWIN_LO16, // lo16(symbol) + VK_PPC_GAS_HA16, // ha16(symbol) <-- Should be "ha(symbol)" + VK_PPC_GAS_LO16 // lo16(symbol) <-- Should be "l(symbol)" -Jim From rafael.espindola at gmail.com Thu Jun 9 13:25:55 2011 From: rafael.espindola at gmail.com (Rafael Avila de Espindola) Date: Thu, 09 Jun 2011 16:25:55 -0400 Subject: [llvm-commits] [llvm] r132797 - in /llvm/trunk: include/llvm/Analysis/CallGraph.h lib/Analysis/IPA/CallGraph.cpp lib/Analysis/IPA/CallGraphSCCPass.cpp lib/Transforms/Utils/InlineFunction.cpp In-Reply-To: <20110609194627.D56E42A6C12C@llvm.org> References: <20110609194627.D56E42A6C12C@llvm.org> Message-ID: <4DF12C53.3010401@gmail.com> On 11-06-09 03:46 PM, John McCall wrote: > Author: rjmccall > Date: Thu Jun 9 14:46:27 2011 > New Revision: 132797 > > URL: http://llvm.org/viewvc/llvm-project?rev=132797&view=rev > Log: > Teach the CallGraph to ignore calls to intrinsics. > > looks like this broke selfhost: clang-3.0: /home/espindola/llvm/llvm/lib/Analysis/IPA/CallGraph.cpp:284: void llvm::CallGraphNode::removeCallEdgeFor(llvm::CallSite): Assertion `I != CalledFunctions.end() && "Cannot find callsite to remove!"' failed. Stack dump: 0. Program arguments: /home/espindola/tmpfs/build/bin/clang-3.0 -cc1 -triple x86_64-unknown-linux-gnu -S -disable-free -main-file-name ARMDecoderEmitter.cpp -pic-level 2 -mdisable-fp-elim -masm-verbose -mconstructor-aliases -munwind-tables -target-cpu x86-64 -momit-leaf-frame-pointer -coverage-file ARMDecoderEmitter.s -resource-dir /home/espindola/tmpfs/build/bin/../lib/clang/3.0 -O3 -Wall -W -Wno-unused-parameter -Wwrite-strings -Wno-long-long -pedantic -fconst-strings -fdeprecated-macro -ferror-limit 19 -fmessage-length 137 -fcxx-exceptions -fexceptions -fgnu-runtime -fdiagnostics-show-option -fcolor-diagnostics -o ARMDecoderEmitter.s -x c++-cpp-output /home/espindola/tmpfs/ARMDecoderEmitter.ii 1. parser at end of file 2. Per-module optimization passes 3. Running pass 'CallGraph Pass Manager' on module '/home/espindola/tmpfs/ARMDecoderEmitter.ii'. Cheers, Rafael From rdivacky at freebsd.org Thu Jun 9 13:25:38 2011 From: rdivacky at freebsd.org (Roman Divacky) Date: Thu, 09 Jun 2011 20:25:38 -0000 Subject: [llvm-commits] [llvm] r132802 - in /llvm/trunk: include/llvm/MC/MCExpr.h lib/MC/MCExpr.cpp lib/Target/PowerPC/PPC.h lib/Target/PowerPC/PPCAsmPrinter.cpp lib/Target/PowerPC/PPCMCInstLower.cpp Message-ID: <20110609202538.8D45C2A6C12C@llvm.org> Author: rdivacky Date: Thu Jun 9 15:25:38 2011 New Revision: 132802 URL: http://llvm.org/viewvc/llvm-project?rev=132802&view=rev Log: Fix emission of PPC64 assembler on non-darwin platforms by splitting VK_PPC_{HA,LO}16 into darwin and gas variants. Darwin wants {ha,lo}16(symbol) while gnu as wants symbol@{ha,l}. Modified: llvm/trunk/include/llvm/MC/MCExpr.h llvm/trunk/lib/MC/MCExpr.cpp llvm/trunk/lib/Target/PowerPC/PPC.h llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp llvm/trunk/lib/Target/PowerPC/PPCMCInstLower.cpp Modified: llvm/trunk/include/llvm/MC/MCExpr.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCExpr.h?rev=132802&r1=132801&r2=132802&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCExpr.h (original) +++ llvm/trunk/include/llvm/MC/MCExpr.h Thu Jun 9 15:25:38 2011 @@ -171,8 +171,10 @@ VK_ARM_GOTTPOFF, VK_PPC_TOC, - VK_PPC_HA16, // ha16(symbol) - VK_PPC_LO16 // lo16(symbol) + VK_PPC_DARWIN_HA16, // ha16(symbol) + VK_PPC_DARWIN_LO16, // lo16(symbol) + VK_PPC_GAS_HA16, // symbol at ha + VK_PPC_GAS_LO16 // symbol at l }; private: Modified: llvm/trunk/lib/MC/MCExpr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCExpr.cpp?rev=132802&r1=132801&r2=132802&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCExpr.cpp (original) +++ llvm/trunk/lib/MC/MCExpr.cpp Thu Jun 9 15:25:38 2011 @@ -42,8 +42,8 @@ // absolute names. bool UseParens = Sym.getName()[0] == '$'; - if (SRE.getKind() == MCSymbolRefExpr::VK_PPC_HA16 || - SRE.getKind() == MCSymbolRefExpr::VK_PPC_LO16) { + if (SRE.getKind() == MCSymbolRefExpr::VK_PPC_DARWIN_HA16 || + SRE.getKind() == MCSymbolRefExpr::VK_PPC_DARWIN_LO16) { OS << MCSymbolRefExpr::getVariantKindName(SRE.getKind()); UseParens = true; } @@ -61,8 +61,8 @@ SRE.getKind() == MCSymbolRefExpr::VK_ARM_GOTTPOFF) OS << MCSymbolRefExpr::getVariantKindName(SRE.getKind()); else if (SRE.getKind() != MCSymbolRefExpr::VK_None && - SRE.getKind() != MCSymbolRefExpr::VK_PPC_HA16 && - SRE.getKind() != MCSymbolRefExpr::VK_PPC_LO16) + SRE.getKind() != MCSymbolRefExpr::VK_PPC_DARWIN_HA16 && + SRE.getKind() != MCSymbolRefExpr::VK_PPC_DARWIN_LO16) OS << '@' << MCSymbolRefExpr::getVariantKindName(SRE.getKind()); return; @@ -197,8 +197,10 @@ case VK_ARM_GOTTPOFF: return "(gottpoff)"; case VK_ARM_TLSGD: return "(tlsgd)"; case VK_PPC_TOC: return "toc"; - case VK_PPC_HA16: return "ha16"; - case VK_PPC_LO16: return "lo16"; + case VK_PPC_DARWIN_HA16: return "ha16"; + case VK_PPC_DARWIN_LO16: return "lo16"; + case VK_PPC_GAS_HA16: return "ha"; + case VK_PPC_GAS_LO16: return "l"; } } Modified: llvm/trunk/lib/Target/PowerPC/PPC.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPC.h?rev=132802&r1=132801&r2=132802&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPC.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPC.h Thu Jun 9 15:25:38 2011 @@ -43,7 +43,7 @@ TargetAsmBackend *createPPCAsmBackend(const Target &, const std::string &); void LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, - AsmPrinter &AP); + AsmPrinter &AP, bool isDarwin); extern Target ThePPC32Target; extern Target ThePPC64Target; Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp?rev=132802&r1=132801&r2=132802&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp Thu Jun 9 15:25:38 2011 @@ -344,7 +344,7 @@ } case PPC::LDtoc: { // Transform %X3 = LDtoc , %X2 - LowerPPCMachineInstrToMCInst(MI, TmpInst, *this); + LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin()); // Change the opcode to LD, and the global address operand to be a // reference to the TOC entry we will synthesize later. @@ -376,7 +376,7 @@ return; } - LowerPPCMachineInstrToMCInst(MI, TmpInst, *this); + LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin()); OutStreamer.EmitInstruction(TmpInst); } Modified: llvm/trunk/lib/Target/PowerPC/PPCMCInstLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCMCInstLower.cpp?rev=132802&r1=132801&r2=132802&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCMCInstLower.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCMCInstLower.cpp Thu Jun 9 15:25:38 2011 @@ -95,14 +95,14 @@ } static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol, - AsmPrinter &Printer) { + AsmPrinter &Printer, bool isDarwin) { MCContext &Ctx = Printer.OutContext; MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None; if (MO.getTargetFlags() & PPCII::MO_LO16) - RefKind = MCSymbolRefExpr::VK_PPC_LO16; + RefKind = isDarwin ? MCSymbolRefExpr::VK_PPC_DARWIN_LO16 : MCSymbolRefExpr::VK_PPC_GAS_LO16; else if (MO.getTargetFlags() & PPCII::MO_HA16) - RefKind = MCSymbolRefExpr::VK_PPC_HA16; + RefKind = isDarwin ? MCSymbolRefExpr::VK_PPC_DARWIN_HA16 : MCSymbolRefExpr::VK_PPC_GAS_HA16; // FIXME: This isn't right, but we don't have a good way to express this in // the MC Level, see below. @@ -130,7 +130,7 @@ } void llvm::LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, - AsmPrinter &AP) { + AsmPrinter &AP, bool isDarwin) { OutMI.setOpcode(MI->getOpcode()); for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { @@ -154,16 +154,17 @@ break; case MachineOperand::MO_GlobalAddress: case MachineOperand::MO_ExternalSymbol: - MCOp = GetSymbolRef(MO, GetSymbolFromOperand(MO, AP), AP); + MCOp = GetSymbolRef(MO, GetSymbolFromOperand(MO, AP), AP, isDarwin); break; case MachineOperand::MO_JumpTableIndex: - MCOp = GetSymbolRef(MO, AP.GetJTISymbol(MO.getIndex()), AP); + MCOp = GetSymbolRef(MO, AP.GetJTISymbol(MO.getIndex()), AP, isDarwin); break; case MachineOperand::MO_ConstantPoolIndex: - MCOp = GetSymbolRef(MO, AP.GetCPISymbol(MO.getIndex()), AP); + MCOp = GetSymbolRef(MO, AP.GetCPISymbol(MO.getIndex()), AP, isDarwin); break; case MachineOperand::MO_BlockAddress: - MCOp = GetSymbolRef(MO,AP.GetBlockAddressSymbol(MO.getBlockAddress()),AP); + MCOp = GetSymbolRef(MO,AP.GetBlockAddressSymbol(MO.getBlockAddress()),AP, + isDarwin); break; } From rjmccall at apple.com Thu Jun 9 13:31:09 2011 From: rjmccall at apple.com (John McCall) Date: Thu, 09 Jun 2011 20:31:09 -0000 Subject: [llvm-commits] [llvm] r132803 - /llvm/trunk/lib/Transforms/IPO/PruneEH.cpp Message-ID: <20110609203109.C75642A6C12C@llvm.org> Author: rjmccall Date: Thu Jun 9 15:31:09 2011 New Revision: 132803 URL: http://llvm.org/viewvc/llvm-project?rev=132803&view=rev Log: When deleting a basic block, remove call edges only for non-intrinsics. Modified: llvm/trunk/lib/Transforms/IPO/PruneEH.cpp Modified: llvm/trunk/lib/Transforms/IPO/PruneEH.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/PruneEH.cpp?rev=132803&r1=132802&r2=132803&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/PruneEH.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/PruneEH.cpp Thu Jun 9 15:31:09 2011 @@ -239,7 +239,7 @@ for (BasicBlock::iterator I = BB->end(), E = BB->begin(); I != E; ) { --I; if (CallInst *CI = dyn_cast(I)) { - if (!isa(I)) + if (!isa(I)) CGN->removeCallEdgeFor(CI); } else if (InvokeInst *II = dyn_cast(I)) CGN->removeCallEdgeFor(II); From echristo at apple.com Thu Jun 9 13:59:27 2011 From: echristo at apple.com (Eric Christopher) Date: Thu, 09 Jun 2011 13:59:27 -0700 Subject: [llvm-commits] [llvm] r132676 - in /llvm/trunk: lib/CodeGen/SelectionDAG/FastISel.cpp test/CodeGen/X86/fast-isel-agg-constant.ll In-Reply-To: <85D18316-EFC8-4370-9363-7B0961DE4420@apple.com> References: <20110606153822.GA6591@freebsd.org> <20110609080819.GA4929@freebsd.org> <969FF868-AE98-4F22-AABD-D59D3C483793@apple.com> <20110609194839.GA45739@freebsd.org> <85D18316-EFC8-4370-9363-7B0961DE4420@apple.com> Message-ID: <9BC5000C-E2A5-4E77-B163-33773F7F5D47@apple.com> >> >> The thing is that in MCExpr there's absolutely nothing related to triples etc. >> It's just a pure container for an expression. Nothing from the outside world >> is there :) >> >> Thats why I introduced the two new variant kinds, to distinguish the two >> dialects. > > Yeah. It's a bit of an ugly solution, but it's pretty much necessary for now. IIRC, there are precedent examples of the same thing in there. We really need a target-hook that has access to the triple level information for this sort of thing, but there's no such beast right now. Which is why I was mentioning using the subtarget. While MCExpr there isn't anything related to targets - at some point we need to know the subtarget to know how to emit relocation/expression information for assembly. There's absolutely no reason why we need two/multiple variants for each way that we'd like to print out a relocation/expression. -eric From rafael.espindola at gmail.com Thu Jun 9 13:55:42 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 09 Jun 2011 20:55:42 -0000 Subject: [llvm-commits] [llvm] r132805 - /llvm/trunk/lib/CodeGen/TailDuplication.cpp Message-ID: <20110609205542.172DC2A6C12C@llvm.org> Author: rafael Date: Thu Jun 9 15:55:41 2011 New Revision: 132805 URL: http://llvm.org/viewvc/llvm-project?rev=132805&view=rev Log: A PHI in this basic block is a use in another basic block. Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=132805&r1=132804&r2=132805&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original) +++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Thu Jun 9 15:55:41 2011 @@ -239,7 +239,7 @@ MachineOperand &UseMO = UI.getOperand(); MachineInstr *UseMI = &*UI; ++UI; - if (UseMI->getParent() == DefBB) + if (UseMI->getParent() == DefBB && !UseMI->isPHI()) continue; SSAUpdate.RewriteUse(UseMO); } From grosbach at apple.com Thu Jun 9 14:03:38 2011 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 09 Jun 2011 14:03:38 -0700 Subject: [llvm-commits] [llvm] r132676 - in /llvm/trunk: lib/CodeGen/SelectionDAG/FastISel.cpp test/CodeGen/X86/fast-isel-agg-constant.ll In-Reply-To: <9BC5000C-E2A5-4E77-B163-33773F7F5D47@apple.com> References: <20110606153822.GA6591@freebsd.org> <20110609080819.GA4929@freebsd.org> <969FF868-AE98-4F22-AABD-D59D3C483793@apple.com> <20110609194839.GA45739@freebsd.org> <85D18316-EFC8-4370-9363-7B0961DE4420@apple.com> <9BC5000C-E2A5-4E77-B163-33773F7F5D47@apple.com> Message-ID: <61506575-176C-490D-A068-04F00EBD450C@apple.com> On Jun 9, 2011, at 1:59 PM, Eric Christopher wrote: >>> >>> The thing is that in MCExpr there's absolutely nothing related to triples etc. >>> It's just a pure container for an expression. Nothing from the outside world >>> is there :) >>> >>> Thats why I introduced the two new variant kinds, to distinguish the two >>> dialects. >> >> Yeah. It's a bit of an ugly solution, but it's pretty much necessary for now. IIRC, there are precedent examples of the same thing in there. We really need a target-hook that has access to the triple level information for this sort of thing, but there's no such beast right now. > > Which is why I was mentioning using the subtarget. While MCExpr there isn't anything related to targets - at some point we need to know the subtarget to know how to emit relocation/expression information for assembly. There's absolutely no reason why we need two/multiple variants for each way that we'd like to print out a relocation/expression. The subtarget is part of the codegen layer. It's not available to MC*. I completely agree there shouldn't need to be multiple variants. MC does not currently have any other way to express this, however. -Jim * There are a few places this layering is broken. Those need to be removed, but it's a Big Deal(tm) to make that happen. From rafael.espindola at gmail.com Thu Jun 9 14:43:25 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 09 Jun 2011 21:43:25 -0000 Subject: [llvm-commits] [llvm] r132806 - /llvm/trunk/lib/CodeGen/TailDuplication.cpp Message-ID: <20110609214325.3D1EC2A6C12C@llvm.org> Author: rafael Date: Thu Jun 9 16:43:25 2011 New Revision: 132806 URL: http://llvm.org/viewvc/llvm-project?rev=132806&view=rev Log: AnalyzeBranch modifies the bb, but we don't want to modify a bb with eh edges. Swap the order of the checks to avoid it. Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=132806&r1=132805&r2=132806&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original) +++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Thu Jun 9 16:43:25 2011 @@ -541,13 +541,13 @@ MachineBasicBlock *PredTBB, *PredFBB; SmallVector PredCond; + // EH edges are ignored by AnalyzeBranch. + if (PredBB->succ_size() != 1) + continue; if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true)) continue; if (!PredCond.empty()) continue; - // EH edges are ignored by AnalyzeBranch. - if (PredBB->succ_size() != 1) - continue; // Don't duplicate into a fall-through predecessor (at least for now). if (PredBB->isLayoutSuccessor(TailBB) && PredBB->canFallThrough()) continue; @@ -603,12 +603,11 @@ MachineBasicBlock *PrevBB = prior(MachineFunction::iterator(TailBB)); MachineBasicBlock *PriorTBB = 0, *PriorFBB = 0; SmallVector PriorCond; - bool PriorUnAnalyzable = - TII->AnalyzeBranch(*PrevBB, PriorTBB, PriorFBB, PriorCond, true); // This has to check PrevBB->succ_size() because EH edges are ignored by // AnalyzeBranch. - if (!PriorUnAnalyzable && PriorCond.empty() && !PriorTBB && - TailBB->pred_size() == 1 && PrevBB->succ_size() == 1 && + if (PrevBB->succ_size() == 1 && + !TII->AnalyzeBranch(*PrevBB, PriorTBB, PriorFBB, PriorCond, true) && + PriorCond.empty() && !PriorTBB && TailBB->pred_size() == 1 && !TailBB->hasAddressTaken()) { DEBUG(dbgs() << "\nMerging into block: " << *PrevBB << "From MBB: " << *TailBB); From eli.friedman at gmail.com Thu Jun 9 15:06:18 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Thu, 9 Jun 2011 15:06:18 -0700 Subject: [llvm-commits] [llvm] r132785 - in /llvm/trunk/test/FrontendC/ARM: dg.exp inline-asm-multichar.c In-Reply-To: <20110609171838.1540F2A6C12C@llvm.org> References: <20110609171838.1540F2A6C12C@llvm.org> Message-ID: On Thu, Jun 9, 2011 at 10:18 AM, Galina Kistanova wrote: > Author: gkistanova > Date: Thu Jun  9 12:18:37 2011 > New Revision: 132785 > > URL: http://llvm.org/viewvc/llvm-project?rev=132785&view=rev > Log: > Added dg.exp to run FrontendC ARM-dependent tests; updated inline-asm-multichar.c test per this change. > > Added: >    llvm/trunk/test/FrontendC/ARM/dg.exp > Modified: >    llvm/trunk/test/FrontendC/ARM/inline-asm-multichar.c This is breaking buildbots; see http://google1.osuosl.org:8011/builders/llvm-gcc-i386-linux-selfhost/builds/2801 . -Eli > Added: llvm/trunk/test/FrontendC/ARM/dg.exp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/ARM/dg.exp?rev=132785&view=auto > ============================================================================== > --- llvm/trunk/test/FrontendC/ARM/dg.exp (added) > +++ llvm/trunk/test/FrontendC/ARM/dg.exp Thu Jun  9 12:18:37 2011 > @@ -0,0 +1,5 @@ > +load_lib llvm.exp > + > +if { [llvm_supports_target ARM] AND [ llvm_gcc_supports c ] } { > +    RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp,s}]] > +} > > Modified: llvm/trunk/test/FrontendC/ARM/inline-asm-multichar.c > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/ARM/inline-asm-multichar.c?rev=132785&r1=132784&r2=132785&view=diff > ============================================================================== > --- llvm/trunk/test/FrontendC/ARM/inline-asm-multichar.c (original) > +++ llvm/trunk/test/FrontendC/ARM/inline-asm-multichar.c Thu Jun  9 12:18:37 2011 > @@ -1,11 +1,8 @@ >  // RUN: %llvmgcc -S -march=armv7a %s > > -// XFAIL: * > -// XTARGET: arm > - >  int t1() { >   static float k = 1.0f; > -CHECK: call void asm sideeffect "flds s15, $0 \0A", "*^Uv,~{s15}" > +// CHECK: call void asm sideeffect "flds s15, $0 \0A", "*^Uv,~{s15}" >   __asm__ volatile ("flds s15, %[k] \n" :: [k] "Uv,m" (k) : "s15"); >   return 0; >  } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From eli.friedman at gmail.com Thu Jun 9 15:14:44 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Thu, 09 Jun 2011 22:14:44 -0000 Subject: [llvm-commits] [llvm] r132809 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/X86/shift-pair.ll Message-ID: <20110609221444.567022A6C12C@llvm.org> Author: efriedma Date: Thu Jun 9 17:14:44 2011 New Revision: 132809 URL: http://llvm.org/viewvc/llvm-project?rev=132809&view=rev Log: Change this DAGCombine to build AND of SHR instead of SHR of AND; this matches the ordering we prefer in instcombine. Part of rdar://9562809. The potential DAGCombine which enforces this more generally messes up some other very fragile patterns, so I'm leaving that alone, at least for now. Added: llvm/trunk/test/CodeGen/X86/shift-pair.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=132809&r1=132808&r2=132809&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jun 9 17:14:44 2011 @@ -3092,26 +3092,27 @@ } } - // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or - // (srl (and x, (shl -1, c1)), (sub c1, c2)) + // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or + // (and (srl x, (sub c1, c2), MASK) if (N1C && N0.getOpcode() == ISD::SRL && N0.getOperand(1).getOpcode() == ISD::Constant) { uint64_t c1 = cast(N0.getOperand(1))->getZExtValue(); if (c1 < VT.getSizeInBits()) { uint64_t c2 = N1C->getZExtValue(); - SDValue HiBitsMask = - DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), - VT.getSizeInBits() - c1), - VT); - SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, - N0.getOperand(0), - HiBitsMask); - if (c2 > c1) - return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, - DAG.getConstant(c2-c1, N1.getValueType())); - else - return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, - DAG.getConstant(c1-c2, N1.getValueType())); + APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), + VT.getSizeInBits() - c1); + SDValue Shift; + if (c2 > c1) { + Mask = Mask.shl(c2-c1); + Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), + DAG.getConstant(c2-c1, N1.getValueType())); + } else { + Mask = Mask.lshr(c1-c2); + Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), + DAG.getConstant(c1-c2, N1.getValueType())); + } + return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift, + DAG.getConstant(Mask, VT)); } } // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) Added: llvm/trunk/test/CodeGen/X86/shift-pair.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shift-pair.ll?rev=132809&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/shift-pair.ll (added) +++ llvm/trunk/test/CodeGen/X86/shift-pair.ll Thu Jun 9 17:14:44 2011 @@ -0,0 +1,11 @@ +; RUN: llc < %s -march=x86-64 | FileCheck %s + +define i64 @test(i64 %A) { +; CHECK: @test +; CHECK: shrq $54 +; CHECK: andq $1020 +; CHECK: ret + %B = lshr i64 %A, 56 + %C = shl i64 %B, 2 + ret i64 %C +} From zwarich at apple.com Thu Jun 9 15:30:07 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Thu, 09 Jun 2011 22:30:07 -0000 Subject: [llvm-commits] [llvm] r132811 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/2011-06-09-TailCallByVal.ll Message-ID: <20110609223007.4B8F12A6C12C@llvm.org> Author: zwarich Date: Thu Jun 9 17:30:07 2011 New Revision: 132811 URL: http://llvm.org/viewvc/llvm-project?rev=132811&view=rev Log: A CCState was being created without setting whether it is in the Call or Prologue state, causing an assertion failure downstream. This fixes . This really seems like it should always be set at CCState creation time, so mistakes like this can never happen. I'll take a look at doing that. Added: llvm/trunk/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=132811&r1=132810&r2=132811&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Jun 9 17:30:07 2011 @@ -1672,6 +1672,7 @@ SmallVector ArgLocs; CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), getTargetMachine(), ArgLocs, *DAG.getContext()); + CCInfo.setCallOrPrologue(Call); CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC, false, isVarArg)); if (CCInfo.getNextStackOffset()) { Added: llvm/trunk/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll?rev=132811&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll (added) +++ llvm/trunk/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll Thu Jun 9 17:30:07 2011 @@ -0,0 +1,39 @@ +; RUN: llc < %s -relocation-model=pic -mcpu=cortex-a8 -arm-tail-calls=1 | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin10" + +%struct._RuneCharClass = type { [14 x i8], i32 } +%struct._RuneEntry = type { i32, i32, i32, i32* } +%struct._RuneLocale = type { [8 x i8], [32 x i8], i32 (i8*, i32, i8**)*, i32 (i32, i8*, i32, i8**)*, i32, [256 x i32], [256 x i32], [256 x i32], %struct._RuneRange, %struct._RuneRange, %struct._RuneRange, i8*, i32, i32, %struct._RuneCharClass* } +%struct._RuneRange = type { i32, %struct._RuneEntry* } +%struct.__collate_st_chain_pri = type { [10 x i32], [2 x i32] } +%struct.__collate_st_char_pri = type { [2 x i32] } +%struct.__collate_st_info = type { [2 x i8], i8, i8, [2 x i32], [2 x i32], i32, i32 } +%struct.__collate_st_large_char_pri = type { i32, %struct.__collate_st_char_pri } +%struct.__collate_st_subst = type { i32, [10 x i32] } +%struct.__xlocale_st_collate = type { i32, void (i8*)*, [32 x i8], %struct.__collate_st_info, [2 x %struct.__collate_st_subst*], %struct.__collate_st_chain_pri*, %struct.__collate_st_large_char_pri*, [256 x %struct.__collate_st_char_pri] } +%struct.__xlocale_st_messages = type { i32, void (i8*)*, i8*, %struct.lc_messages_T } +%struct.__xlocale_st_monetary = type { i32, void (i8*)*, i8*, %struct.lc_monetary_T } +%struct.__xlocale_st_numeric = type { i32, void (i8*)*, i8*, %struct.lc_numeric_T } +%struct.__xlocale_st_runelocale = type { i32, void (i8*)*, [32 x i8], i32, i32, i32 (i32*, i8*, i32, %union.__mbstate_t*, %struct._xlocale*)*, i32 (%union.__mbstate_t*, %struct._xlocale*)*, i32 (i32*, i8**, i32, i32, %union.__mbstate_t*, %struct._xlocale*)*, i32 (i8*, i32, %union.__mbstate_t*, %struct._xlocale*)*, i32 (i8*, i32**, i32, i32, %union.__mbstate_t*, %struct._xlocale*)*, i32, %struct._RuneLocale } +%struct.__xlocale_st_time = type { i32, void (i8*)*, i8*, %struct.lc_time_T } +%struct._xlocale = type { i32, void (i8*)*, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, i32, i64, i8, i8, i8, i8, i8, i8, i8, i8, i8, %struct.__xlocale_st_collate*, %struct.__xlocale_st_runelocale*, %struct.__xlocale_st_messages*, %struct.__xlocale_st_monetary*, %struct.__xlocale_st_numeric*, %struct._xlocale*, %struct.__xlocale_st_time*, %struct.lconv } +%struct.lc_messages_T = type { i8*, i8*, i8*, i8* } +%struct.lc_monetary_T = type { i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8* } +%struct.lc_numeric_T = type { i8*, i8*, i8* } +%struct.lc_time_T = type { [12 x i8*], [12 x i8*], [7 x i8*], [7 x i8*], i8*, i8*, i8*, i8*, i8*, i8*, [12 x i8*], i8*, i8* } +%struct.lconv = type { i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 } +%union.__mbstate_t = type { i64, [120 x i8] } + +@"\01_fnmatch.initial" = external constant %union.__mbstate_t, align 4 + +; CHECK: _fnmatch +; CHECK: blx _fnmatch1 + +define i32 @"\01_fnmatch"(i8* %pattern, i8* %string, i32 %flags) nounwind optsize { +entry: + %call4 = tail call i32 @fnmatch1(i8* %pattern, i8* %string, i8* %string, i32 %flags, %union.__mbstate_t* byval @"\01_fnmatch.initial", %union.__mbstate_t* byval @"\01_fnmatch.initial", %struct._xlocale* undef, i32 64) optsize + ret i32 %call4 +} + +declare i32 @fnmatch1(i8*, i8*, i8*, i32, %union.__mbstate_t* byval, %union.__mbstate_t* byval, %struct._xlocale*, i32) nounwind optsize From rafael.espindola at gmail.com Thu Jun 9 15:53:48 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 09 Jun 2011 22:53:48 -0000 Subject: [llvm-commits] [llvm] r132814 - /llvm/trunk/lib/CodeGen/TailDuplication.cpp Message-ID: <20110609225348.233B32A6C12C@llvm.org> Author: rafael Date: Thu Jun 9 17:53:47 2011 New Revision: 132814 URL: http://llvm.org/viewvc/llvm-project?rev=132814&view=rev Log: Also consider phi nodes when deciding if a register is live out. Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=132814&r1=132813&r2=132814&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original) +++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Thu Jun 9 17:53:47 2011 @@ -81,12 +81,14 @@ void ProcessPHI(MachineInstr *MI, MachineBasicBlock *TailBB, MachineBasicBlock *PredBB, DenseMap &LocalVRMap, - SmallVector, 4> &Copies); + SmallVector, 4> &Copies, + const DenseSet &UsedByPhi); void DuplicateInstruction(MachineInstr *MI, MachineBasicBlock *TailBB, MachineBasicBlock *PredBB, MachineFunction &MF, - DenseMap &LocalVRMap); + DenseMap &LocalVRMap, + const DenseSet &UsedByPhi); void UpdateSuccessorsPHIs(MachineBasicBlock *FromBB, bool isDead, SmallVector &TDBBs, SmallSetVector &Succs); @@ -293,6 +295,24 @@ return 0; } + +// Remember which registers are used by phis in this block. This is +// used to determine which registers are liveout while modifying the +// block (which is why we need to copy the information). +static void getRegsUsedByPHIs(const MachineBasicBlock &BB, + DenseSet *UsedByPhi) { + for(MachineBasicBlock::const_iterator I = BB.begin(), E = BB.end(); + I != E; ++I) { + const MachineInstr &MI = *I; + if (!MI.isPHI()) + break; + for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) { + unsigned SrcReg = MI.getOperand(i).getReg(); + UsedByPhi->insert(SrcReg); + } + } +} + /// AddSSAUpdateEntry - Add a definition and source virtual registers pair for /// SSA update. void TailDuplicatePass::AddSSAUpdateEntry(unsigned OrigReg, unsigned NewReg, @@ -315,7 +335,8 @@ MachineBasicBlock *TailBB, MachineBasicBlock *PredBB, DenseMap &LocalVRMap, - SmallVector, 4> &Copies) { + SmallVector, 4> &Copies, + const DenseSet &RegsUsedByPhi) { unsigned DefReg = MI->getOperand(0).getReg(); unsigned SrcOpIdx = getPHISrcRegOpIdx(MI, PredBB); assert(SrcOpIdx && "Unable to find matching PHI source?"); @@ -327,7 +348,7 @@ // available value liveout of the block. unsigned NewDef = MRI->createVirtualRegister(RC); Copies.push_back(std::make_pair(NewDef, SrcReg)); - if (isDefLiveOut(DefReg, TailBB, MRI)) + if (isDefLiveOut(DefReg, TailBB, MRI) || RegsUsedByPhi.count(DefReg)) AddSSAUpdateEntry(DefReg, NewDef, PredBB); // Remove PredBB from the PHI node. @@ -343,7 +364,8 @@ MachineBasicBlock *TailBB, MachineBasicBlock *PredBB, MachineFunction &MF, - DenseMap &LocalVRMap) { + DenseMap &LocalVRMap, + const DenseSet &UsedByPhi) { MachineInstr *NewMI = TII->duplicate(MI, MF); for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) { MachineOperand &MO = NewMI->getOperand(i); @@ -357,7 +379,7 @@ unsigned NewReg = MRI->createVirtualRegister(RC); MO.setReg(NewReg); LocalVRMap.insert(std::make_pair(Reg, NewReg)); - if (isDefLiveOut(Reg, TailBB, MRI)) + if (isDefLiveOut(Reg, TailBB, MRI) || UsedByPhi.count(Reg)) AddSSAUpdateEntry(Reg, NewReg, PredBB); } else { DenseMap::iterator VI = LocalVRMap.find(Reg); @@ -531,6 +553,8 @@ bool Changed = false; SmallSetVector Preds(TailBB->pred_begin(), TailBB->pred_end()); + DenseSet UsedByPhi; + getRegsUsedByPHIs(*TailBB, &UsedByPhi); for (SmallSetVector::iterator PI = Preds.begin(), PE = Preds.end(); PI != PE; ++PI) { MachineBasicBlock *PredBB = *PI; @@ -570,11 +594,11 @@ if (MI->isPHI()) { // Replace the uses of the def of the PHI with the register coming // from PredBB. - ProcessPHI(MI, TailBB, PredBB, LocalVRMap, CopyInfos); + ProcessPHI(MI, TailBB, PredBB, LocalVRMap, CopyInfos, UsedByPhi); } else { // Replace def of virtual registers with new registers, and update // uses with PHI source register or the new registers. - DuplicateInstruction(MI, TailBB, PredBB, MF, LocalVRMap); + DuplicateInstruction(MI, TailBB, PredBB, MF, LocalVRMap, UsedByPhi); } } MachineBasicBlock::iterator Loc = PredBB->getFirstTerminator(); @@ -620,7 +644,7 @@ // Replace the uses of the def of the PHI with the register coming // from PredBB. MachineInstr *MI = &*I++; - ProcessPHI(MI, TailBB, PrevBB, LocalVRMap, CopyInfos); + ProcessPHI(MI, TailBB, PrevBB, LocalVRMap, CopyInfos, UsedByPhi); if (MI->getParent()) MI->eraseFromParent(); } @@ -630,7 +654,7 @@ // Replace def of virtual registers with new registers, and update // uses with PHI source register or the new registers. MachineInstr *MI = &*I++; - DuplicateInstruction(MI, TailBB, PrevBB, MF, LocalVRMap); + DuplicateInstruction(MI, TailBB, PrevBB, MF, LocalVRMap, UsedByPhi); MI->eraseFromParent(); } MachineBasicBlock::iterator Loc = PrevBB->getFirstTerminator(); From echristo at apple.com Thu Jun 9 15:59:30 2011 From: echristo at apple.com (Eric Christopher) Date: Thu, 09 Jun 2011 15:59:30 -0700 Subject: [llvm-commits] [llvm] r132676 - in /llvm/trunk: lib/CodeGen/SelectionDAG/FastISel.cpp test/CodeGen/X86/fast-isel-agg-constant.ll In-Reply-To: <61506575-176C-490D-A068-04F00EBD450C@apple.com> References: <20110606153822.GA6591@freebsd.org> <20110609080819.GA4929@freebsd.org> <969FF868-AE98-4F22-AABD-D59D3C483793@apple.com> <20110609194839.GA45739@freebsd.org> <85D18316-EFC8-4370-9363-7B0961DE4420@apple.com> <9BC5000C-E2A5-4E77-B163-33773F7F5D47@apple.com> <61506575-176C-490D-A068-04F00EBD450C@apple.com> Message-ID: <3F24BDB3-9AE4-455B-BAFB-B0E8B7EF7CCB@apple.com> On Jun 9, 2011, at 2:03 PM, Jim Grosbach wrote: > > On Jun 9, 2011, at 1:59 PM, Eric Christopher wrote: > >>>> >>>> The thing is that in MCExpr there's absolutely nothing related to triples etc. >>>> It's just a pure container for an expression. Nothing from the outside world >>>> is there :) >>>> >>>> Thats why I introduced the two new variant kinds, to distinguish the two >>>> dialects. >>> >>> Yeah. It's a bit of an ugly solution, but it's pretty much necessary for now. IIRC, there are precedent examples of the same thing in there. We really need a target-hook that has access to the triple level information for this sort of thing, but there's no such beast right now. >> >> Which is why I was mentioning using the subtarget. While MCExpr there isn't anything related to targets - at some point we need to know the subtarget to know how to emit relocation/expression information for assembly. There's absolutely no reason why we need two/multiple variants for each way that we'd like to print out a relocation/expression. > > The subtarget is part of the codegen layer. It's not available to MC*. > But it should be available to the printers and output. That's what I'm saying :) > I completely agree there shouldn't need to be multiple variants. MC does not currently have any other way to express this, however. > *points at backend* Hey, it knows ;) -eric From echristo at apple.com Thu Jun 9 16:00:46 2011 From: echristo at apple.com (Eric Christopher) Date: Thu, 09 Jun 2011 16:00:46 -0700 Subject: [llvm-commits] [llvm] r132676 - in /llvm/trunk: lib/CodeGen/SelectionDAG/FastISel.cpp test/CodeGen/X86/fast-isel-agg-constant.ll In-Reply-To: <61506575-176C-490D-A068-04F00EBD450C@apple.com> References: <20110606153822.GA6591@freebsd.org> <20110609080819.GA4929@freebsd.org> <969FF868-AE98-4F22-AABD-D59D3C483793@apple.com> <20110609194839.GA45739@freebsd.org> <85D18316-EFC8-4370-9363-7B0961DE4420@apple.com> <9BC5000C-E2A5-4E77-B163-33773F7F5D47@apple.com> <61506575-176C-490D-A068-04F00EBD450C@apple.com> Message-ID: <6B1355FD-BDA4-46FE-BA91-021BE02F0D40@apple.com> On Jun 9, 2011, at 2:03 PM, Jim Grosbach wrote: > > On Jun 9, 2011, at 1:59 PM, Eric Christopher wrote: > >>>> >>>> The thing is that in MCExpr there's absolutely nothing related to triples etc. >>>> It's just a pure container for an expression. Nothing from the outside world >>>> is there :) >>>> >>>> Thats why I introduced the two new variant kinds, to distinguish the two >>>> dialects. >>> >>> Yeah. It's a bit of an ugly solution, but it's pretty much necessary for now. IIRC, there are precedent examples of the same thing in there. We really need a target-hook that has access to the triple level information for this sort of thing, but there's no such beast right now. >> >> Which is why I was mentioning using the subtarget. While MCExpr there isn't anything related to targets - at some point we need to know the subtarget to know how to emit relocation/expression information for assembly. There's absolutely no reason why we need two/multiple variants for each way that we'd like to print out a relocation/expression. > > The subtarget is part of the codegen layer. It's not available to MC*. > > I completely agree there shouldn't need to be multiple variants. MC does not currently have any other way to express this, however. MCAsmInfo etc. The same way we do .long etc. :) -eric From eli.friedman at gmail.com Thu Jun 9 16:01:20 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Thu, 9 Jun 2011 16:01:20 -0700 Subject: [llvm-commits] [llvm] r132777 - in /llvm/trunk: lib/Target/Mips/MipsAsmPrinter.cpp lib/Target/Mips/MipsISelDAGToDAG.cpp lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsISelLowering.h lib/Target/Mips/MipsInstrInfo.td lib/Target/Mips/MipsM Message-ID: On Thu, Jun 9, 2011 at 9:03 AM, Eric Christopher wrote: > Author: echristo > Date: Thu Jun  9 11:03:19 2011 > New Revision: 132777 > > URL: http://llvm.org/viewvc/llvm-project?rev=132777&view=rev > Log: > Speculatively revert 132758 and 132768 to try to fix the Windows buildbots. It didn't work. :( I have no idea what else to try. -Eli > Removed: >    llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll > Modified: >    llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp >    llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp >    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp >    llvm/trunk/lib/Target/Mips/MipsISelLowering.h >    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td >    llvm/trunk/lib/Target/Mips/MipsMachineFunction.h >    llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp >    llvm/trunk/test/CodeGen/Mips/alloca.ll > > Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=132777&r1=132776&r2=132777&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original) > +++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Thu Jun  9 11:03:19 2011 > @@ -56,9 +56,6 @@ >     bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, >                          unsigned AsmVariant, const char *ExtraCode, >                          raw_ostream &O); > -    bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, > -                               unsigned AsmVariant, const char *ExtraCode, > -                               raw_ostream &O); >     void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O); >     void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O); >     void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O, > @@ -307,19 +304,6 @@ >   return false; >  } > > -bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, > -                                           unsigned OpNum, unsigned AsmVariant, > -                                           const char *ExtraCode, > -                                           raw_ostream &O) { > -  if (ExtraCode && ExtraCode[0]) > -     return true; // Unknown modifier. > - > -  const MachineOperand &MO = MI->getOperand(OpNum); > -  assert(MO.isReg() && "unexpected inline asm memory operand"); > -  O << "0($" << MipsAsmPrinter::getRegisterName(MO.getReg()) << ")"; > -  return false; > -} > - >  void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum, >                                   raw_ostream &O) { >   const MachineOperand &MO = MI->getOperand(opNum); > > Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=132777&r1=132776&r2=132777&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original) > +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Thu Jun  9 11:03:19 2011 > @@ -94,10 +94,6 @@ >   inline SDValue getI32Imm(unsigned Imm) { >     return CurDAG->getTargetConstant(Imm, MVT::i32); >   } > - > -  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, > -                                            char ConstraintCode, > -                                            std::vector &OutOps); >  }; > >  } > @@ -466,14 +462,6 @@ >   return ResNode; >  } > > -bool MipsDAGToDAGISel:: > -SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, > -                             std::vector &OutOps) { > -  assert(ConstraintCode == 'm' && "unexpected asm memory constraint"); > -  OutOps.push_back(Op); > -  return false; > -} > - >  /// createMipsISelDag - This pass converts a legalized DAG into a >  /// MIPS-specific DAG, ready for instruction scheduling. >  FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) { > > Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=132777&r1=132776&r2=132777&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Thu Jun  9 11:03:19 2011 > @@ -59,7 +59,6 @@ >   case MipsISD::BuildPairF64:      return "MipsISD::BuildPairF64"; >   case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; >   case MipsISD::WrapperPIC:        return "MipsISD::WrapperPIC"; > -  case MipsISD::DynAlloc:          return "MipsISD::DynAlloc"; >   default:                         return NULL; >   } >  } > @@ -1190,9 +1189,6 @@ >  SDValue MipsTargetLowering:: >  LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const >  { > -  MachineFunction &MF = DAG.getMachineFunction(); > -  MipsFunctionInfo *MipsFI = MF.getInfo(); > - >   unsigned StackAlignment = >     getTargetMachine().getFrameLowering()->getStackAlignment(); >   assert(StackAlignment >= > @@ -1215,14 +1211,24 @@ >   // must be placed in the stack pointer register. >   Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub, >                            SDValue()); > +  // Retrieve updated $sp. There is a glue input to prevent instructions that > +  // clobber $sp from being inserted between copytoreg and copyfromreg. > +  SDValue NewSP = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32, > +                                     Chain.getValue(1)); > + > +  // The stack space reserved by alloca is located right above the argument > +  // area. It is aligned on a boundary that is a multiple of StackAlignment. > +  MachineFunction &MF = DAG.getMachineFunction(); > +  MipsFunctionInfo *MipsFI = MF.getInfo(); > +  unsigned SPOffset = (MipsFI->getMaxCallFrameSize() + StackAlignment - 1) / > +                      StackAlignment * StackAlignment; > +  SDValue AllocPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP, > +                                 DAG.getConstant(SPOffset, MVT::i32)); > >   // This node always has two return values: a new stack pointer >   // value and a chain > -  SDVTList VTLs = DAG.getVTList(MVT::i32, MVT::Other); > -  SDValue Ptr = DAG.getFrameIndex(MipsFI->getDynAllocFI(), getPointerTy()); > -  SDValue Ops[] = { Chain, Ptr, Chain.getValue(1) }; > - > -  return DAG.getNode(MipsISD::DynAlloc, dl, VTLs, Ops, 3); > +  SDValue Ops[2] = { AllocPtr, NewSP.getValue(1) }; > +  return DAG.getMergeValues(Ops, 2, dl); >  } > >  SDValue MipsTargetLowering:: > @@ -1764,10 +1770,6 @@ >   if (IsPIC && !MipsFI->getGPFI()) >     MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true)); > > -  // Get the frame index of the stack frame object that points to the location > -  // of dynamically allocated area on the stack. > -  int DynAllocFI = MipsFI->getDynAllocFI(); > - >   // Update size of the maximum argument space. >   // For O32, a minimum of four words (16 bytes) of argument space is >   // allocated. > @@ -1779,17 +1781,14 @@ >   if (MaxCallFrameSize < NextStackOffset) { >     MipsFI->setMaxCallFrameSize(NextStackOffset); > > -    // Set the offsets relative to $sp of the $gp restore slot and dynamically > -    // allocated stack space. These offsets must be aligned to a boundary > -    // determined by the stack alignment of the ABI. > -    unsigned StackAlignment = TFL->getStackAlignment(); > -    NextStackOffset = (NextStackOffset + StackAlignment - 1) / > -                      StackAlignment * StackAlignment; > - > -    if (IsPIC) > -      MFI->setObjectOffset(MipsFI->getGPFI(), NextStackOffset); > - > -    MFI->setObjectOffset(DynAllocFI, NextStackOffset); > +    if (IsPIC) { > +      // $gp restore slot must be aligned. > +      unsigned StackAlignment = TFL->getStackAlignment(); > +      NextStackOffset = (NextStackOffset + StackAlignment - 1) / > +                        StackAlignment * StackAlignment; > +      int GPFI = MipsFI->getGPFI(); > +      MFI->setObjectOffset(GPFI, NextStackOffset); > +    } >   } > >   // With EABI is it possible to have 16 args on registers. > > Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=132777&r1=132776&r2=132777&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original) > +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Thu Jun  9 11:03:19 2011 > @@ -79,9 +79,7 @@ >       BuildPairF64, >       ExtractElementF64, > > -      WrapperPIC, > - > -      DynAlloc > +      WrapperPIC >     }; >   } > > > Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=132777&r1=132776&r2=132777&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) > +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Thu Jun  9 11:03:19 2011 > @@ -39,9 +39,6 @@ > >  def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; > > -def SDT_MipsDynAlloc    : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, > -                                               SDTCisVT<1, iPTR>]>; > - >  // Call >  def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, >                          [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, > @@ -102,10 +99,6 @@ > >  def MipsWrapperPIC    : SDNode<"MipsISD::WrapperPIC",  SDTIntUnaryOp>; > > -// Pointer to dynamically allocated stack area. > -def MipsDynAlloc  : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc, > -                           [SDNPHasChain, SDNPInGlue]>; > - >  //===----------------------------------------------------------------------===// >  // Mips Instruction Predicate Definitions. >  //===----------------------------------------------------------------------===// > @@ -682,12 +675,6 @@ >  // can be matched. It's similar to Sparc LEA_ADDRi >  def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">; > > -// DynAlloc node points to dynamically allocated stack space. > -// $sp is added to the list of implicitly used registers to prevent dead code > -// elimination from removing instructions that modify $sp. > -let Uses = [SP] in > -def DynAlloc : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">; > - >  // MADD*/MSUB* >  def MADD  : MArithR<0, "madd", MipsMAdd, 1>; >  def MADDU : MArithR<1, "maddu", MipsMAddu, 1>; > @@ -865,9 +852,6 @@ >  def : Pat<(setuge CPURegs:$lhs, immSExt16:$rhs), >           (XORi (SLTiu CPURegs:$lhs, immSExt16:$rhs), 1)>; > > -// select MipsDynAlloc > -def : Pat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>; > - >  //===----------------------------------------------------------------------===// >  // Floating Point Support >  //===----------------------------------------------------------------------===// > > Modified: llvm/trunk/lib/Target/Mips/MipsMachineFunction.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMachineFunction.h?rev=132777&r1=132776&r2=132777&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Mips/MipsMachineFunction.h (original) > +++ llvm/trunk/lib/Target/Mips/MipsMachineFunction.h Thu Jun  9 11:03:19 2011 > @@ -27,7 +27,6 @@ >  class MipsFunctionInfo : public MachineFunctionInfo { > >  private: > -  MachineFunction& MF; >   /// SRetReturnReg - Some subtargets require that sret lowering includes >   /// returning the value of the returned struct in a register. This field >   /// holds the virtual register into which the sret argument is passed. > @@ -48,7 +47,6 @@ >   //                LowerCall except for the frame object for restoring $gp. >   std::pair InArgFIRange, OutArgFIRange; >   int GPFI; // Index of the frame object for restoring $gp > -  mutable int DynAllocFI; // Frame index of dynamically allocated stack area. >   unsigned MaxCallFrameSize; > >   /// AtomicFrameIndex - To implement atomic.swap and atomic.cmp.swap > @@ -57,10 +55,10 @@ >   int AtomicFrameIndex; >  public: >   MipsFunctionInfo(MachineFunction& MF) > -  : MF(MF), SRetReturnReg(0), GlobalBaseReg(0), > +  : SRetReturnReg(0), GlobalBaseReg(0), >     VarArgsFrameIndex(0), InArgFIRange(std::make_pair(-1, 0)), > -    OutArgFIRange(std::make_pair(-1, 0)), GPFI(0), DynAllocFI(0), > -    MaxCallFrameSize(0), AtomicFrameIndex(-1) > +    OutArgFIRange(std::make_pair(-1, 0)), GPFI(0), MaxCallFrameSize(0), > +    AtomicFrameIndex(-1) >   {} > >   bool isInArgFI(int FI) const { > @@ -83,16 +81,6 @@ >   bool needGPSaveRestore() const { return getGPFI(); } >   bool isGPFI(int FI) const { return GPFI && GPFI == FI; } > > -  // The first call to this function creates a frame object for dynamically > -  // allocated stack area. > -  int getDynAllocFI() const { > -    if (!DynAllocFI) > -      DynAllocFI = MF.getFrameInfo()->CreateFixedObject(4, 0, true); > - > -    return DynAllocFI; > -  } > -  bool isDynAllocFI(int FI) const { return DynAllocFI && DynAllocFI == FI; } > - >   unsigned getSRetReturnReg() const { return SRetReturnReg; } >   void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } > > > Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=132777&r1=132776&r2=132777&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original) > +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Thu Jun  9 11:03:19 2011 > @@ -177,14 +177,12 @@ >   int Offset; > >   // Calculate final offset. > -  // - There is no need to change the offset if the frame object is one of the > -  //   following: an outgoing argument, pointer to a dynamically allocated > -  //   stack space or a $gp restore location, > +  // - There is no need to change the offset if the frame object is an outgoing > +  //   argument or a $gp restore location, >   // - If the frame object is any of the following, its offset must be adjusted >   //   by adding the size of the stack: >   //   incoming argument, callee-saved register location or local variable. > -  if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isGPFI(FrameIndex) || > -      MipsFI->isDynAllocFI(FrameIndex)) > +  if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isGPFI(FrameIndex)) >     Offset = spOffset; >   else >     Offset = spOffset + stackSize; > @@ -213,7 +211,7 @@ >   //  3. Locations for callee-saved registers. >   // Everything else is referenced relative to whatever register >   // getFrameRegister() returns. > -  if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isDynAllocFI(FrameIndex) || > +  if (MipsFI->isOutArgFI(FrameIndex) || >       (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI)) >     FrameReg = Mips::SP; >   else > > Modified: llvm/trunk/test/CodeGen/Mips/alloca.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/alloca.ll?rev=132777&r1=132776&r2=132777&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/Mips/alloca.ll (original) > +++ llvm/trunk/test/CodeGen/Mips/alloca.ll Thu Jun  9 11:03:19 2011 > @@ -4,15 +4,15 @@ >  entry: >  ; CHECK: subu  $[[T0:[0-9]+]], $sp, $[[SZ:[0-9]+]] >  ; CHECK: addu  $sp, $zero, $[[T0]] > -; CHECK: addiu $[[T1:[0-9]+]], $sp, [[OFF:[0-9]+]] > -; CHECK: subu  $[[T2:[0-9]+]], $sp, $[[SZ]] > -; CHECK: addu  $sp, $zero, $[[T2]] > -; CHECK: addiu $[[T3:[0-9]+]], $sp, [[OFF]] > +; CHECK: addu  $[[SP1:[0-9]+]], $zero, $sp > +; CHECK: subu  $[[T1:[0-9]+]], $sp, $[[SZ]] > +; CHECK: addu  $sp, $zero, $[[T1]] > +; CHECK: addu  $[[SP2:[0-9]+]], $zero, $sp >  ; CHECK: lw  $25, %call16(foo)($gp) > -; CHECK: addu $4, $zero, $[[T1]] > +; CHECK: addiu $4, $[[SP1]], 24 >  ; CHECK: jalr  $25 >  ; CHECK: lw  $25, %call16(foo)($gp) > -; CHECK: addu $4, $zero, $[[T3]] > +; CHECK: addiu $4, $[[SP2]], 24 >  ; CHECK: jalr  $25 >   %tmp1 = alloca i8, i32 %size, align 4 >   %add.ptr = getelementptr inbounds i8* %tmp1, i32 5 > @@ -29,72 +29,3 @@ > >  declare i32 @foo(i8*) > > - at .str = private unnamed_addr constant [22 x i8] c"%d %d %d %d %d %d %d\0A\00", align 1 > - > -define i32 @alloca2(i32 %size) nounwind { > -entry: > -; dynamic allocated stack area and $gp restore slot have the same offsets > -; relative to $sp. > -; > -; CHECK: alloca2 > -; CHECK: .cprestore [[OFF:[0-9]+]] > -; CHECK: subu  $[[T0:[0-9]+]], $sp, $[[SZ:[0-9]+]] > -; CHECK: addu  $sp, $zero, $[[T0]] > -; CHECK: addiu $[[T1:[0-9]+]], $sp, [[OFF]] > - > -  %tmp1 = alloca i8, i32 %size, align 4 > -  %0 = bitcast i8* %tmp1 to i32* > -  %cmp = icmp sgt i32 %size, 10 > -  br i1 %cmp, label %if.then, label %if.else > - > -if.then:                                          ; preds = %entry > -; CHECK: addiu $4, $[[T1]], 40 > - > -  %add.ptr = getelementptr inbounds i8* %tmp1, i32 40 > -  %1 = bitcast i8* %add.ptr to i32* > -  call void @foo3(i32* %1) nounwind > -  %arrayidx15.pre = getelementptr inbounds i8* %tmp1, i32 12 > -  %.pre = bitcast i8* %arrayidx15.pre to i32* > -  br label %if.end > - > -if.else:                                          ; preds = %entry > -; CHECK: addiu $4, $[[T1]], 12 > - > -  %add.ptr5 = getelementptr inbounds i8* %tmp1, i32 12 > -  %2 = bitcast i8* %add.ptr5 to i32* > -  call void @foo3(i32* %2) nounwind > -  br label %if.end > - > -if.end:                                           ; preds = %if.else, %if.then > -; CHECK: lw  $5, 0($[[T1]]) > -; CHECK: lw  $25, %call16(printf) > - > -  %.pre-phi = phi i32* [ %2, %if.else ], [ %.pre, %if.then ] > -  %tmp7 = load i32* %0, align 4, !tbaa !0 > -  %arrayidx9 = getelementptr inbounds i8* %tmp1, i32 4 > -  %3 = bitcast i8* %arrayidx9 to i32* > -  %tmp10 = load i32* %3, align 4, !tbaa !0 > -  %arrayidx12 = getelementptr inbounds i8* %tmp1, i32 8 > -  %4 = bitcast i8* %arrayidx12 to i32* > -  %tmp13 = load i32* %4, align 4, !tbaa !0 > -  %tmp16 = load i32* %.pre-phi, align 4, !tbaa !0 > -  %arrayidx18 = getelementptr inbounds i8* %tmp1, i32 16 > -  %5 = bitcast i8* %arrayidx18 to i32* > -  %tmp19 = load i32* %5, align 4, !tbaa !0 > -  %arrayidx21 = getelementptr inbounds i8* %tmp1, i32 20 > -  %6 = bitcast i8* %arrayidx21 to i32* > -  %tmp22 = load i32* %6, align 4, !tbaa !0 > -  %arrayidx24 = getelementptr inbounds i8* %tmp1, i32 24 > -  %7 = bitcast i8* %arrayidx24 to i32* > -  %tmp25 = load i32* %7, align 4, !tbaa !0 > -  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([22 x i8]* @.str, i32 0, i32 0), i32 %tmp7, i32 %tmp10, i32 %tmp13, i32 %tmp16, i32 %tmp19, i32 %tmp22, i32 %tmp25) nounwind > -  ret i32 0 > -} > - > -declare void @foo3(i32*) > - > -declare i32 @printf(i8* nocapture, ...) nounwind > - > -!0 = metadata !{metadata !"int", metadata !1} > -!1 = metadata !{metadata !"omnipotent char", metadata !2} > -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} > > Removed: llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll?rev=132776&view=auto > ============================================================================== > --- llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll (original) > +++ llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll (removed) > @@ -1,23 +0,0 @@ > -; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s > - > - at g1 = external global i32 > - > -define i32 @f1(i32 %x) nounwind { > -entry: > -; CHECK: addiu $[[T0:[0-9]+]], $sp > -; CHECK: #APP > -; CHECK: sw $4, 0($[[T0]]) > -; CHECK: #NO_APP > -; CHECK: lw  $[[T1:[0-9]+]], %got(g1)($gp) > -; CHECK: #APP > -; CHECK: lw $[[T3:[0-9]+]], 0($[[T0]]) > -; CHECK: #NO_APP > -; CHECK: sw  $[[T3]], 0($[[T1]]) > - > -  %l1 = alloca i32, align 4 > -  call void asm "sw $1, $0", "=*m,r"(i32* %l1, i32 %x) nounwind > -  %0 = call i32 asm "lw $0, $1", "=r,*m"(i32* %l1) nounwind > -  store i32 %0, i32* @g1, align 4 > -  ret i32 %0 > -} > - > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From echristo at apple.com Thu Jun 9 16:02:32 2011 From: echristo at apple.com (Eric Christopher) Date: Thu, 09 Jun 2011 16:02:32 -0700 Subject: [llvm-commits] [llvm] r132777 - in /llvm/trunk: lib/Target/Mips/MipsAsmPrinter.cpp lib/Target/Mips/MipsISelDAGToDAG.cpp lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsISelLowering.h lib/Target/Mips/MipsInstrInfo.td lib/Target/Mips/MipsM In-Reply-To: References: Message-ID: On Jun 9, 2011, at 4:01 PM, Eli Friedman wrote: > On Thu, Jun 9, 2011 at 9:03 AM, Eric Christopher wrote: >> Author: echristo >> Date: Thu Jun 9 11:03:19 2011 >> New Revision: 132777 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=132777&view=rev >> Log: >> Speculatively revert 132758 and 132768 to try to fix the Windows buildbots. > > It didn't work. :( I have no idea what else to try. Me either. Reverting mine didn't work either. -eric From zwarich at apple.com Thu Jun 9 16:05:14 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Thu, 09 Jun 2011 16:05:14 -0700 Subject: [llvm-commits] [llvm] r132814 - /llvm/trunk/lib/CodeGen/TailDuplication.cpp In-Reply-To: <20110609225348.233B32A6C12C@llvm.org> References: <20110609225348.233B32A6C12C@llvm.org> Message-ID: <07B5C12A-B18D-41AD-BB15-66397CD7EFA3@apple.com> Was this motivated by a test case? Cameron On Jun 9, 2011, at 3:53 PM, Rafael Espindola wrote: > Author: rafael > Date: Thu Jun 9 17:53:47 2011 > New Revision: 132814 > > URL: http://llvm.org/viewvc/llvm-project?rev=132814&view=rev > Log: > Also consider phi nodes when deciding if a register is live out. > > Modified: > llvm/trunk/lib/CodeGen/TailDuplication.cpp > > Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=132814&r1=132813&r2=132814&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original) > +++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Thu Jun 9 17:53:47 2011 > @@ -81,12 +81,14 @@ > void ProcessPHI(MachineInstr *MI, MachineBasicBlock *TailBB, > MachineBasicBlock *PredBB, > DenseMap &LocalVRMap, > - SmallVector, 4> &Copies); > + SmallVector, 4> &Copies, > + const DenseSet &UsedByPhi); > void DuplicateInstruction(MachineInstr *MI, > MachineBasicBlock *TailBB, > MachineBasicBlock *PredBB, > MachineFunction &MF, > - DenseMap &LocalVRMap); > + DenseMap &LocalVRMap, > + const DenseSet &UsedByPhi); > void UpdateSuccessorsPHIs(MachineBasicBlock *FromBB, bool isDead, > SmallVector &TDBBs, > SmallSetVector &Succs); > @@ -293,6 +295,24 @@ > return 0; > } > > + > +// Remember which registers are used by phis in this block. This is > +// used to determine which registers are liveout while modifying the > +// block (which is why we need to copy the information). > +static void getRegsUsedByPHIs(const MachineBasicBlock &BB, > + DenseSet *UsedByPhi) { > + for(MachineBasicBlock::const_iterator I = BB.begin(), E = BB.end(); > + I != E; ++I) { > + const MachineInstr &MI = *I; > + if (!MI.isPHI()) > + break; > + for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) { > + unsigned SrcReg = MI.getOperand(i).getReg(); > + UsedByPhi->insert(SrcReg); > + } > + } > +} > + > /// AddSSAUpdateEntry - Add a definition and source virtual registers pair for > /// SSA update. > void TailDuplicatePass::AddSSAUpdateEntry(unsigned OrigReg, unsigned NewReg, > @@ -315,7 +335,8 @@ > MachineBasicBlock *TailBB, > MachineBasicBlock *PredBB, > DenseMap &LocalVRMap, > - SmallVector, 4> &Copies) { > + SmallVector, 4> &Copies, > + const DenseSet &RegsUsedByPhi) { > unsigned DefReg = MI->getOperand(0).getReg(); > unsigned SrcOpIdx = getPHISrcRegOpIdx(MI, PredBB); > assert(SrcOpIdx && "Unable to find matching PHI source?"); > @@ -327,7 +348,7 @@ > // available value liveout of the block. > unsigned NewDef = MRI->createVirtualRegister(RC); > Copies.push_back(std::make_pair(NewDef, SrcReg)); > - if (isDefLiveOut(DefReg, TailBB, MRI)) > + if (isDefLiveOut(DefReg, TailBB, MRI) || RegsUsedByPhi.count(DefReg)) > AddSSAUpdateEntry(DefReg, NewDef, PredBB); > > // Remove PredBB from the PHI node. > @@ -343,7 +364,8 @@ > MachineBasicBlock *TailBB, > MachineBasicBlock *PredBB, > MachineFunction &MF, > - DenseMap &LocalVRMap) { > + DenseMap &LocalVRMap, > + const DenseSet &UsedByPhi) { > MachineInstr *NewMI = TII->duplicate(MI, MF); > for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) { > MachineOperand &MO = NewMI->getOperand(i); > @@ -357,7 +379,7 @@ > unsigned NewReg = MRI->createVirtualRegister(RC); > MO.setReg(NewReg); > LocalVRMap.insert(std::make_pair(Reg, NewReg)); > - if (isDefLiveOut(Reg, TailBB, MRI)) > + if (isDefLiveOut(Reg, TailBB, MRI) || UsedByPhi.count(Reg)) > AddSSAUpdateEntry(Reg, NewReg, PredBB); > } else { > DenseMap::iterator VI = LocalVRMap.find(Reg); > @@ -531,6 +553,8 @@ > bool Changed = false; > SmallSetVector Preds(TailBB->pred_begin(), > TailBB->pred_end()); > + DenseSet UsedByPhi; > + getRegsUsedByPHIs(*TailBB, &UsedByPhi); > for (SmallSetVector::iterator PI = Preds.begin(), > PE = Preds.end(); PI != PE; ++PI) { > MachineBasicBlock *PredBB = *PI; > @@ -570,11 +594,11 @@ > if (MI->isPHI()) { > // Replace the uses of the def of the PHI with the register coming > // from PredBB. > - ProcessPHI(MI, TailBB, PredBB, LocalVRMap, CopyInfos); > + ProcessPHI(MI, TailBB, PredBB, LocalVRMap, CopyInfos, UsedByPhi); > } else { > // Replace def of virtual registers with new registers, and update > // uses with PHI source register or the new registers. > - DuplicateInstruction(MI, TailBB, PredBB, MF, LocalVRMap); > + DuplicateInstruction(MI, TailBB, PredBB, MF, LocalVRMap, UsedByPhi); > } > } > MachineBasicBlock::iterator Loc = PredBB->getFirstTerminator(); > @@ -620,7 +644,7 @@ > // Replace the uses of the def of the PHI with the register coming > // from PredBB. > MachineInstr *MI = &*I++; > - ProcessPHI(MI, TailBB, PrevBB, LocalVRMap, CopyInfos); > + ProcessPHI(MI, TailBB, PrevBB, LocalVRMap, CopyInfos, UsedByPhi); > if (MI->getParent()) > MI->eraseFromParent(); > } > @@ -630,7 +654,7 @@ > // Replace def of virtual registers with new registers, and update > // uses with PHI source register or the new registers. > MachineInstr *MI = &*I++; > - DuplicateInstruction(MI, TailBB, PrevBB, MF, LocalVRMap); > + DuplicateInstruction(MI, TailBB, PrevBB, MF, LocalVRMap, UsedByPhi); > MI->eraseFromParent(); > } > MachineBasicBlock::iterator Loc = PrevBB->getFirstTerminator(); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From eli.friedman at gmail.com Thu Jun 9 16:02:19 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Thu, 09 Jun 2011 23:02:19 -0000 Subject: [llvm-commits] [llvm] r132815 - /llvm/trunk/lib/Target/X86/README-X86-64.txt Message-ID: <20110609230219.D77AE2A6C12F@llvm.org> Author: efriedma Date: Thu Jun 9 18:02:19 2011 New Revision: 132815 URL: http://llvm.org/viewvc/llvm-project?rev=132815&view=rev Log: Chris fixed this README a while back by changing how clang generates code for structs like the given struct. Modified: llvm/trunk/lib/Target/X86/README-X86-64.txt Modified: llvm/trunk/lib/Target/X86/README-X86-64.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/README-X86-64.txt?rev=132815&r1=132814&r2=132815&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/README-X86-64.txt (original) +++ llvm/trunk/lib/Target/X86/README-X86-64.txt Thu Jun 9 18:02:19 2011 @@ -124,51 +124,6 @@ //===---------------------------------------------------------------------===// -Take the following C code -(from http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43640): - -struct u1 -{ - float x; - float y; -}; - -float foo(struct u1 u) -{ - return u.x + u.y; -} - -Optimizes to the following IR: -define float @foo(double %u.0) nounwind readnone { -entry: - %tmp8 = bitcast double %u.0 to i64 ; [#uses=2] - %tmp6 = trunc i64 %tmp8 to i32 ; [#uses=1] - %tmp7 = bitcast i32 %tmp6 to float ; [#uses=1] - %tmp2 = lshr i64 %tmp8, 32 ; [#uses=1] - %tmp3 = trunc i64 %tmp2 to i32 ; [#uses=1] - %tmp4 = bitcast i32 %tmp3 to float ; [#uses=1] - %0 = fadd float %tmp7, %tmp4 ; [#uses=1] - ret float %0 -} - -And current llvm-gcc/clang output: - movd %xmm0, %rax - movd %eax, %xmm1 - shrq $32, %rax - movd %eax, %xmm0 - addss %xmm1, %xmm0 - ret - -We really shouldn't move the floats to RAX, only to immediately move them -straight back to the XMM registers. - -There really isn't any good way to handle this purely in IR optimizers; it -could possibly be handled by changing the output of the fronted, though. It -would also be feasible to add a x86-specific DAGCombine to optimize the -bitcast+trunc+(lshr+)bitcast combination. - -//===---------------------------------------------------------------------===// - Take the following code (from http://gcc.gnu.org/bugzilla/show_bug.cgi?id=34653): extern unsigned long table[]; From rafael.espindola at gmail.com Thu Jun 9 16:20:29 2011 From: rafael.espindola at gmail.com (Rafael Avila de Espindola) Date: Thu, 09 Jun 2011 19:20:29 -0400 Subject: [llvm-commits] [llvm] r132814 - /llvm/trunk/lib/CodeGen/TailDuplication.cpp In-Reply-To: <07B5C12A-B18D-41AD-BB15-66397CD7EFA3@apple.com> References: <20110609225348.233B32A6C12C@llvm.org> <07B5C12A-B18D-41AD-BB15-66397CD7EFA3@apple.com> Message-ID: <4DF1553D.1080708@gmail.com> On 11-06-09 07:05 PM, Cameron Zwarich wrote: > Was this motivated by a test case? Yes, but it depends on us being more aggressive about early tail duplication. Right now that code path is disable for anything but indirectbrs. I found the issue by changing shouldTailDuplicate to return true for small bbs in the PreRegAlloc case, and bootstrapping clang with -tail-dup-size=8. I guess it should be possible to reproduce it now by replacing all braches with indirectbr in the test... I have one more fix to commit, and then it should be possible to benchmark the different thresholds for both taildup passes without crashing :-) > Cameron Cheers, Rafael From rafael.espindola at gmail.com Thu Jun 9 16:22:56 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 09 Jun 2011 23:22:56 -0000 Subject: [llvm-commits] [llvm] r132816 - /llvm/trunk/lib/CodeGen/TailDuplication.cpp Message-ID: <20110609232256.D4A172A6C12C@llvm.org> Author: rafael Date: Thu Jun 9 18:22:56 2011 New Revision: 132816 URL: http://llvm.org/viewvc/llvm-project?rev=132816&view=rev Log: On last fix to the early tail duplication. With this I am able to bootstrap clang with early tail duplication enabled for any small bb and setting tail-dup-size to a relatively large value(8) to stress this code. Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=132816&r1=132815&r2=132816&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original) +++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Thu Jun 9 18:22:56 2011 @@ -82,7 +82,8 @@ MachineBasicBlock *PredBB, DenseMap &LocalVRMap, SmallVector, 4> &Copies, - const DenseSet &UsedByPhi); + const DenseSet &UsedByPhi, + bool Remove); void DuplicateInstruction(MachineInstr *MI, MachineBasicBlock *TailBB, MachineBasicBlock *PredBB, @@ -336,7 +337,8 @@ MachineBasicBlock *PredBB, DenseMap &LocalVRMap, SmallVector, 4> &Copies, - const DenseSet &RegsUsedByPhi) { + const DenseSet &RegsUsedByPhi, + bool Remove) { unsigned DefReg = MI->getOperand(0).getReg(); unsigned SrcOpIdx = getPHISrcRegOpIdx(MI, PredBB); assert(SrcOpIdx && "Unable to find matching PHI source?"); @@ -351,6 +353,9 @@ if (isDefLiveOut(DefReg, TailBB, MRI) || RegsUsedByPhi.count(DefReg)) AddSSAUpdateEntry(DefReg, NewDef, PredBB); + if (!Remove) + return; + // Remove PredBB from the PHI node. MI->RemoveOperand(SrcOpIdx+1); MI->RemoveOperand(SrcOpIdx); @@ -594,7 +599,7 @@ if (MI->isPHI()) { // Replace the uses of the def of the PHI with the register coming // from PredBB. - ProcessPHI(MI, TailBB, PredBB, LocalVRMap, CopyInfos, UsedByPhi); + ProcessPHI(MI, TailBB, PredBB, LocalVRMap, CopyInfos, UsedByPhi, true); } else { // Replace def of virtual registers with new registers, and update // uses with PHI source register or the new registers. @@ -644,7 +649,7 @@ // Replace the uses of the def of the PHI with the register coming // from PredBB. MachineInstr *MI = &*I++; - ProcessPHI(MI, TailBB, PrevBB, LocalVRMap, CopyInfos, UsedByPhi); + ProcessPHI(MI, TailBB, PrevBB, LocalVRMap, CopyInfos, UsedByPhi, true); if (MI->getParent()) MI->eraseFromParent(); } @@ -675,6 +680,57 @@ Changed = true; } + // If this is after register allocation, there are no phis to fix. + if (!PreRegAlloc) + return Changed; + + // If we made no changes so far, we are safe. + if (!Changed) + return Changed; + + + // Handle the nasty case in that we duplicated a block that is part of a loop + // into some but not all of its predecessors. For example: + // 1 -> 2 <-> 3 + // \ + // \---> rest + // if we duplicate 2 into 1 but not into 3, we end up with + // 12 -> 3 <-> 2 -> rest + // \ / + // \----->-----/ + // If there was a "var = phi(1, 3)" in 2, it has to be ultimately replaced + // with a phi in 3 (which now dominates 2). + // What we do here is introduce a copy in 3 of the register defined by the + // phi, just like when we are duplicating 2 into 3, but we don't copy any + // real instructions or remove the 3 -> 2 edge from the phi in 2. + for (SmallSetVector::iterator PI = Preds.begin(), + PE = Preds.end(); PI != PE; ++PI) { + MachineBasicBlock *PredBB = *PI; + if (std::find(TDBBs.begin(), TDBBs.end(), PredBB) != TDBBs.end()) + continue; + + // EH edges + if (PredBB->succ_size() != 1) + continue; + + DenseMap LocalVRMap; + SmallVector, 4> CopyInfos; + MachineBasicBlock::iterator I = TailBB->begin(); + // Process PHI instructions first. + while (I != TailBB->end() && I->isPHI()) { + // Replace the uses of the def of the PHI with the register coming + // from PredBB. + MachineInstr *MI = &*I++; + ProcessPHI(MI, TailBB, PredBB, LocalVRMap, CopyInfos, UsedByPhi, false); + } + MachineBasicBlock::iterator Loc = PredBB->getFirstTerminator(); + for (unsigned i = 0, e = CopyInfos.size(); i != e; ++i) { + Copies.push_back(BuildMI(*PredBB, Loc, DebugLoc(), + TII->get(TargetOpcode::COPY), + CopyInfos[i].first).addReg(CopyInfos[i].second)); + } + } + return Changed; } From aggarwa4 at illinois.edu Thu Jun 9 16:26:30 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Thu, 09 Jun 2011 23:26:30 -0000 Subject: [llvm-commits] [poolalloc] r132817 - /poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Message-ID: <20110609232630.93D1E2A6C12C@llvm.org> Author: aggarwa4 Date: Thu Jun 9 18:26:30 2011 New Revision: 132817 URL: http://llvm.org/viewvc/llvm-project?rev=132817&view=rev Log: Only replace direct calls here. Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=132817&r1=132816&r2=132817&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Thu Jun 9 18:26:30 2011 @@ -637,6 +637,8 @@ CallInst *CI = dyn_cast(ui++); if(!CI) continue; + if(CI->getCalledValue()->stripPointerCasts() != &F) + continue; std::vector Args; unsigned int i; unsigned int NumArgs = CI->getNumOperands() - 1; From aggarwa4 at illinois.edu Thu Jun 9 16:41:30 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Thu, 09 Jun 2011 23:41:30 -0000 Subject: [llvm-commits] [poolalloc] r132820 - /poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Message-ID: <20110609234131.02B452A6C12C@llvm.org> Author: aggarwa4 Date: Thu Jun 9 18:41:30 2011 New Revision: 132820 URL: http://llvm.org/viewvc/llvm-project?rev=132820&view=rev Log: Do not insert AllocaInst's just anywhere. They could be inside loops. Move to function header. Thanks to SAFECode for pointing this out! Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=132820&r1=132819&r2=132820&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Thu Jun 9 18:41:30 2011 @@ -642,8 +642,9 @@ std::vector Args; unsigned int i; unsigned int NumArgs = CI->getNumOperands() - 1; + inst_iterator InsPt = inst_begin(CI->getParent()->getParent()); Value *NumArgsVal = ConstantInt::get(Int32Ty, NumArgs); - AllocaInst *AI = new AllocaInst(Int8Ty, NumArgsVal, "", CI); + AllocaInst *AI = new AllocaInst(Int8Ty, NumArgsVal, "", &*InsPt); // set the metadata for the varargs in AI for(i = 1; i getNumOperands(); i++) { Value *Idx[2]; @@ -877,10 +878,11 @@ if(!CI) continue; std::vector Args; + inst_iterator InsPt = inst_begin(CI->getParent()->getParent()); unsigned int i; unsigned int NumArgs = CI->getNumOperands() - 1; Value *NumArgsVal = ConstantInt::get(Int32Ty, NumArgs); - AllocaInst *AI = new AllocaInst(Int8Ty, NumArgsVal, "", CI); + AllocaInst *AI = new AllocaInst(Int8Ty, NumArgsVal, "", &*CI); // set the metadata for the varargs in AI for(i = 1; i getNumOperands(); i++) { Value *Idx[2]; @@ -1544,7 +1546,8 @@ unsigned int NumArgs = I->getNumOperands() - 1; Value *NumArgsVal = ConstantInt::get(Int32Ty, NumArgs); - AllocaInst *AI = new AllocaInst(Int8Ty, NumArgsVal, "", I); + inst_iterator InsPt = inst_begin(I->getParent()->getParent()); + AllocaInst *AI = new AllocaInst(Int8Ty, NumArgsVal, "", &*InsPt); for(unsigned int i = 1; i < I->getNumOperands(); i++) { Value *Idx[2]; Idx[0] = ConstantInt::get(Int32Ty, i-1); From rafael.espindola at gmail.com Thu Jun 9 16:51:45 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 09 Jun 2011 23:51:45 -0000 Subject: [llvm-commits] [llvm] r132821 - /llvm/trunk/lib/CodeGen/TailDuplication.cpp Message-ID: <20110609235145.2E7532A6C12C@llvm.org> Author: rafael Date: Thu Jun 9 18:51:45 2011 New Revision: 132821 URL: http://llvm.org/viewvc/llvm-project?rev=132821&view=rev Log: Avoid a gcc warning about multiline comments. Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=132821&r1=132820&r2=132821&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original) +++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Thu Jun 9 18:51:45 2011 @@ -691,13 +691,13 @@ // Handle the nasty case in that we duplicated a block that is part of a loop // into some but not all of its predecessors. For example: - // 1 -> 2 <-> 3 - // \ - // \---> rest + // 1 -> 2 <-> 3 | + // \ | + // \---> rest | // if we duplicate 2 into 1 but not into 3, we end up with - // 12 -> 3 <-> 2 -> rest - // \ / - // \----->-----/ + // 12 -> 3 <-> 2 -> rest | + // \ / | + // \----->-----/ | // If there was a "var = phi(1, 3)" in 2, it has to be ultimately replaced // with a phi in 3 (which now dominates 2). // What we do here is introduce a copy in 3 of the register defined by the From rafael.espindola at gmail.com Thu Jun 9 16:55:56 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 09 Jun 2011 23:55:56 -0000 Subject: [llvm-commits] [llvm] r132822 - /llvm/trunk/lib/CodeGen/TailDuplication.cpp Message-ID: <20110609235556.4E2152A6C12C@llvm.org> Author: rafael Date: Thu Jun 9 18:55:56 2011 New Revision: 132822 URL: http://llvm.org/viewvc/llvm-project?rev=132822&view=rev Log: Make the optional verification step more strict. Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=132822&r1=132821&r2=132822&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original) +++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Thu Jun 9 18:55:56 2011 @@ -152,11 +152,11 @@ for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2) { MachineBasicBlock *PHIBB = MI->getOperand(i+1).getMBB(); if (CheckExtra && !Preds.count(PHIBB)) { - // This is not a hard error. dbgs() << "Warning: malformed PHI in BB#" << MBB->getNumber() << ": " << *MI; dbgs() << " extra input from predecessor BB#" << PHIBB->getNumber() << '\n'; + llvm_unreachable(0); } if (PHIBB->getNumber() < 0) { dbgs() << "Malformed PHI in BB#" << MBB->getNumber() << ": " << *MI; @@ -443,6 +443,13 @@ // This register is defined in the tail block. for (unsigned j = 0, ee = LI->second.size(); j != ee; ++j) { MachineBasicBlock *SrcBB = LI->second[j].first; + // If we didn't duplicate a bb into a particular predecessor, we + // might still have added an entry to SSAUpdateVals to correcly + // recompute SSA. If that case, avoid adding a dummy extra argument + // this PHI. + if (!SrcBB->isSuccessor(SuccBB)) + continue; + unsigned SrcReg = LI->second[j].second; if (Idx != 0) { II->getOperand(Idx).setReg(SrcReg); From eli.friedman at gmail.com Thu Jun 9 17:30:08 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Fri, 10 Jun 2011 00:30:08 -0000 Subject: [llvm-commits] [llvm] r132824 - /llvm/trunk/test/CodeGen/X86/fold-xmm-zero.ll Message-ID: <20110610003008.AFF972A6C12C@llvm.org> Author: efriedma Date: Thu Jun 9 19:30:08 2011 New Revision: 132824 URL: http://llvm.org/viewvc/llvm-project?rev=132824&view=rev Log: Add a simple test which makes sure folding immediate float zero to a memory operand works. Added: llvm/trunk/test/CodeGen/X86/fold-xmm-zero.ll Added: llvm/trunk/test/CodeGen/X86/fold-xmm-zero.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fold-xmm-zero.ll?rev=132824&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/fold-xmm-zero.ll (added) +++ llvm/trunk/test/CodeGen/X86/fold-xmm-zero.ll Thu Jun 9 19:30:08 2011 @@ -0,0 +1,34 @@ +; RUN: llc < %s -mtriple=i386-apple-macosx10.6.7 | FileCheck %s + +; Simple test to make sure folding for special constants (like float zero) +; isn't completely broken. + +; CHECK: divss LCPI0 + +%0 = type { float, float, float, float, float, float, float, float } + +define void @f() nounwind ssp { +entry: + %0 = tail call %0 asm sideeffect "foo", "={xmm0},={xmm1},={xmm2},={xmm3},={xmm4},={xmm5},={xmm6},={xmm7},0,1,2,3,4,5,6,7,~{dirflag},~{fpsr},~{flags}"(float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00, float 8.000000e+00) nounwind + %asmresult = extractvalue %0 %0, 0 + %asmresult8 = extractvalue %0 %0, 1 + %asmresult9 = extractvalue %0 %0, 2 + %asmresult10 = extractvalue %0 %0, 3 + %asmresult11 = extractvalue %0 %0, 4 + %asmresult12 = extractvalue %0 %0, 5 + %asmresult13 = extractvalue %0 %0, 6 + %asmresult14 = extractvalue %0 %0, 7 + %div = fdiv float %asmresult, 0.000000e+00 + %1 = tail call %0 asm sideeffect "bar", "={xmm0},={xmm1},={xmm2},={xmm3},={xmm4},={xmm5},={xmm6},={xmm7},0,1,2,3,4,5,6,7,~{dirflag},~{fpsr},~{flags}"(float %div, float %asmresult8, float %asmresult9, float %asmresult10, float %asmresult11, float %asmresult12, float %asmresult13, float %asmresult14) nounwind + %asmresult24 = extractvalue %0 %1, 0 + %asmresult25 = extractvalue %0 %1, 1 + %asmresult26 = extractvalue %0 %1, 2 + %asmresult27 = extractvalue %0 %1, 3 + %asmresult28 = extractvalue %0 %1, 4 + %asmresult29 = extractvalue %0 %1, 5 + %asmresult30 = extractvalue %0 %1, 6 + %asmresult31 = extractvalue %0 %1, 7 + %div33 = fdiv float %asmresult24, 0.000000e+00 + %2 = tail call %0 asm sideeffect "baz", "={xmm0},={xmm1},={xmm2},={xmm3},={xmm4},={xmm5},={xmm6},={xmm7},0,1,2,3,4,5,6,7,~{dirflag},~{fpsr},~{flags}"(float %div33, float %asmresult25, float %asmresult26, float %asmresult27, float %asmresult28, float %asmresult29, float %asmresult30, float %asmresult31) nounwind + ret void +} From mcrosier at apple.com Thu Jun 9 17:53:15 2011 From: mcrosier at apple.com (Chad Rosier) Date: Fri, 10 Jun 2011 00:53:15 -0000 Subject: [llvm-commits] [llvm] r132825 - /llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Message-ID: <20110610005315.5D8952A6C12C@llvm.org> Author: mcrosier Date: Thu Jun 9 19:53:15 2011 New Revision: 132825 URL: http://llvm.org/viewvc/llvm-project?rev=132825&view=rev Log: Ensure that EmitGlobalVariable is correctly differentiating between declarations and definitions when emitting global variables. This was causing global declarations to be emitted as if they were definitions. Fixes . Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=132825&r1=132824&r2=132825&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Thu Jun 9 19:53:15 2011 @@ -269,7 +269,7 @@ } MCSymbol *GVSym = Mang->getSymbol(GV); - EmitVisibility(GVSym, GV->getVisibility()); + EmitVisibility(GVSym, GV->getVisibility(), !GV->isDeclaration()); if (!GV->hasInitializer()) // External globals require no extra code. return; From eli.friedman at gmail.com Thu Jun 9 18:17:07 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Thu, 9 Jun 2011 18:17:07 -0700 Subject: [llvm-commits] [llvm] r132825 - /llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp In-Reply-To: <20110610005315.5D8952A6C12C@llvm.org> References: <20110610005315.5D8952A6C12C@llvm.org> Message-ID: On Thu, Jun 9, 2011 at 5:53 PM, Chad Rosier wrote: > Author: mcrosier > Date: Thu Jun  9 19:53:15 2011 > New Revision: 132825 > > URL: http://llvm.org/viewvc/llvm-project?rev=132825&view=rev > Log: > Ensure that EmitGlobalVariable is correctly differentiating between declarations > and definitions when emitting global variables.  This was causing global > declarations to be emitted as if they were definitions. > Fixes . Testcase? -Eli > Modified: >    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp > > Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=132825&r1=132824&r2=132825&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) > +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Thu Jun  9 19:53:15 2011 > @@ -269,7 +269,7 @@ >   } > >   MCSymbol *GVSym = Mang->getSymbol(GV); > -  EmitVisibility(GVSym, GV->getVisibility()); > +  EmitVisibility(GVSym, GV->getVisibility(), !GV->isDeclaration()); > >   if (!GV->hasInitializer())   // External globals require no extra code. >     return; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From eli.friedman at gmail.com Thu Jun 9 18:13:01 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Fri, 10 Jun 2011 01:13:01 -0000 Subject: [llvm-commits] [llvm] r132826 - /llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Message-ID: <20110610011302.05BB82A6C12C@llvm.org> Author: efriedma Date: Thu Jun 9 20:13:01 2011 New Revision: 132826 URL: http://llvm.org/viewvc/llvm-project?rev=132826&view=rev Log: PR10092 (second try): Don't crash on a load without a momoperand; fast-isel creates loads like this. Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=132826&r1=132825&r2=132826&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Thu Jun 9 20:13:01 2011 @@ -2420,7 +2420,7 @@ Alignment = 4; break; default: - llvm_unreachable("Don't know how to fold this instruction!"); + return 0; } if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { unsigned NewOpc = 0; From mcrosier at apple.com Thu Jun 9 19:35:12 2011 From: mcrosier at apple.com (Chad Rosier) Date: Thu, 09 Jun 2011 19:35:12 -0700 Subject: [llvm-commits] [llvm] r132825 - /llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp In-Reply-To: References: <20110610005315.5D8952A6C12C@llvm.org> Message-ID: <4B247008-6BBB-4CF9-A101-B1B721C36DD0@apple.com> On Jun 9, 2011, at 6:17 PM, Eli Friedman wrote: > On Thu, Jun 9, 2011 at 5:53 PM, Chad Rosier wrote: >> Author: mcrosier >> Date: Thu Jun 9 19:53:15 2011 >> New Revision: 132825 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=132825&view=rev >> Log: >> Ensure that EmitGlobalVariable is correctly differentiating between declarations >> and definitions when emitting global variables. This was causing global >> declarations to be emitted as if they were definitions. >> Fixes . > > Testcase? Sorry about that. Working on this now. > -Eli > >> Modified: >> llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp >> >> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=132825&r1=132824&r2=132825&view=diff >> ============================================================================== >> --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) >> +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Thu Jun 9 19:53:15 2011 >> @@ -269,7 +269,7 @@ >> } >> >> MCSymbol *GVSym = Mang->getSymbol(GV); >> - EmitVisibility(GVSym, GV->getVisibility()); >> + EmitVisibility(GVSym, GV->getVisibility(), !GV->isDeclaration()); >> >> if (!GV->hasInitializer()) // External globals require no extra code. >> return; >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> -------------- next part -------------- An HTML attachment was scrubbed... URL: From mcrosier at apple.com Thu Jun 9 19:44:19 2011 From: mcrosier at apple.com (Chad Rosier) Date: Fri, 10 Jun 2011 02:44:19 -0000 Subject: [llvm-commits] [llvm] r132830 - /llvm/trunk/test/CodeGen/X86/visibility2.ll Message-ID: <20110610024419.CE9FA2A6C12C@llvm.org> Author: mcrosier Date: Thu Jun 9 21:44:19 2011 New Revision: 132830 URL: http://llvm.org/viewvc/llvm-project?rev=132830&view=rev Log: Adding a test case for revision 132825. Added: llvm/trunk/test/CodeGen/X86/visibility2.ll Added: llvm/trunk/test/CodeGen/X86/visibility2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/visibility2.ll?rev=132830&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/visibility2.ll (added) +++ llvm/trunk/test/CodeGen/X86/visibility2.ll Thu Jun 9 21:44:19 2011 @@ -0,0 +1,18 @@ +; This test case ensures that when the visibility of a global declaration is +; emitted they are not treated as definitions. Test case for r132825. +; Fixes . +; +; RUN: llc -mtriple=x86_64-apple-darwin %s -o - | FileCheck %s + + at foo_private_extern_str = external hidden global i8* + +define void @foo1() nounwind ssp { +entry: + %tmp = load i8** @foo_private_extern_str, align 8 + call void @foo3(i8* %tmp) + ret void +} + +declare void @foo3(i8*) + +; CHECK-NOT: .private_extern From michael_rosier at apple.com Thu Jun 9 19:57:59 2011 From: michael_rosier at apple.com (Chad Rosier) Date: Thu, 09 Jun 2011 19:57:59 -0700 Subject: [llvm-commits] [llvm] r132825 - /llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp In-Reply-To: <4B247008-6BBB-4CF9-A101-B1B721C36DD0@apple.com> References: <20110610005315.5D8952A6C12C@llvm.org> <4B247008-6BBB-4CF9-A101-B1B721C36DD0@apple.com> Message-ID: <4BE3D40F-66D7-4439-951A-6648D229B88D@apple.com> On Jun 9, 2011, at 7:35 PM, Chad Rosier wrote: > On Jun 9, 2011, at 6:17 PM, Eli Friedman wrote: > >> On Thu, Jun 9, 2011 at 5:53 PM, Chad Rosier wrote: >>> Author: mcrosier >>> Date: Thu Jun 9 19:53:15 2011 >>> New Revision: 132825 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=132825&view=rev >>> Log: >>> Ensure that EmitGlobalVariable is correctly differentiating between declarations >>> and definitions when emitting global variables. This was causing global >>> declarations to be emitted as if they were definitions. >>> Fixes . >> >> Testcase? > > Sorry about that. Working on this now. Committed revision 132830. Chad > >> -Eli >> >>> Modified: >>> llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp >>> >>> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=132825&r1=132824&r2=132825&view=diff >>> ============================================================================== >>> --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) >>> +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Thu Jun 9 19:53:15 2011 >>> @@ -269,7 +269,7 @@ >>> } >>> >>> MCSymbol *GVSym = Mang->getSymbol(GV); >>> - EmitVisibility(GVSym, GV->getVisibility()); >>> + EmitVisibility(GVSym, GV->getVisibility(), !GV->isDeclaration()); >>> >>> if (!GV->hasInitializer()) // External globals require no extra code. >>> return; >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- An HTML attachment was scrubbed... URL: From gkistanova at gmail.com Thu Jun 9 20:57:02 2011 From: gkistanova at gmail.com (Galina Kistanova) Date: Fri, 10 Jun 2011 03:57:02 -0000 Subject: [llvm-commits] [llvm] r132834 - /llvm/trunk/test/FrontendC/ARM/dg.exp Message-ID: <20110610035702.CC6BB2A6C12C@llvm.org> Author: gkistanova Date: Thu Jun 9 22:57:02 2011 New Revision: 132834 URL: http://llvm.org/viewvc/llvm-project?rev=132834&view=rev Log: Changed condition. Modified: llvm/trunk/test/FrontendC/ARM/dg.exp Modified: llvm/trunk/test/FrontendC/ARM/dg.exp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/ARM/dg.exp?rev=132834&r1=132833&r2=132834&view=diff ============================================================================== --- llvm/trunk/test/FrontendC/ARM/dg.exp (original) +++ llvm/trunk/test/FrontendC/ARM/dg.exp Thu Jun 9 22:57:02 2011 @@ -1,5 +1,5 @@ load_lib llvm.exp -if { [llvm_supports_target ARM] AND [ llvm_gcc_supports c ] } { +if { [llvm_supports_target ARM] && [llvm_gcc_supports c] } { RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp,s}]] } From geek4civic at gmail.com Thu Jun 9 21:02:45 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Fri, 10 Jun 2011 13:02:45 +0900 Subject: [llvm-commits] [llvm] r132777 - in /llvm/trunk: lib/Target/Mips/MipsAsmPrinter.cpp lib/Target/Mips/MipsISelDAGToDAG.cpp lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsISelLowering.h lib/Target/Mips/MipsInstrInfo.td lib/Target/Mips/MipsM In-Reply-To: References: Message-ID: 2011/6/10 Eric Christopher : > > On Jun 9, 2011, at 4:01 PM, Eli Friedman wrote: > >> On Thu, Jun 9, 2011 at 9:03 AM, Eric Christopher wrote: >>> Author: echristo >>> Date: Thu Jun  9 11:03:19 2011 >>> New Revision: 132777 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=132777&view=rev >>> Log: >>> Speculatively revert 132758 and 132768 to try to fix the Windows buildbots. >> >> It didn't work. :(  I have no idea what else to try. > > Me either. Reverting mine didn't work either. I cannot reproduce on msys mingw, damn. test/CodeGen/Mips can pass for me with any (Release|Debug)+-Asserts configurations. ...Takumi From nicholas at mxc.ca Thu Jun 9 21:13:08 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Thu, 09 Jun 2011 21:13:08 -0700 Subject: [llvm-commits] [llvm] r132797 - in /llvm/trunk: include/llvm/Analysis/CallGraph.h lib/Analysis/IPA/CallGraph.cpp lib/Analysis/IPA/CallGraphSCCPass.cpp lib/Transforms/Utils/InlineFunction.cpp In-Reply-To: <20110609194627.D56E42A6C12C@llvm.org> References: <20110609194627.D56E42A6C12C@llvm.org> Message-ID: <4DF199D4.4050006@mxc.ca> John McCall wrote: > Author: rjmccall > Date: Thu Jun 9 14:46:27 2011 > New Revision: 132797 > > URL: http://llvm.org/viewvc/llvm-project?rev=132797&view=rev > Log: > Teach the CallGraph to ignore calls to intrinsics. Why? Nick > > > Modified: > llvm/trunk/include/llvm/Analysis/CallGraph.h > llvm/trunk/lib/Analysis/IPA/CallGraph.cpp > llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp > llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp > > Modified: llvm/trunk/include/llvm/Analysis/CallGraph.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/CallGraph.h?rev=132797&r1=132796&r2=132797&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Analysis/CallGraph.h (original) > +++ llvm/trunk/include/llvm/Analysis/CallGraph.h Thu Jun 9 14:46:27 2011 > @@ -259,6 +259,9 @@ > /// addCalledFunction - Add a function to the list of functions called by this > /// one. > void addCalledFunction(CallSite CS, CallGraphNode *M) { > + assert(!CS.getInstruction() || > + !CS.getCalledFunction() || > + !CS.getCalledFunction()->isIntrinsic()); > CalledFunctions.push_back(std::make_pair(CS.getInstruction(), M)); > M->AddRef(); > } > > Modified: llvm/trunk/lib/Analysis/IPA/CallGraph.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IPA/CallGraph.cpp?rev=132797&r1=132796&r2=132797&view=diff > ============================================================================== > --- llvm/trunk/lib/Analysis/IPA/CallGraph.cpp (original) > +++ llvm/trunk/lib/Analysis/IPA/CallGraph.cpp Thu Jun 9 14:46:27 2011 > @@ -148,7 +148,7 @@ > for (BasicBlock::iterator II = BB->begin(), IE = BB->end(); > II != IE; ++II) { > CallSite CS(cast(II)); > - if (CS&& !isa(II)) { > + if (CS&& !isa(II)) { > const Function *Callee = CS.getCalledFunction(); > if (Callee) > Node->addCalledFunction(CS, getOrInsertFunction(Callee)); > > Modified: llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp?rev=132797&r1=132796&r2=132797&view=diff > ============================================================================== > --- llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp (original) > +++ llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp Thu Jun 9 14:46:27 2011 > @@ -245,8 +245,8 @@ > > for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) > for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) { > - CallSite CS(cast(I)); > - if (!CS || isa(I)) continue; > + CallSite CS(cast(I)); > + if (!CS || isa(I)) continue; > > // If this call site already existed in the callgraph, just verify it > // matches up to expectations and remove it from CallSites. > > Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp?rev=132797&r1=132796&r2=132797&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp (original) > +++ llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Thu Jun 9 14:46:27 2011 > @@ -132,18 +132,6 @@ > }; > } > > -/// Replace all the instruction uses of a value with a different value. > -/// This has the advantage of not screwing up the CallGraph. > -static void replaceAllInsnUsesWith(Instruction *insn, Value *replacement) { > - for (Value::use_iterator i = insn->use_begin(), e = insn->use_end(); > - i != e; ) { > - Use&use = i.getUse(); > - ++i; > - if (isa(use.getUser())) > - use.set(replacement); > - } > -} > - > /// Get or create a target for the branch out of rewritten calls to > /// llvm.eh.resume. > BasicBlock *InvokeInliningInfo::getInnerUnwindDest() { > @@ -196,14 +184,14 @@ > // Create a phi for the exception value... > InnerExceptionPHI = PHINode::Create(exn->getType(), phiCapacity, > "exn.lpad-body", insertPoint); > - replaceAllInsnUsesWith(exn, InnerExceptionPHI); > + exn->replaceAllUsesWith(InnerExceptionPHI); > selector->setArgOperand(0, exn); // restore this use > InnerExceptionPHI->addIncoming(exn, OuterUnwindDest); > > // ...and the selector. > InnerSelectorPHI = PHINode::Create(selector->getType(), phiCapacity, > "selector.lpad-body", insertPoint); > - replaceAllInsnUsesWith(selector, InnerSelectorPHI); > + selector->replaceAllUsesWith(InnerSelectorPHI); > InnerSelectorPHI->addIncoming(selector, OuterUnwindDest); > > // All done. > @@ -547,15 +535,7 @@ > ConstantInt::get(Type::getInt32Ty(Context), 1), > ConstantInt::getFalse(Context) // isVolatile > }; > - CallInst *TheMemCpy = > - CallInst::Create(MemCpyFn, CallArgs, CallArgs+5, "", TheCall); > - > - // If we have a call graph, update it. > - if (CallGraph *CG = IFI.CG) { > - CallGraphNode *MemCpyCGN = CG->getOrInsertFunction(MemCpyFn); > - CallGraphNode *CallerNode = (*CG)[Caller]; > - CallerNode->addCalledFunction(TheMemCpy, MemCpyCGN); > - } > + CallInst::Create(MemCpyFn, CallArgs, CallArgs+5, "", TheCall); > > // Uses of the argument in the function should use our new alloca > // instead. > @@ -767,12 +747,10 @@ > if (hasLifetimeMarkers(AI)) > continue; > > - CallInst *StartCall = builder.CreateLifetimeStart(AI); > - if (IFI.CG) CallerNode->addCalledFunction(StartCall, StartCGN); > + builder.CreateLifetimeStart(AI); > for (unsigned ri = 0, re = Returns.size(); ri != re; ++ri) { > IRBuilder<> builder(Returns[ri]); > - CallInst *EndCall = builder.CreateLifetimeEnd(AI); > - if (IFI.CG) CallerNode->addCalledFunction(EndCall, EndCGN); > + builder.CreateLifetimeEnd(AI); > } > } > } > @@ -785,25 +763,14 @@ > Function *StackSave = Intrinsic::getDeclaration(M, Intrinsic::stacksave); > Function *StackRestore=Intrinsic::getDeclaration(M,Intrinsic::stackrestore); > > - // If we are preserving the callgraph, add edges to the stacksave/restore > - // functions for the calls we insert. > - CallGraphNode *StackSaveCGN = 0, *StackRestoreCGN = 0, *CallerNode = 0; > - if (CallGraph *CG = IFI.CG) { > - StackSaveCGN = CG->getOrInsertFunction(StackSave); > - StackRestoreCGN = CG->getOrInsertFunction(StackRestore); > - CallerNode = (*CG)[Caller]; > - } > - > // Insert the llvm.stacksave. > CallInst *SavedPtr = CallInst::Create(StackSave, "savedstack", > FirstNewBlock->begin()); > - if (IFI.CG) CallerNode->addCalledFunction(SavedPtr, StackSaveCGN); > > // Insert a call to llvm.stackrestore before any return instructions in the > // inlined function. > for (unsigned i = 0, e = Returns.size(); i != e; ++i) { > - CallInst *CI = CallInst::Create(StackRestore, SavedPtr, "", Returns[i]); > - if (IFI.CG) CallerNode->addCalledFunction(CI, StackRestoreCGN); > + CallInst::Create(StackRestore, SavedPtr, "", Returns[i]); > } > > // Count the number of StackRestore calls we insert. > @@ -815,8 +782,7 @@ > for (Function::iterator BB = FirstNewBlock, E = Caller->end(); > BB != E; ++BB) > if (UnwindInst *UI = dyn_cast(BB->getTerminator())) { > - CallInst *CI = CallInst::Create(StackRestore, SavedPtr, "", UI); > - if (IFI.CG) CallerNode->addCalledFunction(CI, StackRestoreCGN); > + CallInst::Create(StackRestore, SavedPtr, "", UI); > ++NumStackRestores; > } > } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From zwarich at apple.com Thu Jun 9 21:15:29 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Thu, 09 Jun 2011 21:15:29 -0700 Subject: [llvm-commits] [llvm] r132797 - in /llvm/trunk: include/llvm/Analysis/CallGraph.h lib/Analysis/IPA/CallGraph.cpp lib/Analysis/IPA/CallGraphSCCPass.cpp lib/Transforms/Utils/InlineFunction.cpp In-Reply-To: <20110609194627.D56E42A6C12C@llvm.org> References: <20110609194627.D56E42A6C12C@llvm.org> Message-ID: <24F08B64-EE6F-49E0-BE84-F056B6FE09DB@apple.com> On Jun 9, 2011, at 12:46 PM, John McCall wrote: > Author: rjmccall > Date: Thu Jun 9 14:46:27 2011 > New Revision: 132797 > > URL: http://llvm.org/viewvc/llvm-project?rev=132797&view=rev > Log: > Teach the CallGraph to ignore calls to intrinsics. I think this needs a test case. Cameron From gkistanova at gmail.com Thu Jun 9 22:35:26 2011 From: gkistanova at gmail.com (Galina Kistanova) Date: Fri, 10 Jun 2011 05:35:26 -0000 Subject: [llvm-commits] [llvm] r132836 - /llvm/trunk/test/FrontendC/ARM/inline-asm-multichar.c Message-ID: <20110610053526.237352A6C12C@llvm.org> Author: gkistanova Date: Fri Jun 10 00:35:25 2011 New Revision: 132836 URL: http://llvm.org/viewvc/llvm-project?rev=132836&view=rev Log: Reverted r132785. It seems this test needs more research. Modified: llvm/trunk/test/FrontendC/ARM/inline-asm-multichar.c Modified: llvm/trunk/test/FrontendC/ARM/inline-asm-multichar.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/ARM/inline-asm-multichar.c?rev=132836&r1=132835&r2=132836&view=diff ============================================================================== --- llvm/trunk/test/FrontendC/ARM/inline-asm-multichar.c (original) +++ llvm/trunk/test/FrontendC/ARM/inline-asm-multichar.c Fri Jun 10 00:35:25 2011 @@ -1,8 +1,11 @@ // RUN: %llvmgcc -S -march=armv7a %s +// XFAIL: * +// XTARGET: arm + int t1() { static float k = 1.0f; -// CHECK: call void asm sideeffect "flds s15, $0 \0A", "*^Uv,~{s15}" +CHECK: call void asm sideeffect "flds s15, $0 \0A", "*^Uv,~{s15}" __asm__ volatile ("flds s15, %[k] \n" :: [k] "Uv,m" (k) : "s15"); return 0; } From gkistanova at gmail.com Fri Jun 10 00:00:40 2011 From: gkistanova at gmail.com (Galina Kistanova) Date: Fri, 10 Jun 2011 00:00:40 -0700 Subject: [llvm-commits] [llvm] r132785 - in /llvm/trunk/test/FrontendC/ARM: dg.exp inline-asm-multichar.c In-Reply-To: References: <20110609171838.1540F2A6C12C@llvm.org> Message-ID: Yeah. It looks like the test requires more attention. I have rolled back my change. Now it should be unsupported for all targets other than ARM and if llm-gcc doesn't support c. Otherwise it xfails. -Galina On Thu, Jun 9, 2011 at 3:06 PM, Eli Friedman wrote: >> Modified: >>    llvm/trunk/test/FrontendC/ARM/inline-asm-multichar.c > > This is breaking buildbots; see > http://google1.osuosl.org:8011/builders/llvm-gcc-i386-linux-selfhost/builds/2801 > . > > -Eli From baldrick at free.fr Fri Jun 10 00:45:30 2011 From: baldrick at free.fr (Duncan Sands) Date: Fri, 10 Jun 2011 09:45:30 +0200 Subject: [llvm-commits] [llvm] r132803 - /llvm/trunk/lib/Transforms/IPO/PruneEH.cpp In-Reply-To: <20110609203109.C75642A6C12C@llvm.org> References: <20110609203109.C75642A6C12C@llvm.org> Message-ID: <4DF1CB9A.1070302@free.fr> Hi John, > When deleting a basic block, remove call edges only for non-intrinsics. > > > Modified: > llvm/trunk/lib/Transforms/IPO/PruneEH.cpp > > Modified: llvm/trunk/lib/Transforms/IPO/PruneEH.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/PruneEH.cpp?rev=132803&r1=132802&r2=132803&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/IPO/PruneEH.cpp (original) > +++ llvm/trunk/lib/Transforms/IPO/PruneEH.cpp Thu Jun 9 15:31:09 2011 > @@ -239,7 +239,7 @@ > for (BasicBlock::iterator I = BB->end(), E = BB->begin(); I != E; ) { > --I; > if (CallInst *CI = dyn_cast(I)) { > - if (!isa(I)) > + if (!isa(I)) > CGN->removeCallEdgeFor(CI); > } else if (InvokeInst *II = dyn_cast(I)) > CGN->removeCallEdgeFor(II); in theory you can have an invoke of an intrinsic I think (not sure), though of course they tend to quickly be turned into calls because of the nounwind attribute (but what if someone hand wrote some IR with an invoke of your new intrinsic that can throw?). So probably the same thing should be done in the invoke case. Maybe the two cases can be unified using a CallSite. Ciao, Duncan. From baldrick at free.fr Fri Jun 10 00:50:06 2011 From: baldrick at free.fr (Duncan Sands) Date: Fri, 10 Jun 2011 09:50:06 +0200 Subject: [llvm-commits] [llvm] r132805 - /llvm/trunk/lib/CodeGen/TailDuplication.cpp In-Reply-To: <20110609205542.172DC2A6C12C@llvm.org> References: <20110609205542.172DC2A6C12C@llvm.org> Message-ID: <4DF1CCAE.7010609@free.fr> > A PHI in this basic block is a use in another basic block. Testcase? Ciao, Duncan. From baldrick at free.fr Fri Jun 10 00:51:49 2011 From: baldrick at free.fr (Duncan Sands) Date: Fri, 10 Jun 2011 09:51:49 +0200 Subject: [llvm-commits] [llvm] r132806 - /llvm/trunk/lib/CodeGen/TailDuplication.cpp In-Reply-To: <20110609214325.3D1EC2A6C12C@llvm.org> References: <20110609214325.3D1EC2A6C12C@llvm.org> Message-ID: <4DF1CD15.1000208@free.fr> > AnalyzeBranch modifies the bb, but we don't want to modify a bb with > eh edges. Swap the order of the checks to avoid it. Testcase? Ciao, Duncan. From baldrick at free.fr Fri Jun 10 00:52:49 2011 From: baldrick at free.fr (Duncan Sands) Date: Fri, 10 Jun 2011 07:52:49 -0000 Subject: [llvm-commits] [dragonegg] r132837 - /dragonegg/trunk/src/Convert.cpp Message-ID: <20110610075249.B7D832A6C12D@llvm.org> Author: baldrick Date: Fri Jun 10 02:52:49 2011 New Revision: 132837 URL: http://llvm.org/viewvc/llvm-project?rev=132837&view=rev Log: Fix thinko: the shuffle mask needs to be a vector of i32, not a vector of whatever integer type is being shuffled. Modified: dragonegg/trunk/src/Convert.cpp Modified: dragonegg/trunk/src/Convert.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=132837&r1=132836&r2=132837&view=diff ============================================================================== --- dragonegg/trunk/src/Convert.cpp (original) +++ dragonegg/trunk/src/Convert.cpp Fri Jun 10 02:52:49 2011 @@ -6803,8 +6803,10 @@ /*isSigned*/false); RHS = Builder.CreateInsertElement(UndefValue::get(VecTy), RHS, Builder.getInt32(0)); + const Type *MaskTy = VectorType::get(Type::getInt32Ty(Context), + VecTy->getNumElements()); RHS = Builder.CreateShuffleVector(RHS, UndefValue::get(VecTy), - ConstantInt::get(VecTy, 0)); + ConstantInt::get(MaskTy, 0)); } } return Builder.CreateBinOp((Instruction::BinaryOps)Opc, LHS, RHS); From baldrick at free.fr Fri Jun 10 01:13:09 2011 From: baldrick at free.fr (Duncan Sands) Date: Fri, 10 Jun 2011 08:13:09 -0000 Subject: [llvm-commits] [dragonegg] r132838 - /dragonegg/trunk/src/Convert.cpp Message-ID: <20110610081309.C29522A6C12D@llvm.org> Author: baldrick Date: Fri Jun 10 03:13:09 2011 New Revision: 132838 URL: http://llvm.org/viewvc/llvm-project?rev=132838&view=rev Log: In gcc-4.5 the base pointer can have type sizetype. Modified: dragonegg/trunk/src/Convert.cpp Modified: dragonegg/trunk/src/Convert.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=132838&r1=132837&r2=132838&view=diff ============================================================================== --- dragonegg/trunk/src/Convert.cpp (original) +++ dragonegg/trunk/src/Convert.cpp Fri Jun 10 03:13:09 2011 @@ -5985,7 +5985,12 @@ Delta = EmitRegister(addr.base); } else { assert(addr.base && "TARGET_MEM_REF has neither base nor symbol!"); - Ref = LValue(EmitRegister(addr.base), 1); + Value *Base = EmitRegister(addr.base); + // The type of BASE is sizetype or a pointer type. Convert sizetype to i8*. + // TODO: In mainline BASE always has pointer type. + if (!isa(Base->getType())) + Base = Builder.CreateIntToPtr(Base, GetUnitPointerType(Context)); + Ref = LValue(Base, 1); } if (addr.index) { From eli.friedman at gmail.com Fri Jun 10 01:28:15 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Fri, 10 Jun 2011 01:28:15 -0700 Subject: [llvm-commits] [llvm] r132803 - /llvm/trunk/lib/Transforms/IPO/PruneEH.cpp In-Reply-To: <4DF1CB9A.1070302@free.fr> References: <20110609203109.C75642A6C12C@llvm.org> <4DF1CB9A.1070302@free.fr> Message-ID: On Fri, Jun 10, 2011 at 12:45 AM, Duncan Sands wrote: > Hi John, > >> When deleting a basic block, remove call edges only for non-intrinsics. >> >> >> Modified: >>      llvm/trunk/lib/Transforms/IPO/PruneEH.cpp >> >> Modified: llvm/trunk/lib/Transforms/IPO/PruneEH.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/PruneEH.cpp?rev=132803&r1=132802&r2=132803&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Transforms/IPO/PruneEH.cpp (original) >> +++ llvm/trunk/lib/Transforms/IPO/PruneEH.cpp Thu Jun  9 15:31:09 2011 >> @@ -239,7 +239,7 @@ >>     for (BasicBlock::iterator I = BB->end(), E = BB->begin(); I != E; ) { >>       --I; >>       if (CallInst *CI = dyn_cast(I)) { >> -      if (!isa(I)) >> +      if (!isa(I)) >>           CGN->removeCallEdgeFor(CI); >>       } else if (InvokeInst *II = dyn_cast(I)) >>         CGN->removeCallEdgeFor(II); > > in theory you can have an invoke of an intrinsic I think (not sure), though of > course they tend to quickly be turned into calls because of the nounwind > attribute (but what if someone hand wrote some IR with an invoke of your new > intrinsic that can throw?).  So probably the same thing should be done in the > invoke case.  Maybe the two cases can be unified using a CallSite. You aren't allowed to invoke intrinsics; the verifier enforces this. Using CallSite is always nice, though. -Eli From eli.friedman at gmail.com Fri Jun 10 01:26:26 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Fri, 10 Jun 2011 08:26:26 -0000 Subject: [llvm-commits] [llvm] r132839 - /llvm/trunk/test/CodeGen/X86/fold-xmm-zero.ll Message-ID: <20110610082626.A975B2A6C12C@llvm.org> Author: efriedma Date: Fri Jun 10 03:26:26 2011 New Revision: 132839 URL: http://llvm.org/viewvc/llvm-project?rev=132839&view=rev Log: Add -mattr=+sse2 to make the buildbots happy. Modified: llvm/trunk/test/CodeGen/X86/fold-xmm-zero.ll Modified: llvm/trunk/test/CodeGen/X86/fold-xmm-zero.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fold-xmm-zero.ll?rev=132839&r1=132838&r2=132839&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fold-xmm-zero.ll (original) +++ llvm/trunk/test/CodeGen/X86/fold-xmm-zero.ll Fri Jun 10 03:26:26 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i386-apple-macosx10.6.7 | FileCheck %s +; RUN: llc < %s -mtriple=i386-apple-macosx10.6.7 -mattr=+sse2 | FileCheck %s ; Simple test to make sure folding for special constants (like float zero) ; isn't completely broken. From richard at xmos.com Fri Jun 10 05:28:25 2011 From: richard at xmos.com (Richard Osborne) Date: Fri, 10 Jun 2011 12:28:25 -0000 Subject: [llvm-commits] [llvm] r132844 - /llvm/trunk/include/llvm/Support/PassManagerBuilder.h Message-ID: <20110610122825.10CA52A6C12C@llvm.org> Author: friedgold Date: Fri Jun 10 07:28:24 2011 New Revision: 132844 URL: http://llvm.org/viewvc/llvm-project?rev=132844&view=rev Log: Fix example code in comment. Modified: llvm/trunk/include/llvm/Support/PassManagerBuilder.h Modified: llvm/trunk/include/llvm/Support/PassManagerBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/PassManagerBuilder.h?rev=132844&r1=132843&r2=132844&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/PassManagerBuilder.h (original) +++ llvm/trunk/include/llvm/Support/PassManagerBuilder.h Fri Jun 10 07:28:24 2011 @@ -32,8 +32,8 @@ /// sequence for languages like C and C++, allowing some APIs to customize the /// pass sequence in various ways. A simple example of using it would be: /// -/// OptimizerBuilder Builder; -/// Builder.setOptimizationLevel(2); +/// PassManagerBuilder Builder; +/// Builder.OptLevel = 2; /// Builder.populateFunctionPassManager(FPM); /// Builder.populateModulePassManager(MPM); /// From rafael.espindola at gmail.com Fri Jun 10 05:40:29 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Fri, 10 Jun 2011 08:40:29 -0400 Subject: [llvm-commits] [llvm] r132805 - /llvm/trunk/lib/CodeGen/TailDuplication.cpp In-Reply-To: <4DF1CCAE.7010609@free.fr> References: <20110609205542.172DC2A6C12C@llvm.org> <4DF1CCAE.7010609@free.fr> Message-ID: <4DF210BD.4080603@gmail.com> On 11-06-10 3:50 AM, Duncan Sands wrote: >> A PHI in this basic block is a use in another basic block. > > Testcase? Early tail duplication is effectively disable right now for anything but indirectbr. I found the problem by enabling it and setting a large size (8) while bootstrapping clang. > Ciao, Duncan. Cheers, Rafael From baldrick at free.fr Fri Jun 10 06:25:15 2011 From: baldrick at free.fr (Duncan Sands) Date: Fri, 10 Jun 2011 15:25:15 +0200 Subject: [llvm-commits] [llvm] r132805 - /llvm/trunk/lib/CodeGen/TailDuplication.cpp In-Reply-To: <4DF210BD.4080603@gmail.com> References: <20110609205542.172DC2A6C12C@llvm.org> <4DF1CCAE.7010609@free.fr> <4DF210BD.4080603@gmail.com> Message-ID: <4DF21B3B.5040708@free.fr> Hi Rafael, >>> A PHI in this basic block is a use in another basic block. >> >> Testcase? > > Early tail duplication is effectively disable right now for anything but > indirectbr. I found the problem by enabling it and setting a large size > (8) while bootstrapping clang. are you saying that you have a testcase but it would pass even without this patch because to get it to fail you have to tweak the LLVM source? If so, maybe you should add the testcase anyway. Ciao, Duncan. From baldrick at free.fr Fri Jun 10 06:38:44 2011 From: baldrick at free.fr (Duncan Sands) Date: Fri, 10 Jun 2011 13:38:44 -0000 Subject: [llvm-commits] [dragonegg] r132845 - /dragonegg/trunk/src/Backend.cpp Message-ID: <20110610133844.4DF3A2A6C12C@llvm.org> Author: baldrick Date: Fri Jun 10 08:38:44 2011 New Revision: 132845 URL: http://llvm.org/viewvc/llvm-project?rev=132845&view=rev Log: Make it easy to tweak the per-module and per-function optimization levels individually. Modified: dragonegg/trunk/src/Backend.cpp Modified: dragonegg/trunk/src/Backend.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Backend.cpp?rev=132845&r1=132844&r2=132845&view=diff ============================================================================== --- dragonegg/trunk/src/Backend.cpp (original) +++ dragonegg/trunk/src/Backend.cpp Fri Jun 10 08:38:44 2011 @@ -216,22 +216,16 @@ return CodeGenOpt::Aggressive; } -/// IROptLevel - The optimization level to be used by the IR level optimizers. -static int IROptLevel() { +/// PerFunctionOptLevel - The optimization level to be used by the per-function +/// IR optimizers. +static int PerFunctionOptLevel() { return LLVMIROptimizeArg >= 0 ? LLVMIROptimizeArg : optimize; } -// GuessAtInliningThreshold - Figure out a reasonable threshold to pass llvm's -// inliner. gcc has many options that control inlining, but we have decided -// not to support anything like that for llvm-gcc. -static unsigned GuessAtInliningThreshold() { - if (optimize_size) - // Reduce inline limit. - return 75; - - if (IROptLevel() >= 3) - return 275; - return 225; +/// ModuleOptLevel - The optimization level to be used by the module level IR +/// optimizers. +static int ModuleOptLevel() { + return LLVMIROptimizeArg >= 0 ? LLVMIROptimizeArg : optimize; } // SizeOfGlobalMatchesDecl - Whether the size of the given global value is the @@ -519,7 +513,6 @@ InstallLanguageSettings(); // Configure the pass builder. - PassBuilder.OptLevel = IROptLevel(); PassBuilder.SizeLevel = optimize_size; PassBuilder.DisableSimplifyLibCalls = flag_no_simplify_libcalls; PassBuilder.DisableUnrollLoops = !flag_unroll_loops; @@ -561,6 +554,7 @@ PerFunctionPasses->add(createVerifierPass()); #endif + PassBuilder.OptLevel = PerFunctionOptLevel(); PassBuilder.populateFunctionPassManager(*PerFunctionPasses); // If there are no module-level passes that have to be run, we codegen as @@ -602,8 +596,18 @@ bool NeedAlwaysInliner = false; llvm::Pass *InliningPass = 0; if (flag_inline_small_functions && !flag_no_inline) { - // Inline small functions. - InliningPass = createFunctionInliningPass(GuessAtInliningThreshold()); + // Inline small functions. Figure out a reasonable threshold to pass llvm's + // inliner. GCC has many options that control inlining, but we have decided + // not to support anything like that for dragonegg. + unsigned Threshold; + if (optimize_size) + // Reduce inline limit. + Threshold = 75; + else if (ModuleOptLevel() >= 3) + Threshold = 275; + else + Threshold = 225; + InliningPass = createFunctionInliningPass(Threshold); } else { // If full inliner is not run, check if always-inline is needed to handle // functions that are marked as always_inline. @@ -619,6 +623,7 @@ InliningPass = createAlwaysInlinerPass(); // Inline always_inline funcs } + PassBuilder.OptLevel = ModuleOptLevel(); PassBuilder.Inliner = InliningPass; PassBuilder.populateModulePassManager(*PerModulePasses); From dblaikie at gmail.com Wed Jun 8 18:42:18 2011 From: dblaikie at gmail.com (David Blaikie) Date: Wed, 8 Jun 2011 18:42:18 -0700 Subject: [llvm-commits] Retail warnings in Mips lowering code Message-ID: There's a couple of variables that are only used in asserts in the MIPS lowering code (lib/Target/Mips/MipsISelLowering.cpp) - this causes warnings in retail builds. I've fixed both instances by rolling the relevant expression (they don't appear to have any side effects) into the assert call & I added a comment in the second case since it seemed like the name of the variable gave some context/semantic information that wasn't necessarily entirely obvious from the expression itself. -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: mipswarnings.diff Type: application/octet-stream Size: 1233 bytes Desc: not available URL: From dblaikie at gmail.com Fri Jun 10 01:16:03 2011 From: dblaikie at gmail.com (David Blaikie) Date: Fri, 10 Jun 2011 01:16:03 -0700 Subject: [llvm-commits] [llvm] r132732 - /llvm/trunk/utils/TableGen/FastISelEmitter.cpp In-Reply-To: <20110607204132.03E232A6C12C@llvm.org> References: <20110607204132.03E232A6C12C@llvm.org> Message-ID: > > } else if (Operands[i].isFP()) { > OS << "f" << i; > } else { > - assert("Unknown operand kind!"); > - abort(); > + llvm_unreachable("Unknown operand kind!"); > } > if (i + 1 != e) > OS << ", "; > Just wondering about coding conventions - would it be more appropriate to change this from: else if (cond) { ... } else { /* unreachable */ } to: else { assert(cond); ... }; This would be marginally more efficient in release builds, potentially. -------------- next part -------------- An HTML attachment was scrubbed... URL: From baldrick at free.fr Fri Jun 10 07:17:24 2011 From: baldrick at free.fr (Duncan Sands) Date: Fri, 10 Jun 2011 14:17:24 -0000 Subject: [llvm-commits] [dragonegg] r132846 - /dragonegg/trunk/src/Backend.cpp Message-ID: <20110610141724.7B56B2A6C12C@llvm.org> Author: baldrick Date: Fri Jun 10 09:17:24 2011 New Revision: 132846 URL: http://llvm.org/viewvc/llvm-project?rev=132846&view=rev Log: Try a radical experiment: if GCC optimizations are run, don't try to run any heavy IR level optimizations: just do some per-function cleanup. Modified: dragonegg/trunk/src/Backend.cpp Modified: dragonegg/trunk/src/Backend.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Backend.cpp?rev=132846&r1=132845&r2=132846&view=diff ============================================================================== --- dragonegg/trunk/src/Backend.cpp (original) +++ dragonegg/trunk/src/Backend.cpp Fri Jun 10 09:17:24 2011 @@ -225,7 +225,11 @@ /// ModuleOptLevel - The optimization level to be used by the module level IR /// optimizers. static int ModuleOptLevel() { - return LLVMIROptimizeArg >= 0 ? LLVMIROptimizeArg : optimize; + if (LLVMIROptimizeArg >= 0) + return LLVMIROptimizeArg; + if (EnableGCCOptimizations) + return 0; + return optimize; } // SizeOfGlobalMatchesDecl - Whether the size of the given global value is the From rafael.espindola at gmail.com Fri Jun 10 07:55:08 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Fri, 10 Jun 2011 10:55:08 -0400 Subject: [llvm-commits] [llvm] r132805 - /llvm/trunk/lib/CodeGen/TailDuplication.cpp In-Reply-To: <4DF21B3B.5040708@free.fr> References: <20110609205542.172DC2A6C12C@llvm.org> <4DF1CCAE.7010609@free.fr> <4DF210BD.4080603@gmail.com> <4DF21B3B.5040708@free.fr> Message-ID: <4DF2304C.5040303@gmail.com> > are you saying that you have a testcase but it would pass even without this > patch because to get it to fail you have to tweak the LLVM source? If so, > maybe you should add the testcase anyway. Yes. I am currently benchmarking enabling early tail dup for any small (tail-dup-size) block. With that in I should be able to add a test that uses -tail-dup-size=8. > Ciao, Duncan. Cheers, Rafael From rjmccall at apple.com Fri Jun 10 09:11:17 2011 From: rjmccall at apple.com (John McCall) Date: Fri, 10 Jun 2011 09:11:17 -0700 Subject: [llvm-commits] [llvm] r132797 - in /llvm/trunk: include/llvm/Analysis/CallGraph.h lib/Analysis/IPA/CallGraph.cpp lib/Analysis/IPA/CallGraphSCCPass.cpp lib/Transforms/Utils/InlineFunction.cpp In-Reply-To: <4DF199D4.4050006@mxc.ca> References: <20110609194627.D56E42A6C12C@llvm.org> <4DF199D4.4050006@mxc.ca> Message-ID: <91D1DF33-BB43-4326-9395-0AC46B1F63AB@apple.com> On Jun 9, 2011, at 9:13 PM, Nick Lewycky wrote: > John McCall wrote: >> Author: rjmccall >> Date: Thu Jun 9 14:46:27 2011 >> New Revision: 132797 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=132797&view=rev >> Log: >> Teach the CallGraph to ignore calls to intrinsics. > > Why? I was hacking on the inliner and found it annoying to have to update the call graph when inserting and removing eh.exception and eh.selector calls. We were already opting the debug info intrinsics out of the call graph, or at least not making it reliable for them, so I was considering just widening that to include a few more intrinsics, but decided that it just doesn't make any sense to have intrinsics in the call graph at all. The call graph exists to serve interprocedural optimizations, which will never trigger for intrinsics because they're always declarations. Meanwhile, it's expensive to make edges for all these intrinsics, which can be pretty dense in the IR, and which are very frequently added and removed by generic optimizations. On Jun 9, 2011, at 9:15 PM, Cameron Zwarich wrote: > I think this needs a test case. Uh, sure, I'll see what I can do. John. From aggarwa4 at illinois.edu Fri Jun 10 09:13:15 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Fri, 10 Jun 2011 16:13:15 -0000 Subject: [llvm-commits] [poolalloc] r132847 - /poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Message-ID: <20110610161315.19D152A6C12C@llvm.org> Author: aggarwa4 Date: Fri Jun 10 11:13:14 2011 New Revision: 132847 URL: http://llvm.org/viewvc/llvm-project?rev=132847&view=rev Log: Cleanup debug printing. Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c?rev=132847&r1=132846&r2=132847&view=diff ============================================================================== --- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c (original) +++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Fri Jun 10 11:13:14 2011 @@ -79,7 +79,7 @@ shadow_begin[p] = typeNumber; memset(&shadow_begin[p + 1], 0, size - 1); #if DEBUG - printf("Global: %p, %p = %u | %lu bytes\n", ptr, (void *)p, typeNumber, size); + printf("Global(%d): %p, %p = %u | %lu bytes\n", tag, ptr, (void *)p, typeNumber, size); #endif } @@ -105,7 +105,7 @@ shadow_begin[p] = typeNumber; memset(&shadow_begin[p + 1], 0, size - 1); #if DEBUG - printf("Store: %p, %p = %u | %lu bytes | %d\n", ptr, (void *)p, typeNumber, size, tag); + printf("Store(%d): %p, %p = %u | %lu bytes | \n", tag, ptr, (void *)p, typeNumber, size; #endif } @@ -147,7 +147,7 @@ assert(p + size < SIZE); #if DEBUG - printf("Load: %p, %p = actual: %u, expect: %u | %lu bytes %d \n", ptr, (void *)p, typeNumber, shadow_begin[p], size, tag); + printf("Load(%d): %p, %p = actual: %u, expect: %u | %lu bytes\n", tag, ptr, (void *)p, typeNumber, shadow_begin[p], size); #endif /* Check if this an initialized but untyped memory.*/ @@ -208,7 +208,7 @@ uintptr_t s = maskAddress(srcptr); memcpy(&shadow_begin[d], &shadow_begin[s], size); #if DEBUG - printf("Copy: %p, %p = %u | %lu bytes | %u\n", dstptr, srcptr, shadow_begin[s], size, tag); + printf("Copy(%d): %p, %p = %u | %lu bytes \n", tag, dstptr, srcptr, shadow_begin[s], size); #endif } From aggarwa4 at illinois.edu Fri Jun 10 09:58:46 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Fri, 10 Jun 2011 16:58:46 -0000 Subject: [llvm-commits] [poolalloc] r132848 - /poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Message-ID: <20110610165846.631852A6C12C@llvm.org> Author: aggarwa4 Date: Fri Jun 10 11:58:46 2011 New Revision: 132848 URL: http://llvm.org/viewvc/llvm-project?rev=132848&view=rev Log: Make sure we build a correct GEP. For every new type we must add an index. For arrays, the starting pointer should be the start of the array, not the global variable. Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=132848&r1=132847&r2=132848&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Fri Jun 10 11:58:46 2011 @@ -1132,6 +1132,7 @@ if(!I->hasInitializer()) continue; SmallVectorindex; + index.push_back(ConstantInt::get(Int64Ty, 0)); visitGlobal(M, *I, I->getInitializer(), *InsertPt, index); } // @@ -1219,11 +1220,16 @@ const Type * ElementType = CA->getType()->getElementType(); // Create the type entry for the first element // using recursive creation till we get to the base types + Indices.push_back(ConstantInt::get(Int64Ty,0)); visitGlobal(M, GV, CA->getOperand(0), I, Indices); + Indices.pop_back(); + GetElementPtrInst *GEP = GetElementPtrInst::CreateInBounds(&GV, Indices.begin(), + Indices.end(),"", &I) ; + + CastInst *BCI = BitCastInst::CreatePointerCast(GEP, VoidPtrTy, "", &I); // Copy the type metadata for the first element // over for the rest of the elements. - CastInst *BCI = BitCastInst::CreatePointerCast(&GV, VoidPtrTy, "", &I); std::vector Args; Args.push_back(BCI); Args.push_back(getSizeConstant(ElementType)); @@ -1249,8 +1255,13 @@ const Type *Ty = CAZ->getType(); if(const ArrayType * ATy = dyn_cast(Ty)) { const Type * ElementType = ATy->getElementType(); + Indices.push_back(ConstantInt::get(Int64Ty,0)); visitGlobal(M, GV, Constant::getNullValue(ElementType), I, Indices); - CastInst *BCI = BitCastInst::CreatePointerCast(&GV, VoidPtrTy, "", &I); + Indices.pop_back(); + GetElementPtrInst *GEP = GetElementPtrInst::CreateInBounds(&GV, Indices.begin(), + Indices.end(),"", &I) ; + + CastInst *BCI = BitCastInst::CreatePointerCast(GEP, VoidPtrTy, "", &I); std::vector Args; Args.push_back(BCI); Args.push_back(getSizeConstant(ElementType)); From mcrosier at apple.com Fri Jun 10 10:37:31 2011 From: mcrosier at apple.com (Chad Rosier) Date: Fri, 10 Jun 2011 10:37:31 -0700 Subject: [llvm-commits] [llvm] r132732 - /llvm/trunk/utils/TableGen/FastISelEmitter.cpp In-Reply-To: References: <20110607204132.03E232A6C12C@llvm.org> Message-ID: On Jun 10, 2011, at 1:16 AM, David Blaikie wrote: > } else if (Operands[i].isFP()) { > OS << "f" << i; > } else { > - assert("Unknown operand kind!"); > - abort(); > + llvm_unreachable("Unknown operand kind!"); > } > if (i + 1 != e) > OS << ", "; > > Just wondering about coding conventions - would it be more appropriate to change this from: > else if (cond) { ... } else { /* unreachable */ } > to: > else { assert(cond); ... }; > This would be marginally more efficient in release builds, potentially. > You're correct in pointing out that most sanity checks should be written with asserts (e.g., assert (cond && "msg")). However, in the case of unreachable code we know that doom and gloom are sure to follow and thus we should gracefully abort and notify the user accordingly. There's no performance to be gained because if we've reached this state the game is already over. In general, if you see something like assert(0 && "I should have never gotten here.."); it should be replaced with llvm_unreachable("I should have never gotten here.."). Notice that the condition is hardcoded to zero and thus the assert will always fire. Chad -------------- next part -------------- An HTML attachment was scrubbed... URL: From dblaikie at gmail.com Fri Jun 10 11:22:32 2011 From: dblaikie at gmail.com (David Blaikie) Date: Fri, 10 Jun 2011 11:22:32 -0700 Subject: [llvm-commits] [llvm] r132732 - /llvm/trunk/utils/TableGen/FastISelEmitter.cpp In-Reply-To: References: <20110607204132.03E232A6C12C@llvm.org> Message-ID: > > Just wondering about coding conventions - would it be more appropriate to > change this from: > else if (cond) { ... } else { /* unreachable */ } > to: > else { assert(cond); ... }; > This would be marginally more efficient in release builds, potentially. > > > You're correct in pointing out that most sanity checks should be written > with asserts (e.g., assert (cond && "msg")). However, in the case of > unreachable code we know that doom and gloom are sure to follow and thus we > should gracefully abort and notify the user accordingly. There's no > performance to be gained because if we've reached this state the game is > already over. > > In general, if you see something like assert(0 && "I should have never > gotten here.."); it should be replaced with llvm_unreachable("I should > have never gotten here.."). Notice that the condition is hardcoded to > zero and thus the assert will always fire. > Right - but that's my point, there's performance to be gained by not at all checking 'cond' in retail builds - whereas the code as you have it now will check it unnecessarily & then go to llvm_unreachable if it's false. The perf gain would be that retail builds would never check the condition because it should never be false. That sounds like an assert to me, or am I missing something? Perhaps my example was oversimplified/unclear, what I meant was from this: } else if (Operands[i].isFP()) { OS << "ConstantFP *f" << i; } else { llvm_unreachable("Unknown operand kind!"); } to this: } else { assert(Operands[i].isFP() && "Unknown operator kind!"); OS << "ConstantFP *f" << i; } -------------- next part -------------- An HTML attachment was scrubbed... URL: From stoklund at 2pi.dk Fri Jun 10 11:40:00 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 10 Jun 2011 18:40:00 -0000 Subject: [llvm-commits] [llvm] r132849 - in /llvm/trunk/utils/TableGen: CodeGenRegisters.cpp CodeGenRegisters.h CodeGenTarget.cpp CodeGenTarget.h RegisterInfoEmitter.cpp Message-ID: <20110610184000.C77142A6C12C@llvm.org> Author: stoklund Date: Fri Jun 10 13:40:00 2011 New Revision: 132849 URL: http://llvm.org/viewvc/llvm-project?rev=132849&view=rev Log: Move some sub-register index calculations to CodeGenRegisters.cpp Create a new CodeGenRegBank class that will eventually hold all the code that computes the register structure from Records. Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.cpp llvm/trunk/utils/TableGen/CodeGenRegisters.h llvm/trunk/utils/TableGen/CodeGenTarget.cpp llvm/trunk/utils/TableGen/CodeGenTarget.h llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.cpp?rev=132849&r1=132848&r2=132849&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenRegisters.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenRegisters.cpp Fri Jun 10 13:40:00 2011 @@ -99,3 +99,30 @@ return TheDef->getName(); } +//===----------------------------------------------------------------------===// +// CodeGenRegBank +//===----------------------------------------------------------------------===// + +CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) : Records(Records) { + // Read in the user-defined (named) sub-register indices. More indices will + // be synthesized. + SubRegIndices = Records.getAllDerivedDefinitions("SubRegIndex"); + std::sort(SubRegIndices.begin(), SubRegIndices.end(), LessRecord()); + NumNamedIndices = SubRegIndices.size(); +} + +Record *CodeGenRegBank::getCompositeSubRegIndex(Record *A, Record *B) { + std::string Name = A->getName() + "_then_" + B->getName(); + Record *R = new Record(Name, SMLoc(), Records); + Records.addDef(R); + SubRegIndices.push_back(R); + return R; +} + +unsigned CodeGenRegBank::getSubRegIndexNo(Record *idx) { + std::vector::const_iterator i = + std::find(SubRegIndices.begin(), SubRegIndices.end(), idx); + assert(i != SubRegIndices.end() && "Not a SubRegIndex"); + return (i - SubRegIndices.begin()) + 1; +} + Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.h?rev=132849&r1=132848&r2=132849&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenRegisters.h (original) +++ llvm/trunk/utils/TableGen/CodeGenRegisters.h Fri Jun 10 13:40:00 2011 @@ -24,6 +24,7 @@ namespace llvm { class Record; + class RecordKeeper; /// CodeGenRegister - Represents a register definition. struct CodeGenRegister { @@ -98,6 +99,32 @@ CodeGenRegisterClass(Record *R); }; + + // CodeGenRegBank - Represent a target's registers and the relations between + // them. + class CodeGenRegBank { + RecordKeeper &Records; + + // Sub-register indices. The first NumNamedIndices are defined by the user + // in the .td files. The rest are synthesized such that all sub-registers + // have a unique name. + std::vector SubRegIndices; + + unsigned NumNamedIndices; + + public: + CodeGenRegBank(RecordKeeper&); + + const std::vector &getSubRegIndices() { return SubRegIndices; } + + unsigned getNumNamedIndices() { return NumNamedIndices; } + + // Map a SubRegIndex Record to its enum value. + unsigned getSubRegIndexNo(Record *idx); + + // Create a new sub-register index representing the A+B composition. + Record *getCompositeSubRegIndex(Record *A, Record *B); + }; } #endif Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=132849&r1=132848&r2=132849&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Fri Jun 10 13:40:00 2011 @@ -108,7 +108,8 @@ /// getTarget - Return the current instance of the Target class. /// -CodeGenTarget::CodeGenTarget(RecordKeeper &records) : Records(records) { +CodeGenTarget::CodeGenTarget(RecordKeeper &records) + : Records(records), RegBank(0) { std::vector Targets = Records.getAllDerivedDefinitions("Target"); if (Targets.size() == 0) throw std::string("ERROR: No 'Target' subclasses defined!"); @@ -156,6 +157,12 @@ return LI[AsmWriterNum]; } +CodeGenRegBank &CodeGenTarget::getRegBank() const { + if (!RegBank) + RegBank = new CodeGenRegBank(Records); + return *RegBank; +} + void CodeGenTarget::ReadRegisters() const { std::vector Regs = Records.getAllDerivedDefinitions("Register"); if (Regs.empty()) @@ -169,18 +176,6 @@ Registers[i].EnumValue = i + 1; } -void CodeGenTarget::ReadSubRegIndices() const { - SubRegIndices = Records.getAllDerivedDefinitions("SubRegIndex"); - std::sort(SubRegIndices.begin(), SubRegIndices.end(), LessRecord()); -} - -Record *CodeGenTarget::createSubRegIndex(const std::string &Name) { - Record *R = new Record(Name, SMLoc(), Records); - Records.addDef(R); - SubRegIndices.push_back(R); - return R; -} - void CodeGenTarget::ReadRegisterClasses() const { std::vector RegClasses = Records.getAllDerivedDefinitions("RegisterClass"); Modified: llvm/trunk/utils/TableGen/CodeGenTarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.h?rev=132849&r1=132848&r2=132849&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenTarget.h (original) +++ llvm/trunk/utils/TableGen/CodeGenTarget.h Fri Jun 10 13:40:00 2011 @@ -65,12 +65,11 @@ Record *TargetRec; mutable DenseMap Instructions; + mutable CodeGenRegBank *RegBank; mutable std::vector Registers; - mutable std::vector SubRegIndices; mutable std::vector RegisterClasses; mutable std::vector LegalValueTypes; void ReadRegisters() const; - void ReadSubRegIndices() const; void ReadRegisterClasses() const; void ReadInstructions() const; void ReadLegalValueTypes() const; @@ -98,6 +97,9 @@ /// Record *getAsmWriter() const; + /// getRegBank - Return the register bank description. + CodeGenRegBank &getRegBank() const; + const std::vector &getRegisters() const { if (Registers.empty()) ReadRegisters(); return Registers; @@ -107,23 +109,6 @@ /// return it. const CodeGenRegister *getRegisterByName(StringRef Name) const; - const std::vector &getSubRegIndices() const { - if (SubRegIndices.empty()) ReadSubRegIndices(); - return SubRegIndices; - } - - // Map a SubRegIndex Record to its number. - unsigned getSubRegIndexNo(Record *idx) const { - if (SubRegIndices.empty()) ReadSubRegIndices(); - std::vector::const_iterator i = - std::find(SubRegIndices.begin(), SubRegIndices.end(), idx); - assert(i != SubRegIndices.end() && "Not a SubRegIndex"); - return (i - SubRegIndices.begin()) + 1; - } - - // Create a new SubRegIndex with the given name. - Record *createSubRegIndex(const std::string &Name); - const std::vector &getRegisterClasses() const { if (RegisterClasses.empty()) ReadRegisterClasses(); return RegisterClasses; Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=132849&r1=132848&r2=132849&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Fri Jun 10 13:40:00 2011 @@ -26,6 +26,7 @@ // runEnums - Print out enum values for all of the registers. void RegisterInfoEmitter::runEnums(raw_ostream &OS) { CodeGenTarget Target(Records); + CodeGenRegBank &Bank = Target.getRegBank(); const std::vector &Registers = Target.getRegisters(); std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace"); @@ -47,14 +48,14 @@ if (!Namespace.empty()) OS << "}\n"; - const std::vector SubRegIndices = Target.getSubRegIndices(); + const std::vector &SubRegIndices = Bank.getSubRegIndices(); if (!SubRegIndices.empty()) { OS << "\n// Subregister indices\n"; Namespace = SubRegIndices[0]->getValueAsString("Namespace"); if (!Namespace.empty()) OS << "namespace " << Namespace << " {\n"; OS << "enum {\n NoSubRegister,\n"; - for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) + for (unsigned i = 0, e = Bank.getNumNamedIndices(); i != e; ++i) OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n"; OS << " NUM_TARGET_NAMED_SUBREGS = " << SubRegIndices.size()+1 << "\n"; OS << "};\n"; @@ -257,8 +258,8 @@ ++I) { Record *&Comp = Composite[I->second]; if (!Comp) - Comp = Target.createSubRegIndex(I->second.first->getName() + "_then_" + - I->second.second->getName()); + Comp = Target.getRegBank().getCompositeSubRegIndex(I->second.first, + I->second.second); SRM[Comp] = I->first; } @@ -338,6 +339,7 @@ // void RegisterInfoEmitter::run(raw_ostream &OS) { CodeGenTarget Target(Records); + CodeGenRegBank &RegBank = Target.getRegBank(); EmitSourceFileHeader("Register Information Source Fragment", OS); OS << "namespace llvm {\n\n"; @@ -404,7 +406,7 @@ std::map > SuperRegClassMap; OS << "\n"; - unsigned NumSubRegIndices = Target.getSubRegIndices().size(); + unsigned NumSubRegIndices = RegBank.getSubRegIndices().size(); if (NumSubRegIndices) { // Emit the sub-register classes for each RegisterClass @@ -415,7 +417,7 @@ i = RC.SubRegClasses.begin(), e = RC.SubRegClasses.end(); i != e; ++i) { // Build SRC array. - unsigned idx = Target.getSubRegIndexNo(i->first); + unsigned idx = RegBank.getSubRegIndexNo(i->first); SRC.at(idx-1) = i->second; // Find the register class number of i->second for SuperRegClassMap. @@ -863,13 +865,13 @@ // Calculate the mapping of subregister+index pairs to physical registers. // This will also create further anonymous indexes. - unsigned NamedIndices = Target.getSubRegIndices().size(); + unsigned NamedIndices = RegBank.getNumNamedIndices(); RegisterMaps RegMaps; for (unsigned i = 0, e = Regs.size(); i != e; ++i) RegMaps.inferSubRegIndices(Regs[i].TheDef, Target); // Emit SubRegIndex names, skipping 0 - const std::vector SubRegIndices = Target.getSubRegIndices(); + const std::vector &SubRegIndices = RegBank.getSubRegIndices(); OS << "\n const char *const SubRegIndexTable[] = { \""; for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { OS << SubRegIndices[i]->getName(); From mcrosier at apple.com Fri Jun 10 11:57:40 2011 From: mcrosier at apple.com (Chad Rosier) Date: Fri, 10 Jun 2011 11:57:40 -0700 Subject: [llvm-commits] [llvm] r132732 - /llvm/trunk/utils/TableGen/FastISelEmitter.cpp In-Reply-To: References: <20110607204132.03E232A6C12C@llvm.org> Message-ID: On Jun 10, 2011, at 11:22 AM, David Blaikie wrote: >> Just wondering about coding conventions - would it be more appropriate to change this from: >> else if (cond) { ... } else { /* unreachable */ } >> to: >> else { assert(cond); ... }; >> This would be marginally more efficient in release builds, potentially. >> > > You're correct in pointing out that most sanity checks should be written with asserts (e.g., assert (cond && "msg")). However, in the case of unreachable code we know that doom and gloom are sure to follow and thus we should gracefully abort and notify the user accordingly. There's no performance to be gained because if we've reached this state the game is already over. > > In general, if you see something like assert(0 && "I should have never gotten here.."); it should be replaced with llvm_unreachable("I should have never gotten here.."). Notice that the condition is hardcoded to zero and thus the assert will always fire. > > Right - but that's my point, there's performance to be gained by not at all checking 'cond' in retail builds - whereas the code as you have it now will check it unnecessarily & then go to llvm_unreachable if it's false. The perf gain would be that retail builds would never check the condition because it should never be false. That sounds like an assert to me, or am I missing something? > > Perhaps my example was oversimplified/unclear, what I meant was from this: > > } else if (Operands[i].isFP()) { > OS << "ConstantFP *f" << i; > } else { > llvm_unreachable("Unknown operand kind!"); > } > > to this: > > } else { > assert(Operands[i].isFP() && "Unknown operator kind!"); > OS << "ConstantFP *f" << i; > } Ahh.. yes, I misunderstood your example. Here are the source comments, which best explain the use of llvm_unreachable: /// Marks that the current location is not supposed to be reachable. /// In !NDEBUG builds, prints the message and location info to stderr. /// In NDEBUG builds, becomes an optimizer hint that the current location /// is not supposed to be reachable. On compilers that don't support /// such hints, prints a reduced message instead. /// /// Use this instead of assert(0). It conveys intent more clearly and /// allows compilers to omit some unnecessary code. In the case of a release build an unreachable hint is emitted. The compiler then uses this hint to transform: } else if (Operands[i].isFP()) { OS << "ConstantFP *f" << i; } else { llvm_unreachable("Unknown operand kind!"); } to: } else if (Operands[i].isFP()) { OS << "ConstantFP *f" << i; } I hope this helps answer your question. In the end the compiler is being smart about removing the unreachable code. For more details you could also checkout: http://www.nondot.org/sabre/LLVMNotes/UnreachableInstruction.txt Chad -------------- next part -------------- An HTML attachment was scrubbed... URL: From dblaikie at gmail.com Fri Jun 10 12:05:02 2011 From: dblaikie at gmail.com (David Blaikie) Date: Fri, 10 Jun 2011 12:05:02 -0700 Subject: [llvm-commits] [llvm] r132732 - /llvm/trunk/utils/TableGen/FastISelEmitter.cpp In-Reply-To: References: <20110607204132.03E232A6C12C@llvm.org> Message-ID: > > Ahh.. yes, I misunderstood your example. Here are the source comments, > which best explain the use of llvm_unreachable: > > */// Marks that the current location is not supposed to be reachable.**/// In !NDEBUG builds, prints the message and location info to stderr.**/// In NDEBUG builds, becomes an optimizer hint that the current location**/// is not supposed to be reachable. On compilers that don't support**/// such hints, prints a reduced message instead.**///**/// Use this instead of assert(0). It conveys intent more clearly and**/// allows compilers to omit some unnecessary code.* > > In the case of a release build an unreachable hint is emitted. The > compiler then uses this hint to transform: > > } else if (Operands[i].isFP()) { > OS << "ConstantFP *f" << i; > } else { > llvm_unreachable("Unknown operand kind!"); > } > > to: > > } else if (Operands[i].isFP()) { > OS << "ConstantFP *f" << i; > } > > I hope this helps answer your question. In the end the compiler is being > smart about removing the unreachable code. For more details you could also > checkout: http://www.nondot.org/sabre/LLVMNotes/UnreachableInstruction.txt > Ah, ok - thanks for the explanation. I didn't realize llvm_unreachable was that advanced/involved (though I suppose I Should've expected as much). So both versions (the assert & the unreachable) seem to have similar semantics (performance & correctness) given a sufficiently advanced compiler (that uses the unreachable to remove the isFP() call) - makes sense. [is there any policy/recommendations on which way to go in this case? I guess it's not a problem to leave this up to the author of any particular piece of LLVM code about which expression they prefer/find more clear in a given situation] Thanks again for the help, - David -------------- next part -------------- An HTML attachment was scrubbed... URL: From bob.wilson at apple.com Fri Jun 10 12:06:45 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Fri, 10 Jun 2011 12:06:45 -0700 Subject: [llvm-commits] [llvm] r132806 - /llvm/trunk/lib/CodeGen/TailDuplication.cpp In-Reply-To: <20110609214325.3D1EC2A6C12C@llvm.org> References: <20110609214325.3D1EC2A6C12C@llvm.org> Message-ID: On Jun 9, 2011, at 2:43 PM, Rafael Espindola wrote: > Author: rafael > Date: Thu Jun 9 16:43:25 2011 > New Revision: 132806 > > URL: http://llvm.org/viewvc/llvm-project?rev=132806&view=rev > Log: > AnalyzeBranch modifies the bb, but we don't want to modify a bb with > eh edges. Swap the order of the checks to avoid it. Maybe it would be better to call AnalyzeBranch with AllowModify=false? At least for the early tail-dup pass, I don't see why this code needs to let AnalyzeBranch modify the code. I doubt if the late tail-dup pass benefits much, either. One more comment below.... > > Modified: > llvm/trunk/lib/CodeGen/TailDuplication.cpp > > Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=132806&r1=132805&r2=132806&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original) > +++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Thu Jun 9 16:43:25 2011 > @@ -541,13 +541,13 @@ > > MachineBasicBlock *PredTBB, *PredFBB; > SmallVector PredCond; > + // EH edges are ignored by AnalyzeBranch. > + if (PredBB->succ_size() != 1) > + continue; > if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true)) > continue; > if (!PredCond.empty()) > continue; > - // EH edges are ignored by AnalyzeBranch. > - if (PredBB->succ_size() != 1) > - continue; > // Don't duplicate into a fall-through predecessor (at least for now). > if (PredBB->isLayoutSuccessor(TailBB) && PredBB->canFallThrough()) > continue; This is fine, but I think you can remove that check altogether. Just a few lines above, we have: assert(TailBB != PredBB && "Single-block loop should have been rejected earlier!"); if (PredBB->succ_size() > 1) continue; From mcrosier at apple.com Fri Jun 10 12:14:03 2011 From: mcrosier at apple.com (Chad Rosier) Date: Fri, 10 Jun 2011 12:14:03 -0700 Subject: [llvm-commits] [llvm] r132732 - /llvm/trunk/utils/TableGen/FastISelEmitter.cpp In-Reply-To: References: <20110607204132.03E232A6C12C@llvm.org> Message-ID: <35227283-0AB1-43C3-8C2C-170701BAC65D@apple.com> On Jun 10, 2011, at 12:05 PM, David Blaikie wrote: > Ahh.. yes, I misunderstood your example. Here are the source comments, which best explain the use of llvm_unreachable: > > /// Marks that the current location is not supposed to be reachable. > /// In !NDEBUG builds, prints the message and location info to stderr. > /// In NDEBUG builds, becomes an optimizer hint that the current location > /// is not supposed to be reachable. On compilers that don't support > /// such hints, prints a reduced message instead. > /// > /// Use this instead of assert(0). It conveys intent more clearly and > /// allows compilers to omit some unnecessary code. > In the case of a release build an unreachable hint is emitted. The compiler then uses this hint to transform: > > } else if (Operands[i].isFP()) { > OS << "ConstantFP *f" << i; > } else { > llvm_unreachable("Unknown operand kind!"); > } > > to: > > } else if (Operands[i].isFP()) { > OS << "ConstantFP *f" << i; > } > > I hope this helps answer your question. In the end the compiler is being smart about removing the unreachable code. For more details you could also checkout: http://www.nondot.org/sabre/LLVMNotes/UnreachableInstruction.txt > > Ah, ok - thanks for the explanation. I didn't realize llvm_unreachable was that advanced/involved (though I suppose I Should've expected as much). > > So both versions (the assert & the unreachable) seem to have similar semantics (performance & correctness) given a sufficiently advanced compiler (that uses the unreachable to remove the isFP() call) - makes sense. > > [is there any policy/recommendations on which way to go in this case? I guess it's not a problem to leave this up to the author of any particular piece of LLVM code about which expression they prefer/find more clear in a given situation] Like the comment says, llvm_unreachable() should be used in lieu of assert (0). Otherwise, assert (cond && "msg") should be used for code that is expected to execute. > Thanks again for the help, > - David > -------------- next part -------------- An HTML attachment was scrubbed... URL: From respindola at mozilla.com Fri Jun 10 12:16:45 2011 From: respindola at mozilla.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Fri, 10 Jun 2011 15:16:45 -0400 Subject: [llvm-commits] Enable early dup of any small bb Message-ID: <4DF26D9D.7050102@mozilla.com> My idea when I started working on PR10096 was to swap the responsibilities of early and late tail dup. The early one would duplicate small blocks and the late one would be the one responsible for duplicating the "large" blocks with indirectbr. Unfortunately, we cannot really depend only on the late pass to handle indirectbr. In the firefox case, gcc produces code that looks like movq (%rbx,%r12,8), %rax jmp *%rax clang changed to produce multiple indirectbr instructions produces jmpq *(%rsi,%rdx,8) and clang with only late tail dup (or when it gets lost in ra) produces leaq (%rax,%rcx,8), %rax jmpq *(%rax) So it looks like we really have to fix the taildup,phielim,ra interaction. The good news is that during benchmarking the options I found some bugs when early tail dup is enabled for bb without indirectbr in them. I fixed them an did some more benchmarking by just enabling it. I got some interesting results. The build time stayed the same, XUL 64 bits goes from 48745892 to 48735612 and firefox gets a bit faster 1550.87runs/s to 1627.12runs/s in dromaeo in a current build. I think the size reduction is because the blocks that we are duplicating early would be duplicated late anyway, we just have more passes to clean it up after us. Since this is just adding small blocks, the RA is still able to do a good job. In summary, is the attached patch OK? :-) Cheers, Rafael -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: dup.patch URL: From bob.wilson at apple.com Fri Jun 10 12:17:28 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Fri, 10 Jun 2011 12:17:28 -0700 Subject: [llvm-commits] [llvm] r132732 - /llvm/trunk/utils/TableGen/FastISelEmitter.cpp In-Reply-To: References: <20110607204132.03E232A6C12C@llvm.org> Message-ID: <02D447F1-7B51-40CB-AD91-97A97F369D95@apple.com> On Jun 10, 2011, at 12:05 PM, David Blaikie wrote: > Ah, ok - thanks for the explanation. I didn't realize llvm_unreachable was that advanced/involved (though I suppose I Should've expected as much). > > So both versions (the assert & the unreachable) seem to have similar semantics (performance & correctness) given a sufficiently advanced compiler (that uses the unreachable to remove the isFP() call) - makes sense. > > [is there any policy/recommendations on which way to go in this case? I guess it's not a problem to leave this up to the author of any particular piece of LLVM code about which expression they prefer/find more clear in a given situation] If I remember correctly, Chris has expressed a strong opinion to use assert instead of llvm_unreachable. I can't find the message where he said that, so hopefully I'm not misremembering. Maybe we should add something about that to the LLVM Coding Standards? I have noticed llvm_unreachable being used quite a bit lately, so I don't think the message is clear. From mcrosier at apple.com Fri Jun 10 12:22:23 2011 From: mcrosier at apple.com (Chad Rosier) Date: Fri, 10 Jun 2011 12:22:23 -0700 Subject: [llvm-commits] [llvm] r132732 - /llvm/trunk/utils/TableGen/FastISelEmitter.cpp In-Reply-To: <02D447F1-7B51-40CB-AD91-97A97F369D95@apple.com> References: <20110607204132.03E232A6C12C@llvm.org> <02D447F1-7B51-40CB-AD91-97A97F369D95@apple.com> Message-ID: On Jun 10, 2011, at 12:17 PM, Bob Wilson wrote: > > On Jun 10, 2011, at 12:05 PM, David Blaikie wrote: >> Ah, ok - thanks for the explanation. I didn't realize llvm_unreachable was that advanced/involved (though I suppose I Should've expected as much). >> >> So both versions (the assert & the unreachable) seem to have similar semantics (performance & correctness) given a sufficiently advanced compiler (that uses the unreachable to remove the isFP() call) - makes sense. >> >> [is there any policy/recommendations on which way to go in this case? I guess it's not a problem to leave this up to the author of any particular piece of LLVM code about which expression they prefer/find more clear in a given situation] > > If I remember correctly, Chris has expressed a strong opinion to use assert instead of llvm_unreachable. I can't find the message where he said that, so hopefully I'm not misremembering. > > Maybe we should add something about that to the LLVM Coding Standards? I have noticed llvm_unreachable being used quite a bit lately, so I don't think the message is clear. Admittedly, my reply is based on the recent trend Bob is referring too. From isanbard at gmail.com Fri Jun 10 12:20:28 2011 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 10 Jun 2011 19:20:28 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r132850 - /llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Message-ID: <20110610192028.2F8E02A6C12C@llvm.org> Author: void Date: Fri Jun 10 14:20:28 2011 New Revision: 132850 URL: http://llvm.org/viewvc/llvm-project?rev=132850&view=rev Log: Lower the MOVNT* variants to the appropriate native LLVM-IR equivalents. Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp?rev=132850&r1=132849&r2=132850&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Fri Jun 10 14:20:28 2011 @@ -445,6 +445,21 @@ Result = Builder.CreateCall(Func, CallOps, CallOps + 2); return true; } + case IX86_BUILTIN_MOVNTPS: + case IX86_BUILTIN_MOVNTPD: + case IX86_BUILTIN_MOVNTDQ: + case IX86_BUILTIN_MOVNTI: { + MDNode *Node = MDNode::get(Context, Builder.getInt32(1)); + + // Convert the type of the pointer to a pointer to the stored type. + Value *BC = Builder.CreateBitCast(Ops[0], + PointerType::getUnqual(Ops[1]->getType()), + "cast"); + StoreInst *SI = Builder.CreateStore(Ops[1], BC); + SI->setMetadata(TheModule->getMDKindID("nontemporal"), Node); + SI->setAlignment(16); + return SI; + } case IX86_BUILTIN_PALIGNR: { static const Type *MMXTy = Type::getX86_MMXTy(Context); Function *Func = Intrinsic::getDeclaration(TheModule, From bob.wilson at apple.com Fri Jun 10 12:46:59 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Fri, 10 Jun 2011 12:46:59 -0700 Subject: [llvm-commits] Enable early dup of any small bb In-Reply-To: <4DF26D9D.7050102@mozilla.com> References: <4DF26D9D.7050102@mozilla.com> Message-ID: We did some experiments of early tail dup when we first created the pass and found that it made almost no difference in performance for anything except indirect branches. Did you benchmark more than just firefox? If you're seeing cases where there is a significant benefit, and if there are no regressions in code size, code quality or build times, we could consider doing this. I'd like to see benchmark results across a fairly wide range of tests and on multiple targets before deciding that. In the longer term, I plan to add a separate "indirect branch duplication" pass, and I was hoping that could entirely replace the early tail-dup pass. The current tail duplication pass is not smart enough to do a good job for indirect branches. In order to get it to do what we need for indirect branches, we had to crank up the duplication limit fairly high, and then it blindly duplicates through multiple blocks, in some cases blowing up code size for no good reason. There are also cases where it fails because it cannot duplicate a block when a predecessor ends with a conditional branch. I haven't worked on that new pass for a while, but I wouldn't mind getting back to it, especially if you're seeing cases where it's needed. As you saw, tail dup for indirect branches has to happen before reg alloc to get good results. On Jun 10, 2011, at 12:16 PM, Rafael Ávila de Espíndola wrote: > My idea when I started working on PR10096 was to swap the responsibilities of early and late tail dup. The early one would duplicate small blocks and the late one would be the one responsible for duplicating the "large" blocks with indirectbr. > > Unfortunately, we cannot really depend only on the late pass to handle indirectbr. In the firefox case, gcc produces code that looks like > > movq (%rbx,%r12,8), %rax > > jmp *%rax > > clang changed to produce multiple indirectbr instructions produces > > jmpq *(%rsi,%rdx,8) > > and clang with only late tail dup (or when it gets lost in ra) produces > > leaq (%rax,%rcx,8), %rax > > jmpq *(%rax) > > So it looks like we really have to fix the taildup,phielim,ra interaction. > > The good news is that during benchmarking the options I found some bugs when early tail dup is enabled for bb without indirectbr in them. I fixed them an did some more benchmarking by just enabling it. > > I got some interesting results. The build time stayed the same, XUL 64 bits goes from 48745892 to 48735612 and firefox gets a bit faster 1550.87runs/s to 1627.12runs/s in dromaeo in a current build. > > I think the size reduction is because the blocks that we are duplicating early would be duplicated late anyway, we just have more passes to clean it up after us. Since this is just adding small blocks, the RA is still able to do a good job. > > In summary, is the attached patch OK? :-) > > Cheers, > Rafael > From respindola at mozilla.com Fri Jun 10 13:05:15 2011 From: respindola at mozilla.com (Rafael Avila de Espindola) Date: Fri, 10 Jun 2011 16:05:15 -0400 Subject: [llvm-commits] Enable early dup of any small bb In-Reply-To: References: <4DF26D9D.7050102@mozilla.com> Message-ID: <4DF278FB.3010902@mozilla.com> On 11-06-10 03:46 PM, Bob Wilson wrote: > We did some experiments of early tail dup when we first created the > pass and found that it made almost no difference in performance for > anything except indirect branches. Did you benchmark more than just > firefox? If you're seeing cases where there is a significant > benefit, and if there are no regressions in code size, code quality > or build times, we could consider doing this. I'd like to see > benchmark results across a fairly wide range of tests and on multiple > targets before deciding that. The only two easy tests I have at hand are firefox and clang iself. Would running the llvm-testsuite be a good measure? What kind of problems were you having with early dup before? In the cases I looked at the assembly, having an early dup with the same limit as the late one just cleans up the code a bit. It doesn't change a lot which blocks are duplicated, just when. Same idea for why it is good to duplicate indirectbr early, just not as dramatic. > In the longer term, I plan to add a separate "indirect branch > duplication" pass, and I was hoping that could entirely replace the > early tail-dup pass. The current tail duplication pass is not smart > enough to do a good job for indirect branches. In order to get it to > do what we need for indirect branches, we had to crank up the > duplication limit fairly high, and then it blindly duplicates through > multiple blocks, in some cases blowing up code size for no good > reason. There are also cases where it fails because it cannot > duplicate a block when a predecessor ends with a conditional branch. > I haven't worked on that new pass for a while, but I wouldn't mind > getting back to it, especially if you're seeing cases where it's > needed. The problem I have found have to do with the register allocator being unhappy with the output of early tail dup. As a test, I tried reducing the limit to the very minimum that would duplicate the original blocks and stop. It helped a bit, but the register allocator was still confused. Maybe in a case not as insane as jsinterp.o the decision of what to duplicate is more important. I guess the most important part is then not so much deciding what to duplicate, but doing a good job at it. I am still reducing a case where doing the duplication at clang produces better results than duplicating just before regalloc (1/2 as many spills). What were your plans for the indirectbr duplication pass? > As you saw, tail dup for indirect branches has to happen before reg > alloc to get good results. Indeed. Thanks, Rafael From dblaikie at gmail.com Fri Jun 10 13:07:16 2011 From: dblaikie at gmail.com (David Blaikie) Date: Fri, 10 Jun 2011 13:07:16 -0700 Subject: [llvm-commits] [llvm] r132732 - /llvm/trunk/utils/TableGen/FastISelEmitter.cpp In-Reply-To: <35227283-0AB1-43C3-8C2C-170701BAC65D@apple.com> References: <20110607204132.03E232A6C12C@llvm.org> <35227283-0AB1-43C3-8C2C-170701BAC65D@apple.com> Message-ID: > > Like the comment says, llvm_unreachable() should be used in lieu of assert > (0). Otherwise, assert (cond && "msg") should be used for code that is > expected to execute. > Right - but in this case the code could be either. It's not a question of assert(0) versus llvm_unreachable - in which case I'd favor the latter, certainly. It's a question of assert(cond && "msg") and (sort of) if (cond) { llvm_unreachable; } (it's not that simple - there's a difference in legibility between the two actual options, etc) - David -------------- next part -------------- An HTML attachment was scrubbed... URL: From rafael.espindola at gmail.com Fri Jun 10 13:08:23 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Fri, 10 Jun 2011 20:08:23 -0000 Subject: [llvm-commits] [llvm] r132851 - /llvm/trunk/lib/CodeGen/TailDuplication.cpp Message-ID: <20110610200823.917B32A6C12C@llvm.org> Author: rafael Date: Fri Jun 10 15:08:23 2011 New Revision: 132851 URL: http://llvm.org/viewvc/llvm-project?rev=132851&view=rev Log: Remove duplicated test. Thanks Bob Wilson for noticing it! Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=132851&r1=132850&r2=132851&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original) +++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Fri Jun 10 15:08:23 2011 @@ -573,13 +573,12 @@ assert(TailBB != PredBB && "Single-block loop should have been rejected earlier!"); - if (PredBB->succ_size() > 1) continue; + // EH edges are ignored by AnalyzeBranch. + if (PredBB->succ_size() > 1) + continue; MachineBasicBlock *PredTBB, *PredFBB; SmallVector PredCond; - // EH edges are ignored by AnalyzeBranch. - if (PredBB->succ_size() != 1) - continue; if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true)) continue; if (!PredCond.empty()) From rafael.espindola at gmail.com Fri Jun 10 13:15:10 2011 From: rafael.espindola at gmail.com (Rafael Avila de Espindola) Date: Fri, 10 Jun 2011 16:15:10 -0400 Subject: [llvm-commits] [llvm] r132806 - /llvm/trunk/lib/CodeGen/TailDuplication.cpp In-Reply-To: References: <20110609214325.3D1EC2A6C12C@llvm.org> Message-ID: <4DF27B4E.10705@gmail.com> > Maybe it would be better to call AnalyzeBranch with > AllowModify=false? At least for the early tail-dup pass, I don't see > why this code needs to let AnalyzeBranch modify the code. I doubt if > the late tail-dup pass benefits much, either. I considered that, but since it is removing some branches, I decided to fix the problem with as little change to the produced code as possible while benchmarking it. > One more comment below.... >> MachineBasicBlock *PredTBB, *PredFBB; SmallVector> 4> PredCond; + // EH edges are ignored by AnalyzeBranch. + >> if (PredBB->succ_size() != 1) + continue; if >> (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true)) >> continue; if (!PredCond.empty()) continue; - // EH edges are >> ignored by AnalyzeBranch. - if (PredBB->succ_size() != 1) - >> continue; // Don't duplicate into a fall-through predecessor (at >> least for now). if (PredBB->isLayoutSuccessor(TailBB)&& >> PredBB->canFallThrough()) continue; > > This is fine, but I think you can remove that check altogether. Just > a few lines above, we have: > > assert(TailBB != PredBB&& "Single-block loop should have been > rejected earlier!"); if (PredBB->succ_size()> 1) continue; > Fixed! Thanks, Rafael From zwarich at apple.com Fri Jun 10 13:30:08 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Fri, 10 Jun 2011 20:30:08 -0000 Subject: [llvm-commits] [llvm] r132852 - /llvm/trunk/lib/CodeGen/CallingConvLower.cpp Message-ID: <20110610203008.3D5B52A6C12C@llvm.org> Author: zwarich Date: Fri Jun 10 15:30:08 2011 New Revision: 132852 URL: http://llvm.org/viewvc/llvm-project?rev=132852&view=rev Log: Remove a pointless const_cast. Modified: llvm/trunk/lib/CodeGen/CallingConvLower.cpp Modified: llvm/trunk/lib/CodeGen/CallingConvLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CallingConvLower.cpp?rev=132852&r1=132851&r2=132852&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CallingConvLower.cpp (original) +++ llvm/trunk/lib/CodeGen/CallingConvLower.cpp Fri Jun 10 15:30:08 2011 @@ -51,7 +51,7 @@ Align = MinAlign; if (MF.getFrameInfo()->getMaxAlignment() < Align) MF.getFrameInfo()->setMaxAlignment(Align); - TM.getTargetLowering()->HandleByVal(const_cast(this), Size); + TM.getTargetLowering()->HandleByVal(this, Size); unsigned Offset = AllocateStack(Size, Align); addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); } From zwarich at apple.com Fri Jun 10 13:31:39 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Fri, 10 Jun 2011 20:31:39 -0000 Subject: [llvm-commits] [llvm] r132853 - in /llvm/trunk: include/llvm/CodeGen/CallingConvLower.h lib/CodeGen/CallingConvLower.cpp Message-ID: <20110610203139.3AE302A6C12C@llvm.org> Author: zwarich Date: Fri Jun 10 15:31:39 2011 New Revision: 132853 URL: http://llvm.org/viewvc/llvm-project?rev=132853&view=rev Log: Remove tabs. Modified: llvm/trunk/include/llvm/CodeGen/CallingConvLower.h llvm/trunk/lib/CodeGen/CallingConvLower.cpp Modified: llvm/trunk/include/llvm/CodeGen/CallingConvLower.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/CallingConvLower.h?rev=132853&r1=132852&r2=132853&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/CallingConvLower.h (original) +++ llvm/trunk/include/llvm/CodeGen/CallingConvLower.h Fri Jun 10 15:31:39 2011 @@ -163,8 +163,8 @@ ParmContext CallOrPrologue; public: CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF, - const TargetMachine &TM, - SmallVector &locs, LLVMContext &C); + const TargetMachine &TM, SmallVector &locs, + LLVMContext &C); void addLoc(const CCValAssign &V) { Locs.push_back(V); Modified: llvm/trunk/lib/CodeGen/CallingConvLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CallingConvLower.cpp?rev=132853&r1=132852&r2=132853&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CallingConvLower.cpp (original) +++ llvm/trunk/lib/CodeGen/CallingConvLower.cpp Fri Jun 10 15:31:39 2011 @@ -24,8 +24,8 @@ using namespace llvm; CCState::CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &mf, - const TargetMachine &tm, - SmallVector &locs, LLVMContext &C) + const TargetMachine &tm, SmallVector &locs, + LLVMContext &C) : CallingConv(CC), IsVarArg(isVarArg), MF(mf), TM(tm), TRI(*TM.getRegisterInfo()), Locs(locs), Context(C), CallOrPrologue(Invalid) { From bob.wilson at apple.com Fri Jun 10 13:40:00 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Fri, 10 Jun 2011 13:40:00 -0700 Subject: [llvm-commits] Enable early dup of any small bb In-Reply-To: <4DF278FB.3010902@mozilla.com> References: <4DF26D9D.7050102@mozilla.com> <4DF278FB.3010902@mozilla.com> Message-ID: <4097E3A2-F9A1-45D9-97B9-D82957AD2275@apple.com> On Jun 10, 2011, at 1:05 PM, Rafael Avila de Espindola wrote: > On 11-06-10 03:46 PM, Bob Wilson wrote: >> We did some experiments of early tail dup when we first created the >> pass and found that it made almost no difference in performance for >> anything except indirect branches. Did you benchmark more than just >> firefox? If you're seeing cases where there is a significant >> benefit, and if there are no regressions in code size, code quality >> or build times, we could consider doing this. I'd like to see >> benchmark results across a fairly wide range of tests and on multiple >> targets before deciding that. > > The only two easy tests I have at hand are firefox and clang iself. Would running the llvm-testsuite be a good measure? If the llvm-testsuite is all you've got, that would be a good start. We don't have enough real applications in the testsuite, but I don't know what else to suggest. > > What kind of problems were you having with early dup before? In the cases I looked at the assembly, having an early dup with the same limit as the late one just cleans up the code a bit. It doesn't change a lot which blocks are duplicated, just when. Same idea for why it is good to duplicate indirectbr early, just not as dramatic. We didn't have any problems with early tail dup. It just didn't make much difference in code quality and it has at least some negative effect on compile time. > >> In the longer term, I plan to add a separate "indirect branch >> duplication" pass, and I was hoping that could entirely replace the >> early tail-dup pass. The current tail duplication pass is not smart >> enough to do a good job for indirect branches. In order to get it to >> do what we need for indirect branches, we had to crank up the >> duplication limit fairly high, and then it blindly duplicates through >> multiple blocks, in some cases blowing up code size for no good >> reason. There are also cases where it fails because it cannot >> duplicate a block when a predecessor ends with a conditional branch. >> I haven't worked on that new pass for a while, but I wouldn't mind >> getting back to it, especially if you're seeing cases where it's >> needed. > > The problem I have found have to do with the register allocator being unhappy with the output of early tail dup. As a test, I tried reducing the limit to the very minimum that would duplicate the original blocks and stop. It helped a bit, but the register allocator was still confused. Maybe in a case not as insane as jsinterp.o the decision of what to duplicate is more important. Maybe I missed some things, but did you ever track down the root cause of the allocator's confusion? It seems like fixing the allocator would be the right thing to do here, regardless of whether we make other changes to tail dup. > > I guess the most important part is then not so much deciding what to duplicate, but doing a good job at it. I am still reducing a case where doing the duplication at clang produces better results than duplicating just before regalloc (1/2 as many spills). > > What were your plans for the indirectbr duplication pass? I'd basically like it to "undo" the front-end's merging of indirect branches. The idea I was working on duplicated regions of code, not just individual blocks, based on dominance info. Basically each successor of the indirect branch, corresponding to a "case" in a switch statement, dominates a region of code ending with one or more jumps back to the indirect branch, and we should try to duplicate one and only one copy of the indirect branch into each of those regions. From zwarich at apple.com Fri Jun 10 13:37:36 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Fri, 10 Jun 2011 20:37:36 -0000 Subject: [llvm-commits] [llvm] r132854 - in /llvm/trunk: include/llvm/CodeGen/CallingConvLower.h lib/CodeGen/CallingConvLower.cpp Message-ID: <20110610203736.CE46F2A6C12C@llvm.org> Author: zwarich Date: Fri Jun 10 15:37:36 2011 New Revision: 132854 URL: http://llvm.org/viewvc/llvm-project?rev=132854&view=rev Log: Rename the ParmContext enum values to make a bit more sense and add a small comment on their meaning. Modified: llvm/trunk/include/llvm/CodeGen/CallingConvLower.h llvm/trunk/lib/CodeGen/CallingConvLower.cpp Modified: llvm/trunk/include/llvm/CodeGen/CallingConvLower.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/CallingConvLower.h?rev=132854&r1=132853&r2=132854&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/CallingConvLower.h (original) +++ llvm/trunk/include/llvm/CodeGen/CallingConvLower.h Fri Jun 10 15:37:36 2011 @@ -142,7 +142,10 @@ MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State); -typedef enum { Invalid, Prologue, Call } ParmContext; +/// ParmContext - This enum tracks whether calling convention lowering is in +/// the context of prologue or call generation. Not all backends make use of +/// this information. +typedef enum { Unknown, Prologue, Call } ParmContext; /// CCState - This class holds information needed while lowering arguments and /// return values. It captures which registers are already assigned and which Modified: llvm/trunk/lib/CodeGen/CallingConvLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CallingConvLower.cpp?rev=132854&r1=132853&r2=132854&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CallingConvLower.cpp (original) +++ llvm/trunk/lib/CodeGen/CallingConvLower.cpp Fri Jun 10 15:37:36 2011 @@ -28,7 +28,7 @@ LLVMContext &C) : CallingConv(CC), IsVarArg(isVarArg), MF(mf), TM(tm), TRI(*TM.getRegisterInfo()), Locs(locs), Context(C), - CallOrPrologue(Invalid) { + CallOrPrologue(Unknown) { // No stack is used. StackOffset = 0; From bob.wilson at apple.com Fri Jun 10 13:48:46 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Fri, 10 Jun 2011 13:48:46 -0700 Subject: [llvm-commits] [llvm] r132805 - /llvm/trunk/lib/CodeGen/TailDuplication.cpp In-Reply-To: <20110609205542.172DC2A6C12C@llvm.org> References: <20110609205542.172DC2A6C12C@llvm.org> Message-ID: I'd really like to see a testcase for this, because I can't figure out how this could matter. We explicitly rule out tail-duplication for single-block loops, i.e., when the tail block is its own successor. You're checking here to exclude a PHI that uses a register defined in the same basic block, but wouldn't that always fail the single-block loop check? On Jun 9, 2011, at 1:55 PM, Rafael Espindola wrote: > Author: rafael > Date: Thu Jun 9 15:55:41 2011 > New Revision: 132805 > > URL: http://llvm.org/viewvc/llvm-project?rev=132805&view=rev > Log: > A PHI in this basic block is a use in another basic block. > > Modified: > llvm/trunk/lib/CodeGen/TailDuplication.cpp > > Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=132805&r1=132804&r2=132805&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original) > +++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Thu Jun 9 15:55:41 2011 > @@ -239,7 +239,7 @@ > MachineOperand &UseMO = UI.getOperand(); > MachineInstr *UseMI = &*UI; > ++UI; > - if (UseMI->getParent() == DefBB) > + if (UseMI->getParent() == DefBB && !UseMI->isPHI()) > continue; > SSAUpdate.RewriteUse(UseMO); > } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From bob.wilson at apple.com Fri Jun 10 13:51:18 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Fri, 10 Jun 2011 13:51:18 -0700 Subject: [llvm-commits] [llvm] r132805 - /llvm/trunk/lib/CodeGen/TailDuplication.cpp In-Reply-To: References: <20110609205542.172DC2A6C12C@llvm.org> Message-ID: <76AE2848-BA5E-4E57-95D9-AB67C1521935@apple.com> On Jun 10, 2011, at 1:48 PM, Bob Wilson wrote: > I'd really like to see a testcase for this, because I can't figure out how this could matter. > > We explicitly rule out tail-duplication for single-block loops, i.e., when the tail block is its own successor. You're checking here to exclude a PHI that uses a register defined in the same basic block, but wouldn't that always fail the single-block loop check? Oh wait, I guess it could go through an intermediate block. Nevermind. > > On Jun 9, 2011, at 1:55 PM, Rafael Espindola wrote: > >> Author: rafael >> Date: Thu Jun 9 15:55:41 2011 >> New Revision: 132805 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=132805&view=rev >> Log: >> A PHI in this basic block is a use in another basic block. >> >> Modified: >> llvm/trunk/lib/CodeGen/TailDuplication.cpp >> >> Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=132805&r1=132804&r2=132805&view=diff >> ============================================================================== >> --- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original) >> +++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Thu Jun 9 15:55:41 2011 >> @@ -239,7 +239,7 @@ >> MachineOperand &UseMO = UI.getOperand(); >> MachineInstr *UseMI = &*UI; >> ++UI; >> - if (UseMI->getParent() == DefBB) >> + if (UseMI->getParent() == DefBB && !UseMI->isPHI()) >> continue; >> SSAUpdate.RewriteUse(UseMO); >> } >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From bob.wilson at apple.com Fri Jun 10 13:53:43 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Fri, 10 Jun 2011 13:53:43 -0700 Subject: [llvm-commits] [llvm] r132814 - /llvm/trunk/lib/CodeGen/TailDuplication.cpp In-Reply-To: <20110609225348.233B32A6C12C@llvm.org> References: <20110609225348.233B32A6C12C@llvm.org> Message-ID: <827B6FAF-BFBC-4F5C-9E32-0E858BBA4DB2@apple.com> Please fix the tabs! Otherwise, this looks good. On Jun 9, 2011, at 3:53 PM, Rafael Espindola wrote: > Author: rafael > Date: Thu Jun 9 17:53:47 2011 > New Revision: 132814 > > URL: http://llvm.org/viewvc/llvm-project?rev=132814&view=rev > Log: > Also consider phi nodes when deciding if a register is live out. > > Modified: > llvm/trunk/lib/CodeGen/TailDuplication.cpp > > Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=132814&r1=132813&r2=132814&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original) > +++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Thu Jun 9 17:53:47 2011 > @@ -81,12 +81,14 @@ > void ProcessPHI(MachineInstr *MI, MachineBasicBlock *TailBB, > MachineBasicBlock *PredBB, > DenseMap &LocalVRMap, > - SmallVector, 4> &Copies); > + SmallVector, 4> &Copies, > + const DenseSet &UsedByPhi); > void DuplicateInstruction(MachineInstr *MI, > MachineBasicBlock *TailBB, > MachineBasicBlock *PredBB, > MachineFunction &MF, > - DenseMap &LocalVRMap); > + DenseMap &LocalVRMap, > + const DenseSet &UsedByPhi); > void UpdateSuccessorsPHIs(MachineBasicBlock *FromBB, bool isDead, > SmallVector &TDBBs, > SmallSetVector &Succs); > @@ -293,6 +295,24 @@ > return 0; > } > > + > +// Remember which registers are used by phis in this block. This is > +// used to determine which registers are liveout while modifying the > +// block (which is why we need to copy the information). > +static void getRegsUsedByPHIs(const MachineBasicBlock &BB, > + DenseSet *UsedByPhi) { > + for(MachineBasicBlock::const_iterator I = BB.begin(), E = BB.end(); > + I != E; ++I) { > + const MachineInstr &MI = *I; > + if (!MI.isPHI()) > + break; > + for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) { > + unsigned SrcReg = MI.getOperand(i).getReg(); > + UsedByPhi->insert(SrcReg); > + } > + } > +} > + > /// AddSSAUpdateEntry - Add a definition and source virtual registers pair for > /// SSA update. > void TailDuplicatePass::AddSSAUpdateEntry(unsigned OrigReg, unsigned NewReg, > @@ -315,7 +335,8 @@ > MachineBasicBlock *TailBB, > MachineBasicBlock *PredBB, > DenseMap &LocalVRMap, > - SmallVector, 4> &Copies) { > + SmallVector, 4> &Copies, > + const DenseSet &RegsUsedByPhi) { > unsigned DefReg = MI->getOperand(0).getReg(); > unsigned SrcOpIdx = getPHISrcRegOpIdx(MI, PredBB); > assert(SrcOpIdx && "Unable to find matching PHI source?"); > @@ -327,7 +348,7 @@ > // available value liveout of the block. > unsigned NewDef = MRI->createVirtualRegister(RC); > Copies.push_back(std::make_pair(NewDef, SrcReg)); > - if (isDefLiveOut(DefReg, TailBB, MRI)) > + if (isDefLiveOut(DefReg, TailBB, MRI) || RegsUsedByPhi.count(DefReg)) > AddSSAUpdateEntry(DefReg, NewDef, PredBB); > > // Remove PredBB from the PHI node. > @@ -343,7 +364,8 @@ > MachineBasicBlock *TailBB, > MachineBasicBlock *PredBB, > MachineFunction &MF, > - DenseMap &LocalVRMap) { > + DenseMap &LocalVRMap, > + const DenseSet &UsedByPhi) { > MachineInstr *NewMI = TII->duplicate(MI, MF); > for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) { > MachineOperand &MO = NewMI->getOperand(i); > @@ -357,7 +379,7 @@ > unsigned NewReg = MRI->createVirtualRegister(RC); > MO.setReg(NewReg); > LocalVRMap.insert(std::make_pair(Reg, NewReg)); > - if (isDefLiveOut(Reg, TailBB, MRI)) > + if (isDefLiveOut(Reg, TailBB, MRI) || UsedByPhi.count(Reg)) > AddSSAUpdateEntry(Reg, NewReg, PredBB); > } else { > DenseMap::iterator VI = LocalVRMap.find(Reg); > @@ -531,6 +553,8 @@ > bool Changed = false; > SmallSetVector Preds(TailBB->pred_begin(), > TailBB->pred_end()); > + DenseSet UsedByPhi; > + getRegsUsedByPHIs(*TailBB, &UsedByPhi); > for (SmallSetVector::iterator PI = Preds.begin(), > PE = Preds.end(); PI != PE; ++PI) { > MachineBasicBlock *PredBB = *PI; > @@ -570,11 +594,11 @@ > if (MI->isPHI()) { > // Replace the uses of the def of the PHI with the register coming > // from PredBB. > - ProcessPHI(MI, TailBB, PredBB, LocalVRMap, CopyInfos); > + ProcessPHI(MI, TailBB, PredBB, LocalVRMap, CopyInfos, UsedByPhi); > } else { > // Replace def of virtual registers with new registers, and update > // uses with PHI source register or the new registers. > - DuplicateInstruction(MI, TailBB, PredBB, MF, LocalVRMap); > + DuplicateInstruction(MI, TailBB, PredBB, MF, LocalVRMap, UsedByPhi); > } > } > MachineBasicBlock::iterator Loc = PredBB->getFirstTerminator(); > @@ -620,7 +644,7 @@ > // Replace the uses of the def of the PHI with the register coming > // from PredBB. > MachineInstr *MI = &*I++; > - ProcessPHI(MI, TailBB, PrevBB, LocalVRMap, CopyInfos); > + ProcessPHI(MI, TailBB, PrevBB, LocalVRMap, CopyInfos, UsedByPhi); > if (MI->getParent()) > MI->eraseFromParent(); > } > @@ -630,7 +654,7 @@ > // Replace def of virtual registers with new registers, and update > // uses with PHI source register or the new registers. > MachineInstr *MI = &*I++; > - DuplicateInstruction(MI, TailBB, PrevBB, MF, LocalVRMap); > + DuplicateInstruction(MI, TailBB, PrevBB, MF, LocalVRMap, UsedByPhi); > MI->eraseFromParent(); > } > MachineBasicBlock::iterator Loc = PrevBB->getFirstTerminator(); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From respindola at mozilla.com Fri Jun 10 13:57:04 2011 From: respindola at mozilla.com (Rafael Avila de Espindola) Date: Fri, 10 Jun 2011 16:57:04 -0400 Subject: [llvm-commits] Enable early dup of any small bb In-Reply-To: <4097E3A2-F9A1-45D9-97B9-D82957AD2275@apple.com> References: <4DF26D9D.7050102@mozilla.com> <4DF278FB.3010902@mozilla.com> <4097E3A2-F9A1-45D9-97B9-D82957AD2275@apple.com> Message-ID: <4DF28520.9070300@mozilla.com> > If the llvm-testsuite is all you've got, that would be a good start. > We don't have enough real applications in the testsuite, but I don't > know what else to suggest. I will give that and clang itself a try. >> The problem I have found have to do with the register allocator >> being unhappy with the output of early tail dup. As a test, I tried >> reducing the limit to the very minimum that would duplicate the >> original blocks and stop. It helped a bit, but the register >> allocator was still confused. Maybe in a case not as insane as >> jsinterp.o the decision of what to duplicate is more important. > > Maybe I missed some things, but did you ever track down the root > cause of the allocator's confusion? It seems like fixing the > allocator would be the right thing to do here, regardless of whether > we make other changes to tail dup. I haven't found what is confusing the register allocator (or phielim) yet. I started looking at this as a short time solution, but found that, in jsinterp.o at least, the minimum necessary duplication already breaks ra. Finding that enabling early dup of small blocks helps code size and performance a bit was a happy accident. >> What were your plans for the indirectbr duplication pass? > > I'd basically like it to "undo" the front-end's merging of indirect > branches. The idea I was working on duplicated regions of code, not > just individual blocks, based on dominance info. Basically each > successor of the indirect branch, corresponding to a "case" in a > switch statement, dominates a region of code ending with one or more > jumps back to the indirect branch, and we should try to duplicate one > and only one copy of the indirect branch into each of those regions. I would be happy to beta test it once I am able to make RA happy with the extra duplicated blocks :-) Cheers, Rafael From zwarich at apple.com Fri Jun 10 13:59:24 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Fri, 10 Jun 2011 20:59:24 -0000 Subject: [llvm-commits] [llvm] r132856 - in /llvm/trunk: include/llvm/CodeGen/CallingConvLower.h lib/Target/ARM/ARMISelLowering.cpp Message-ID: <20110610205924.9372C2A6C12C@llvm.org> Author: zwarich Date: Fri Jun 10 15:59:24 2011 New Revision: 132856 URL: http://llvm.org/viewvc/llvm-project?rev=132856&view=rev Log: Provide an ARMCCState subclass of CCState so that ARM clients will always set CallOrPrologue correctly and eliminate the existing setter. Modified: llvm/trunk/include/llvm/CodeGen/CallingConvLower.h llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Modified: llvm/trunk/include/llvm/CodeGen/CallingConvLower.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/CallingConvLower.h?rev=132856&r1=132855&r2=132856&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/CallingConvLower.h (original) +++ llvm/trunk/include/llvm/CodeGen/CallingConvLower.h Fri Jun 10 15:59:24 2011 @@ -151,6 +151,7 @@ /// return values. It captures which registers are already assigned and which /// stack slots are used. It provides accessors to allocate these values. class CCState { +private: CallingConv::ID CallingConv; bool IsVarArg; MachineFunction &MF; @@ -163,7 +164,10 @@ SmallVector UsedRegs; unsigned FirstByValReg; bool FirstByValRegValid; + +protected: ParmContext CallOrPrologue; + public: CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF, const TargetMachine &TM, SmallVector &locs, @@ -308,7 +312,6 @@ bool isFirstByValRegValid() { return FirstByValRegValid; } ParmContext getCallOrPrologue() { return CallOrPrologue; } - void setCallOrPrologue(ParmContext pc) { CallOrPrologue = pc; } private: /// MarkAllocated - Mark a register and all of its aliases as allocated. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=132856&r1=132855&r2=132856&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Jun 10 15:59:24 2011 @@ -72,6 +72,21 @@ cl::desc("Enable / disable ARM interworking (for debugging only)"), cl::init(true)); +namespace llvm { + class ARMCCState : public CCState { + public: + ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF, + const TargetMachine &TM, SmallVector &locs, + LLVMContext &C, ParmContext PC) + : CCState(CC, isVarArg, MF, TM, locs, C) { + assert(((PC == Call) || (PC == Prologue)) && + "ARMCCState users must specify whether their context is call" + "or prologue generation."); + CallOrPrologue = PC; + } + }; +} + // The APCS parameter registers. static const unsigned GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 @@ -1071,8 +1086,8 @@ // Assign locations to each value returned by this call. SmallVector RVLocs; - CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), - getTargetMachine(), RVLocs, *DAG.getContext()); + ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), RVLocs, *DAG.getContext(), Call); CCInfo.AnalyzeCallResult(Ins, CCAssignFnForNode(CallConv, /* Return*/ true, isVarArg)); @@ -1206,9 +1221,8 @@ // Analyze operands of the call, assigning locations to each operand. SmallVector ArgLocs; - CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), - getTargetMachine(), ArgLocs, *DAG.getContext()); - CCInfo.setCallOrPrologue(Call); + ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), ArgLocs, *DAG.getContext(), Call); CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv, /* Return*/ false, isVarArg)); @@ -1638,13 +1652,13 @@ // results are returned in the same way as what the caller expects. if (!CCMatch) { SmallVector RVLocs1; - CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), - getTargetMachine(), RVLocs1, *DAG.getContext()); + ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), + getTargetMachine(), RVLocs1, *DAG.getContext(), Call); CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg)); SmallVector RVLocs2; - CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), - getTargetMachine(), RVLocs2, *DAG.getContext()); + ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), + getTargetMachine(), RVLocs2, *DAG.getContext(), Call); CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg)); if (RVLocs1.size() != RVLocs2.size()) @@ -1670,9 +1684,8 @@ // Check if stack adjustment is needed. For now, do not do this if any // argument is passed on the stack. SmallVector ArgLocs; - CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), - getTargetMachine(), ArgLocs, *DAG.getContext()); - CCInfo.setCallOrPrologue(Call); + ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), ArgLocs, *DAG.getContext(), Call); CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC, false, isVarArg)); if (CCInfo.getNextStackOffset()) { @@ -1731,8 +1744,8 @@ SmallVector RVLocs; // CCState - Info about the registers and stack slots. - CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), - getTargetMachine(), RVLocs, *DAG.getContext()); + ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), RVLocs, *DAG.getContext(), Call); // Analyze outgoing return values. CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true, @@ -2425,9 +2438,8 @@ // Assign locations to all of the incoming arguments. SmallVector ArgLocs; - CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), - getTargetMachine(), ArgLocs, *DAG.getContext()); - CCInfo.setCallOrPrologue(Prologue); + ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), + getTargetMachine(), ArgLocs, *DAG.getContext(), Prologue); CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv, /* Return*/ false, isVarArg)); From rafael.espindola at gmail.com Fri Jun 10 14:01:53 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Fri, 10 Jun 2011 21:01:53 -0000 Subject: [llvm-commits] [llvm] r132857 - /llvm/trunk/lib/CodeGen/TailDuplication.cpp Message-ID: <20110610210153.C20882A6C12C@llvm.org> Author: rafael Date: Fri Jun 10 16:01:53 2011 New Revision: 132857 URL: http://llvm.org/viewvc/llvm-project?rev=132857&view=rev Log: Removed tabs. Also fixed my editor... Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=132857&r1=132856&r2=132857&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original) +++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Fri Jun 10 16:01:53 2011 @@ -301,7 +301,7 @@ // used to determine which registers are liveout while modifying the // block (which is why we need to copy the information). static void getRegsUsedByPHIs(const MachineBasicBlock &BB, - DenseSet *UsedByPhi) { + DenseSet *UsedByPhi) { for(MachineBasicBlock::const_iterator I = BB.begin(), E = BB.end(); I != E; ++I) { const MachineInstr &MI = *I; @@ -337,7 +337,7 @@ MachineBasicBlock *PredBB, DenseMap &LocalVRMap, SmallVector, 4> &Copies, - const DenseSet &RegsUsedByPhi, + const DenseSet &RegsUsedByPhi, bool Remove) { unsigned DefReg = MI->getOperand(0).getReg(); unsigned SrcOpIdx = getPHISrcRegOpIdx(MI, PredBB); @@ -753,4 +753,3 @@ // Remove the block. MBB->eraseFromParent(); } - From aggarwa4 at illinois.edu Fri Jun 10 14:23:35 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Fri, 10 Jun 2011 21:23:35 -0000 Subject: [llvm-commits] [poolalloc] r132858 - /poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Message-ID: <20110610212335.BE14E2A6C12C@llvm.org> Author: aggarwa4 Date: Fri Jun 10 16:23:35 2011 New Revision: 132858 URL: http://llvm.org/viewvc/llvm-project?rev=132858&view=rev Log: Do not replace uses where the function is passed to external functions as argument. Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=132858&r1=132857&r2=132858&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Fri Jun 10 16:23:35 2011 @@ -366,6 +366,10 @@ continue; } } + if(CallInst *CI = dyn_cast(user)) { + if(CI->getCalledFunction()->isDeclaration()) + continue; + } user->replaceUsesOfWith(F, CNew); } } From aggarwa4 at illinois.edu Fri Jun 10 14:25:12 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Fri, 10 Jun 2011 21:25:12 -0000 Subject: [llvm-commits] [poolalloc] r132859 - in /poolalloc/trunk: include/assistDS/FuncSimplify.h lib/AssistDS/FuncSimplify.cpp Message-ID: <20110610212512.8B8AA2A6C12C@llvm.org> Author: aggarwa4 Date: Fri Jun 10 16:25:12 2011 New Revision: 132859 URL: http://llvm.org/viewvc/llvm-project?rev=132859&view=rev Log: Replace all uses of aliases with the aliasee values. Added: poolalloc/trunk/include/assistDS/FuncSimplify.h poolalloc/trunk/lib/AssistDS/FuncSimplify.cpp Added: poolalloc/trunk/include/assistDS/FuncSimplify.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/FuncSimplify.h?rev=132859&view=auto ============================================================================== --- poolalloc/trunk/include/assistDS/FuncSimplify.h (added) +++ poolalloc/trunk/include/assistDS/FuncSimplify.h Fri Jun 10 16:25:12 2011 @@ -0,0 +1,30 @@ +//===-------- ArgCast.cpp - Cast Arguments to Calls -----------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// + +#include "llvm/Instructions.h" +#include "llvm/Module.h" +#include "llvm/Pass.h" + +namespace llvm { + // + // Class: FuncSimplify + // + // Description: + // Replace all internal aliases with the + // aliasee value + // + class FuncSimplify : public ModulePass { + public: + static char ID; + FuncSimplify() : ModulePass(&ID) {} + virtual bool runOnModule(Module& M); + }; +} + Added: poolalloc/trunk/lib/AssistDS/FuncSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/FuncSimplify.cpp?rev=132859&view=auto ============================================================================== --- poolalloc/trunk/lib/AssistDS/FuncSimplify.cpp (added) +++ poolalloc/trunk/lib/AssistDS/FuncSimplify.cpp Fri Jun 10 16:25:12 2011 @@ -0,0 +1,72 @@ +//===-------- FuncSimplify.cpp - Replace Global Aliases -------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// +#define DEBUG_TYPE "func-simplify" + +#include "assistDS/FuncSimplify.h" +#include "llvm/Attributes.h" +#include "llvm/Transforms/Utils/Cloning.h" +#include "llvm/ADT/Statistic.h" +#include "llvm/Support/FormattedStream.h" +#include "llvm/Support/Debug.h" + +#include +#include +#include + +using namespace llvm; + +// Pass statistics +STATISTIC(numChanged, "Number of aliases deleted"); + +// +// Method: runOnModule() +// +// Description: +// Entry point for this LLVM pass. +// Replace all internal aliases with the +// aliasee value +// +// Inputs: +// M - A reference to the LLVM module to transform +// +// Outputs: +// M - The transformed LLVM module. +// +// Return value: +// true - The module was modified. +// false - The module was not modified. +// +bool FuncSimplify::runOnModule(Module& M) { + + std::vector toDelete; + for (Module::alias_iterator I = M.alias_begin(); I != M.alias_end(); ++I) { + if(!I->hasInternalLinkage()) + continue; + I->replaceAllUsesWith(I->getAliasee()); + toDelete.push_back(I); + } + numChanged += toDelete.size(); + + while(!toDelete.empty()) { + GlobalAlias *I = toDelete.back(); + toDelete.pop_back(); + I->eraseFromParent(); + } + + + return true; +} + +// Pass ID variable +char FuncSimplify::ID = 0; + +// Register the pass +static RegisterPass +X("func-simplify", "Delete Aliases"); From isanbard at gmail.com Fri Jun 10 14:47:14 2011 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 10 Jun 2011 21:47:14 -0000 Subject: [llvm-commits] [llvm] r132860 - /llvm/trunk/Makefile Message-ID: <20110610214714.DB7212A6C12C@llvm.org> Author: void Date: Fri Jun 10 16:47:14 2011 New Revision: 132860 URL: http://llvm.org/viewvc/llvm-project?rev=132860&view=rev Log: Install libprofile_rt.dylib where it's more available for gcov support. Modified: llvm/trunk/Makefile Modified: llvm/trunk/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile?rev=132860&r1=132859&r2=132860&view=diff ============================================================================== --- llvm/trunk/Makefile (original) +++ llvm/trunk/Makefile Fri Jun 10 16:47:14 2011 @@ -69,7 +69,7 @@ ifeq ($(MAKECMDGOALS),install-clang) DIRS := tools/clang/tools/driver tools/clang/lib/Headers \ tools/clang/runtime tools/clang/docs \ - tools/lto + tools/lto runtime OPTIONAL_DIRS := NO_INSTALL = 1 endif @@ -83,7 +83,7 @@ endif ifeq ($(MAKECMDGOALS),clang-only) - DIRS := $(filter-out tools runtime docs unittests, $(DIRS)) \ + DIRS := $(filter-out tools docs unittests, $(DIRS)) \ tools/clang tools/lto OPTIONAL_DIRS := endif From gohman at apple.com Fri Jun 10 15:30:30 2011 From: gohman at apple.com (Dan Gohman) Date: Fri, 10 Jun 2011 22:30:30 -0000 Subject: [llvm-commits] [llvm] r132862 - /llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Message-ID: <20110610223030.F2BF82A6C12C@llvm.org> Author: djg Date: Fri Jun 10 17:30:30 2011 New Revision: 132862 URL: http://llvm.org/viewvc/llvm-project?rev=132862&view=rev Log: Initialize BasicAA's AliasCache to set it to use fewer buckets by default, since it usually has very few elements. This speeds up alias queries in many cases, because AliasCache.clear() doesn't have to visit as many buckets. Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=132862&r1=132861&r2=132862&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Fri Jun 10 17:30:30 2011 @@ -451,7 +451,13 @@ /// BasicAliasAnalysis - This is the primary alias analysis implementation. struct BasicAliasAnalysis : public ImmutablePass, public AliasAnalysis { static char ID; // Class identification, replacement for typeinfo - BasicAliasAnalysis() : ImmutablePass(ID) { + BasicAliasAnalysis() : ImmutablePass(ID), + // AliasCache rarely has more than 1 or 2 elements, + // so start it off fairly small so that clear() + // doesn't have to tromp through 64 (the default) + // elements on each alias query. This really wants + // something like a SmallDenseMap. + AliasCache(8) { initializeBasicAliasAnalysisPass(*PassRegistry::getPassRegistry()); } From echristo at apple.com Fri Jun 10 16:05:08 2011 From: echristo at apple.com (Eric Christopher) Date: Fri, 10 Jun 2011 23:05:08 -0000 Subject: [llvm-commits] [llvm] r132863 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Message-ID: <20110610230508.D45472A6C12C@llvm.org> Author: echristo Date: Fri Jun 10 18:05:08 2011 New Revision: 132863 URL: http://llvm.org/viewvc/llvm-project?rev=132863&view=rev Log: 80-col cleanups. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=132863&r1=132862&r2=132863&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Fri Jun 10 18:05:08 2011 @@ -573,9 +573,9 @@ DebugLoc DL = N->getDebugLoc(); EVT SmallVT = LHS.getValueType(); - // To determine if the result overflowed in a larger type, we extend the input - // to the larger type, do the multiply, then check the high bits of the result - // to see if the overflow happened. + // To determine if the result overflowed in a larger type, we extend the + // input to the larger type, do the multiply, then check the high bits of + // the result to see if the overflow happened. if (N->getOpcode() == ISD::SMULO) { LHS = SExtPromotedInteger(LHS); RHS = SExtPromotedInteger(RHS); @@ -585,8 +585,8 @@ } SDValue Mul = DAG.getNode(ISD::MUL, DL, LHS.getValueType(), LHS, RHS); - // Overflow occurred iff the high part of the result does not zero/sign-extend - // the low part. + // Overflow occurred iff the high part of the result does not + // zero/sign-extend the low part. SDValue Overflow; if (N->getOpcode() == ISD::UMULO) { // Unsigned overflow occurred iff the high part is non-zero. @@ -2789,4 +2789,3 @@ return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0), &NewOps[0], NewOps.size()); } - From eli.friedman at gmail.com Fri Jun 10 16:39:36 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Fri, 10 Jun 2011 23:39:36 -0000 Subject: [llvm-commits] [llvm] r132864 - in /llvm/trunk: lib/Target/X86/X86FastISel.cpp test/CodeGen/X86/fast-isel-call.ll Message-ID: <20110610233936.4B9222A6C12C@llvm.org> Author: efriedma Date: Fri Jun 10 18:39:36 2011 New Revision: 132864 URL: http://llvm.org/viewvc/llvm-project?rev=132864&view=rev Log: Add full x86 fast-isel support for memcpy and memset. rdar://9431466 Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp llvm/trunk/test/CodeGen/X86/fast-isel-call.ll Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=132864&r1=132863&r2=132864&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Fri Jun 10 18:39:36 2011 @@ -111,6 +111,8 @@ bool X86VisitIntrinsicCall(const IntrinsicInst &I); bool X86SelectCall(const Instruction *I); + bool DoSelectCall(const Instruction *I, const char *MemIntName); + const X86InstrInfo *getInstrInfo() const { return getTargetMachine()->getInstrInfo(); } @@ -1333,20 +1335,44 @@ case Intrinsic::memcpy: { const MemCpyInst &MCI = cast(I); // Don't handle volatile or variable length memcpys. - if (MCI.isVolatile() || !isa(MCI.getLength())) + if (MCI.isVolatile()) return false; - uint64_t Len = cast(MCI.getLength())->getZExtValue(); + if (isa(MCI.getLength())) { + // Small memcpy's are common enough that we want to do them + // without a call if possible. + uint64_t Len = cast(MCI.getLength())->getZExtValue(); + if (IsMemcpySmall(Len)) { + X86AddressMode DestAM, SrcAM; + if (!X86SelectAddress(MCI.getRawDest(), DestAM) || + !X86SelectAddress(MCI.getRawSource(), SrcAM)) + return false; + TryEmitSmallMemcpy(DestAM, SrcAM, Len); + return true; + } + } + + unsigned SizeWidth = Subtarget->is64Bit() ? 64 : 32; + if (!MCI.getLength()->getType()->isIntegerTy(SizeWidth)) + return false; - // Get the address of the dest and source addresses. - X86AddressMode DestAM, SrcAM; - if (!X86SelectAddress(MCI.getRawDest(), DestAM) || - !X86SelectAddress(MCI.getRawSource(), SrcAM)) + if (MCI.getSourceAddressSpace() > 255 || MCI.getDestAddressSpace() > 255) return false; - return TryEmitSmallMemcpy(DestAM, SrcAM, Len); + return DoSelectCall(&I, "memcpy"); } + case Intrinsic::memset: { + const MemSetInst &MSI = cast(I); + + unsigned SizeWidth = Subtarget->is64Bit() ? 64 : 32; + if (!MSI.getLength()->getType()->isIntegerTy(SizeWidth)) + return false; + + if (MSI.getDestAddressSpace() > 255) + return false; + return DoSelectCall(&I, "memset"); + } case Intrinsic::stackprotector: { // Emit code inline code to store the stack guard onto the stack. EVT PtrTy = TLI.getPointerTy(); @@ -1437,6 +1463,14 @@ if (const IntrinsicInst *II = dyn_cast(CI)) return X86VisitIntrinsicCall(*II); + return DoSelectCall(I, 0); +} + +// Select either a call, or an llvm.memcpy/memmove/memset intrinsic +bool X86FastISel::DoSelectCall(const Instruction *I, const char *MemIntName) { + const CallInst *CI = cast(I); + const Value *Callee = CI->getCalledValue(); + // Handle only C and fastcc calling conventions for now. ImmutableCallSite CS(CI); CallingConv::ID CC = CS.getCallingConv(); @@ -1498,6 +1532,10 @@ ArgFlags.reserve(CS.arg_size()); for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); i != e; ++i) { + // If we're lowering a mem intrinsic instead of a regular call, skip the + // last two arguments, which should not passed to the underlying functions. + if (MemIntName && e-i <= 2) + break; Value *ArgVal = *i; ISD::ArgFlagsTy Flags; unsigned AttrInd = i - CS.arg_begin() + 1; @@ -1744,8 +1782,11 @@ } - MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc)) - .addGlobalAddress(GV, 0, OpFlags); + MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc)); + if (MemIntName) + MIB.addExternalSymbol(MemIntName); + else + MIB.addGlobalAddress(GV, 0, OpFlags); } // Add an implicit use GOT pointer in EBX. Modified: llvm/trunk/test/CodeGen/X86/fast-isel-call.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-call.ll?rev=132864&r1=132863&r2=132864&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fast-isel-call.ll (original) +++ llvm/trunk/test/CodeGen/X86/fast-isel-call.ll Fri Jun 10 18:39:36 2011 @@ -29,3 +29,27 @@ ; CHECK: movl 8(%eax) ; CHECK: movl {{.*}}, 8(%esp) } + +declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind + +define void @test3(i8* %a) { + call void @llvm.memset.p0i8.i32(i8* %a, i8 0, i32 100, i32 1, i1 false) + ret void +; CHECK: test3: +; CHECK: movl {{.*}}, (%esp) +; CHECK: movl $0, 4(%esp) +; CHECK: movl $100, 8(%esp) +; CHECK: calll {{.*}}memset +} + +declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind + +define void @test4(i8* %a, i8* %b) { + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %a, i8* %b, i32 100, i32 1, i1 false) + ret void +; CHECK: test4: +; CHECK: movl {{.*}}, (%esp) +; CHECK: movl {{.*}}, 4(%esp) +; CHECK: movl $100, 8(%esp) +; CHECK: calll {{.*}}memcpy +} From dpatel at apple.com Fri Jun 10 17:32:45 2011 From: dpatel at apple.com (Devang Patel) Date: Fri, 10 Jun 2011 17:32:45 -0700 Subject: [llvm-commits] [llvm] r132797 - in /llvm/trunk: include/llvm/Analysis/CallGraph.h lib/Analysis/IPA/CallGraph.cpp lib/Analysis/IPA/CallGraphSCCPass.cpp lib/Transforms/Utils/InlineFunction.cpp In-Reply-To: <20110609194627.D56E42A6C12C@llvm.org> References: <20110609194627.D56E42A6C12C@llvm.org> Message-ID: On Jun 9, 2011, at 12:46 PM, John McCall wrote: > @@ -547,15 +535,7 @@ > ConstantInt::get(Type::getInt32Ty(Context), 1), > ConstantInt::getFalse(Context) // isVolatile > }; > - CallInst *TheMemCpy = > - CallInst::Create(MemCpyFn, CallArgs, CallArgs+5, "", TheCall); > - > - // If we have a call graph, update it. > - if (CallGraph *CG = IFI.CG) { > - CallGraphNode *MemCpyCGN = CG->getOrInsertFunction(MemCpyFn); > - CallGraphNode *CallerNode = (*CG)[Caller]; > - CallerNode->addCalledFunction(TheMemCpy, MemCpyCGN); > - } > + CallInst::Create(MemCpyFn, CallArgs, CallArgs+5, "", TheCall); Please use IRBuilder so that we can have appropriate line number information attached with new instruction. - Devang From stoklund at 2pi.dk Fri Jun 10 17:28:06 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Sat, 11 Jun 2011 00:28:06 -0000 Subject: [llvm-commits] [llvm] r132865 - in /llvm/trunk/utils/TableGen: CodeGenRegisters.cpp CodeGenRegisters.h CodeGenTarget.cpp CodeGenTarget.h RegisterInfoEmitter.cpp Message-ID: <20110611002806.3FB122A6C12C@llvm.org> Author: stoklund Date: Fri Jun 10 19:28:06 2011 New Revision: 132865 URL: http://llvm.org/viewvc/llvm-project?rev=132865&view=rev Log: Move the list of registers into CodeGenRegBank. Also move the sub-register index computations from RegisterInfoEmitter into CodeGenRegBank. Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.cpp llvm/trunk/utils/TableGen/CodeGenRegisters.h llvm/trunk/utils/TableGen/CodeGenTarget.cpp llvm/trunk/utils/TableGen/CodeGenTarget.h llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.cpp?rev=132865&r1=132864&r2=132865&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenRegisters.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenRegisters.cpp Fri Jun 10 19:28:06 2011 @@ -14,6 +14,7 @@ #include "CodeGenRegisters.h" #include "CodeGenTarget.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringExtras.h" using namespace llvm; @@ -22,14 +23,111 @@ // CodeGenRegister //===----------------------------------------------------------------------===// -CodeGenRegister::CodeGenRegister(Record *R) : TheDef(R) { - CostPerUse = R->getValueAsInt("CostPerUse"); -} +CodeGenRegister::CodeGenRegister(Record *R, unsigned Enum) + : TheDef(R), + EnumValue(Enum), + CostPerUse(R->getValueAsInt("CostPerUse")), + SubRegsComplete(false) +{} const std::string &CodeGenRegister::getName() const { return TheDef->getName(); } +namespace { + struct Orphan { + CodeGenRegister *SubReg; + Record *First, *Second; + Orphan(CodeGenRegister *r, Record *a, Record *b) + : SubReg(r), First(a), Second(b) {} + }; +} + +const CodeGenRegister::SubRegMap & +CodeGenRegister::getSubRegs(CodeGenRegBank &RegBank) { + // Only compute this map once. + if (SubRegsComplete) + return SubRegs; + SubRegsComplete = true; + + std::vector SubList = TheDef->getValueAsListOfDefs("SubRegs"); + std::vector Indices = TheDef->getValueAsListOfDefs("SubRegIndices"); + if (SubList.size() != Indices.size()) + throw TGError(TheDef->getLoc(), "Register " + getName() + + " SubRegIndices doesn't match SubRegs"); + + // First insert the direct subregs and make sure they are fully indexed. + for (unsigned i = 0, e = SubList.size(); i != e; ++i) { + CodeGenRegister *SR = RegBank.getReg(SubList[i]); + if (!SubRegs.insert(std::make_pair(Indices[i], SR)).second) + throw TGError(TheDef->getLoc(), "SubRegIndex " + Indices[i]->getName() + + " appears twice in Register " + getName()); + } + + // Keep track of inherited subregs and how they can be reached. + SmallVector Orphans; + + // Clone inherited subregs and place duplicate entries on Orphans. + // Here the order is important - earlier subregs take precedence. + for (unsigned i = 0, e = SubList.size(); i != e; ++i) { + CodeGenRegister *SR = RegBank.getReg(SubList[i]); + const SubRegMap &Map = SR->getSubRegs(RegBank); + for (SubRegMap::const_iterator SI = Map.begin(), SE = Map.end(); SI != SE; + ++SI) + if (!SubRegs.insert(*SI).second) + Orphans.push_back(Orphan(SI->second, Indices[i], SI->first)); + } + + // Process the composites. + ListInit *Comps = TheDef->getValueAsListInit("CompositeIndices"); + for (unsigned i = 0, e = Comps->size(); i != e; ++i) { + DagInit *Pat = dynamic_cast(Comps->getElement(i)); + if (!Pat) + throw TGError(TheDef->getLoc(), "Invalid dag '" + + Comps->getElement(i)->getAsString() + + "' in CompositeIndices"); + DefInit *BaseIdxInit = dynamic_cast(Pat->getOperator()); + if (!BaseIdxInit || !BaseIdxInit->getDef()->isSubClassOf("SubRegIndex")) + throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in " + + Pat->getAsString()); + + // Resolve list of subreg indices into R2. + CodeGenRegister *R2 = this; + for (DagInit::const_arg_iterator di = Pat->arg_begin(), + de = Pat->arg_end(); di != de; ++di) { + DefInit *IdxInit = dynamic_cast(*di); + if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex")) + throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in " + + Pat->getAsString()); + const SubRegMap &R2Subs = R2->getSubRegs(RegBank); + SubRegMap::const_iterator ni = R2Subs.find(IdxInit->getDef()); + if (ni == R2Subs.end()) + throw TGError(TheDef->getLoc(), "Composite " + Pat->getAsString() + + " refers to bad index in " + R2->getName()); + R2 = ni->second; + } + + // Insert composite index. Allow overriding inherited indices etc. + SubRegs[BaseIdxInit->getDef()] = R2; + + // R2 is no longer an orphan. + for (unsigned j = 0, je = Orphans.size(); j != je; ++j) + if (Orphans[j].SubReg == R2) + Orphans[j].SubReg = 0; + } + + // Now Orphans contains the inherited subregisters without a direct index. + // Create inferred indexes for all missing entries. + for (unsigned i = 0, e = Orphans.size(); i != e; ++i) { + Orphan &O = Orphans[i]; + if (!O.SubReg) + continue; + SubRegs[RegBank.getCompositeSubRegIndex(O.First, O.Second, true)] = + O.SubReg; + } + return SubRegs; +} + //===----------------------------------------------------------------------===// // CodeGenRegisterClass //===----------------------------------------------------------------------===// @@ -104,19 +202,45 @@ //===----------------------------------------------------------------------===// CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) : Records(Records) { - // Read in the user-defined (named) sub-register indices. More indices will - // be synthesized. + // Read in the user-defined (named) sub-register indices. + // More indices will be synthesized later. SubRegIndices = Records.getAllDerivedDefinitions("SubRegIndex"); std::sort(SubRegIndices.begin(), SubRegIndices.end(), LessRecord()); NumNamedIndices = SubRegIndices.size(); + + // Read in the register definitions. + std::vector Regs = Records.getAllDerivedDefinitions("Register"); + std::sort(Regs.begin(), Regs.end(), LessRecord()); + Registers.reserve(Regs.size()); + // Assign the enumeration values. + for (unsigned i = 0, e = Regs.size(); i != e; ++i) + Registers.push_back(CodeGenRegister(Regs[i], i + 1)); +} + +CodeGenRegister *CodeGenRegBank::getReg(Record *Def) { + if (Def2Reg.empty()) + for (unsigned i = 0, e = Registers.size(); i != e; ++i) + Def2Reg[Registers[i].TheDef] = &Registers[i]; + + if (CodeGenRegister *Reg = Def2Reg[Def]) + return Reg; + + throw TGError(Def->getLoc(), "Not a known Register!"); } -Record *CodeGenRegBank::getCompositeSubRegIndex(Record *A, Record *B) { +Record *CodeGenRegBank::getCompositeSubRegIndex(Record *A, Record *B, + bool create) { + // Look for an existing entry. + Record *&Comp = Composite[std::make_pair(A, B)]; + if (Comp || !create) + return Comp; + + // None exists, synthesize one. std::string Name = A->getName() + "_then_" + B->getName(); - Record *R = new Record(Name, SMLoc(), Records); - Records.addDef(R); - SubRegIndices.push_back(R); - return R; + Comp = new Record(Name, SMLoc(), Records); + Records.addDef(Comp); + SubRegIndices.push_back(Comp); + return Comp; } unsigned CodeGenRegBank::getSubRegIndexNo(Record *idx) { @@ -126,3 +250,63 @@ return (i - SubRegIndices.begin()) + 1; } +void CodeGenRegBank::computeComposites() { + // Precompute all sub-register maps. This will create Composite entries for + // all inferred sub-register indices. + for (unsigned i = 0, e = Registers.size(); i != e; ++i) + Registers[i].getSubRegs(*this); + + for (unsigned i = 0, e = Registers.size(); i != e; ++i) { + CodeGenRegister *Reg1 = &Registers[i]; + const CodeGenRegister::SubRegMap &SRM1 = Reg1->getSubRegs(*this); + for (CodeGenRegister::SubRegMap::const_iterator i1 = SRM1.begin(), + e1 = SRM1.end(); i1 != e1; ++i1) { + Record *Idx1 = i1->first; + CodeGenRegister *Reg2 = i1->second; + // Ignore identity compositions. + if (Reg1 == Reg2) + continue; + const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs(*this); + // Try composing Idx1 with another SubRegIndex. + for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM2.begin(), + e2 = SRM2.end(); i2 != e2; ++i2) { + std::pair IdxPair(Idx1, i2->first); + CodeGenRegister *Reg3 = i2->second; + // Ignore identity compositions. + if (Reg2 == Reg3) + continue; + // OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3. + for (CodeGenRegister::SubRegMap::const_iterator i1d = SRM1.begin(), + e1d = SRM1.end(); i1d != e1d; ++i1d) { + if (i1d->second == Reg3) { + std::pair Ins = + Composite.insert(std::make_pair(IdxPair, i1d->first)); + // Conflicting composition? Emit a warning but allow it. + if (!Ins.second && Ins.first->second != i1d->first) { + errs() << "Warning: SubRegIndex " << getQualifiedName(Idx1) + << " and " << getQualifiedName(IdxPair.second) + << " compose ambiguously as " + << getQualifiedName(Ins.first->second) << " or " + << getQualifiedName(i1d->first) << "\n"; + } + } + } + } + } + } + + // We don't care about the difference between (Idx1, Idx2) -> Idx2 and invalid + // compositions, so remove any mappings of that form. + for (CompositeMap::iterator i = Composite.begin(), e = Composite.end(); + i != e;) { + CompositeMap::iterator j = i; + ++i; + if (j->first.second == j->second) + Composite.erase(j); + } +} + +void CodeGenRegBank::computeDerivedInfo() { + computeComposites(); +} + Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.h?rev=132865&r1=132864&r2=132865&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenRegisters.h (original) +++ llvm/trunk/utils/TableGen/CodeGenRegisters.h Fri Jun 10 19:28:06 2011 @@ -15,24 +15,43 @@ #ifndef CODEGEN_REGISTERS_H #define CODEGEN_REGISTERS_H +#include "Record.h" #include "llvm/CodeGen/ValueTypes.h" #include "llvm/ADT/DenseMap.h" +#include +#include #include -#include #include -#include +#include namespace llvm { - class Record; - class RecordKeeper; + class CodeGenRegBank; /// CodeGenRegister - Represents a register definition. struct CodeGenRegister { Record *TheDef; - const std::string &getName() const; unsigned EnumValue; unsigned CostPerUse; - CodeGenRegister(Record *R); + + // Map SubRegIndex -> Register. + typedef std::map SubRegMap; + + CodeGenRegister(Record *R, unsigned Enum); + + const std::string &getName() const; + + // Get a map of sub-registers computed lazily. + // This includes unique entries for all sub-sub-registers. + const SubRegMap &getSubRegs(CodeGenRegBank&); + + const SubRegMap &getSubRegs() const { + assert(SubRegsComplete && "Must precompute sub-registers"); + return SubRegs; + } + + private: + bool SubRegsComplete; + SubRegMap SubRegs; }; @@ -104,26 +123,41 @@ // them. class CodeGenRegBank { RecordKeeper &Records; - - // Sub-register indices. The first NumNamedIndices are defined by the user - // in the .td files. The rest are synthesized such that all sub-registers - // have a unique name. std::vector SubRegIndices; - unsigned NumNamedIndices; + std::vector Registers; + DenseMap Def2Reg; + + // Composite SubRegIndex instances. + // Map (SubRegIndex, SubRegIndex) -> SubRegIndex. + typedef DenseMap, Record*> CompositeMap; + CompositeMap Composite; + + // Populate the Composite map from sub-register relationships. + void computeComposites(); public: CodeGenRegBank(RecordKeeper&); + // Sub-register indices. The first NumNamedIndices are defined by the user + // in the .td files. The rest are synthesized such that all sub-registers + // have a unique name. const std::vector &getSubRegIndices() { return SubRegIndices; } - unsigned getNumNamedIndices() { return NumNamedIndices; } // Map a SubRegIndex Record to its enum value. unsigned getSubRegIndexNo(Record *idx); - // Create a new sub-register index representing the A+B composition. - Record *getCompositeSubRegIndex(Record *A, Record *B); + // Find or create a sub-register index representing the A+B composition. + Record *getCompositeSubRegIndex(Record *A, Record *B, bool create = false); + + const std::vector &getRegisters() { return Registers; } + + // Find a register from its Record def. + CodeGenRegister *getReg(Record*); + + // Computed derived records such as missing sub-register indices. + void computeDerivedInfo(); }; } Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=132865&r1=132864&r2=132865&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Fri Jun 10 19:28:06 2011 @@ -163,19 +163,6 @@ return *RegBank; } -void CodeGenTarget::ReadRegisters() const { - std::vector Regs = Records.getAllDerivedDefinitions("Register"); - if (Regs.empty()) - throw std::string("No 'Register' subclasses defined!"); - std::sort(Regs.begin(), Regs.end(), LessRecord()); - - Registers.reserve(Regs.size()); - Registers.assign(Regs.begin(), Regs.end()); - // Assign the enumeration values. - for (unsigned i = 0, e = Registers.size(); i != e; ++i) - Registers[i].EnumValue = i + 1; -} - void CodeGenTarget::ReadRegisterClasses() const { std::vector RegClasses = Records.getAllDerivedDefinitions("RegisterClass"); @@ -189,7 +176,7 @@ /// getRegisterByName - If there is a register with the specific AsmName, /// return it. const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const { - const std::vector &Regs = getRegisters(); + const std::vector &Regs = getRegBank().getRegisters(); for (unsigned i = 0, e = Regs.size(); i != e; ++i) { const CodeGenRegister &Reg = Regs[i]; if (Reg.TheDef->getValueAsString("AsmName") == Name) Modified: llvm/trunk/utils/TableGen/CodeGenTarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.h?rev=132865&r1=132864&r2=132865&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenTarget.h (original) +++ llvm/trunk/utils/TableGen/CodeGenTarget.h Fri Jun 10 19:28:06 2011 @@ -66,10 +66,8 @@ mutable DenseMap Instructions; mutable CodeGenRegBank *RegBank; - mutable std::vector Registers; mutable std::vector RegisterClasses; mutable std::vector LegalValueTypes; - void ReadRegisters() const; void ReadRegisterClasses() const; void ReadInstructions() const; void ReadLegalValueTypes() const; @@ -101,8 +99,7 @@ CodeGenRegBank &getRegBank() const; const std::vector &getRegisters() const { - if (Registers.empty()) ReadRegisters(); - return Registers; + return getRegBank().getRegisters(); } /// getRegisterByName - If there is a register with the specific AsmName, Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=132865&r1=132864&r2=132865&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Fri Jun 10 19:28:06 2011 @@ -168,159 +168,6 @@ addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases); } -struct RegisterMaps { - // Map SubRegIndex -> Register - typedef std::map SubRegMap; - // Map Register -> SubRegMap - typedef std::map SubRegMaps; - - SubRegMaps SubReg; - SubRegMap &inferSubRegIndices(Record *Reg, CodeGenTarget &); - - // Composite SubRegIndex instances. - // Map (SubRegIndex,SubRegIndex) -> SubRegIndex - typedef DenseMap,Record*> CompositeMap; - CompositeMap Composite; - - // Compute SubRegIndex compositions after inferSubRegIndices has run on all - // registers. - void computeComposites(); -}; - -// Calculate all subregindices for Reg. Loopy subregs cause infinite recursion. -RegisterMaps::SubRegMap &RegisterMaps::inferSubRegIndices(Record *Reg, - CodeGenTarget &Target) { - SubRegMap &SRM = SubReg[Reg]; - if (!SRM.empty()) - return SRM; - std::vector SubRegs = Reg->getValueAsListOfDefs("SubRegs"); - std::vector Indices = Reg->getValueAsListOfDefs("SubRegIndices"); - if (SubRegs.size() != Indices.size()) - throw "Register " + Reg->getName() + " SubRegIndices doesn't match SubRegs"; - - // First insert the direct subregs and make sure they are fully indexed. - for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) { - if (!SRM.insert(std::make_pair(Indices[i], SubRegs[i])).second) - throw "SubRegIndex " + Indices[i]->getName() - + " appears twice in Register " + Reg->getName(); - inferSubRegIndices(SubRegs[i], Target); - } - - // Keep track of inherited subregs and how they can be reached. - // Register -> (SubRegIndex, SubRegIndex) - typedef std::map, LessRecord> OrphanMap; - OrphanMap Orphans; - - // Clone inherited subregs. Here the order is important - earlier subregs take - // precedence. - for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) { - SubRegMap &M = SubReg[SubRegs[i]]; - for (SubRegMap::iterator si = M.begin(), se = M.end(); si != se; ++si) - if (!SRM.insert(*si).second) - Orphans[si->second] = std::make_pair(Indices[i], si->first); - } - - // Finally process the composites. - ListInit *Comps = Reg->getValueAsListInit("CompositeIndices"); - for (unsigned i = 0, e = Comps->size(); i != e; ++i) { - DagInit *Pat = dynamic_cast(Comps->getElement(i)); - if (!Pat) - throw "Invalid dag '" + Comps->getElement(i)->getAsString() - + "' in CompositeIndices"; - DefInit *BaseIdxInit = dynamic_cast(Pat->getOperator()); - if (!BaseIdxInit || !BaseIdxInit->getDef()->isSubClassOf("SubRegIndex")) - throw "Invalid SubClassIndex in " + Pat->getAsString(); - - // Resolve list of subreg indices into R2. - Record *R2 = Reg; - for (DagInit::const_arg_iterator di = Pat->arg_begin(), - de = Pat->arg_end(); di != de; ++di) { - DefInit *IdxInit = dynamic_cast(*di); - if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex")) - throw "Invalid SubClassIndex in " + Pat->getAsString(); - SubRegMap::const_iterator ni = SubReg[R2].find(IdxInit->getDef()); - if (ni == SubReg[R2].end()) - throw "Composite " + Pat->getAsString() + " refers to bad index in " - + R2->getName(); - R2 = ni->second; - } - - // Insert composite index. Allow overriding inherited indices etc. - SRM[BaseIdxInit->getDef()] = R2; - - // R2 is now directly addressable, no longer an orphan. - Orphans.erase(R2); - } - - // Now Orphans contains the inherited subregisters without a direct index. - // Create inferred indexes for all missing entries. - for (OrphanMap::iterator I = Orphans.begin(), E = Orphans.end(); I != E; - ++I) { - Record *&Comp = Composite[I->second]; - if (!Comp) - Comp = Target.getRegBank().getCompositeSubRegIndex(I->second.first, - I->second.second); - SRM[Comp] = I->first; - } - - return SRM; -} - -void RegisterMaps::computeComposites() { - for (SubRegMaps::const_iterator sri = SubReg.begin(), sre = SubReg.end(); - sri != sre; ++sri) { - Record *Reg1 = sri->first; - const SubRegMap &SRM1 = sri->second; - for (SubRegMap::const_iterator i1 = SRM1.begin(), e1 = SRM1.end(); - i1 != e1; ++i1) { - Record *Idx1 = i1->first; - Record *Reg2 = i1->second; - // Ignore identity compositions. - if (Reg1 == Reg2) - continue; - // If Reg2 has no subregs, Idx1 doesn't compose. - if (!SubReg.count(Reg2)) - continue; - const SubRegMap &SRM2 = SubReg[Reg2]; - // Try composing Idx1 with another SubRegIndex. - for (SubRegMap::const_iterator i2 = SRM2.begin(), e2 = SRM2.end(); - i2 != e2; ++i2) { - std::pair IdxPair(Idx1, i2->first); - Record *Reg3 = i2->second; - // OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3. - for (SubRegMap::const_iterator i1d = SRM1.begin(), e1d = SRM1.end(); - i1d != e1d; ++i1d) { - // Ignore identity compositions. - if (Reg2 == Reg3) - continue; - if (i1d->second == Reg3) { - std::pair Ins = - Composite.insert(std::make_pair(IdxPair, i1d->first)); - // Conflicting composition? Emit a warning but allow it. - if (!Ins.second && Ins.first->second != i1d->first) { - errs() << "Warning: SubRegIndex " << getQualifiedName(Idx1) - << " and " << getQualifiedName(IdxPair.second) - << " compose ambiguously as " - << getQualifiedName(Ins.first->second) << " or " - << getQualifiedName(i1d->first) << "\n"; - } - } - } - } - } - } - - // We don't care about the difference between (Idx1, Idx2) -> Idx2 and invalid - // compositions, so remove any mappings of that form. - for (CompositeMap::iterator i = Composite.begin(), e = Composite.end(); - i != e;) { - CompositeMap::iterator j = i; - ++i; - if (j->first.second == j->second) - Composite.erase(j); - } -} - class RegisterSorter { private: std::map, LessRecord> &RegisterSubRegs; @@ -340,6 +187,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { CodeGenTarget Target(Records); CodeGenRegBank &RegBank = Target.getRegBank(); + RegBank.computeDerivedInfo(); EmitSourceFileHeader("Register Information Source Fragment", OS); OS << "namespace llvm {\n\n"; @@ -866,9 +714,6 @@ // Calculate the mapping of subregister+index pairs to physical registers. // This will also create further anonymous indexes. unsigned NamedIndices = RegBank.getNumNamedIndices(); - RegisterMaps RegMaps; - for (unsigned i = 0, e = Regs.size(); i != e; ++i) - RegMaps.inferSubRegIndices(Regs[i].TheDef, Target); // Emit SubRegIndex names, skipping 0 const std::vector &SubRegIndices = RegBank.getSubRegIndices(); @@ -901,16 +746,16 @@ << " switch (RegNo) {\n" << " default:\n return 0;\n"; for (unsigned i = 0, e = Regs.size(); i != e; ++i) { - RegisterMaps::SubRegMap &SRM = RegMaps.SubReg[Regs[i].TheDef]; + const CodeGenRegister::SubRegMap &SRM = Regs[i].getSubRegs(); if (SRM.empty()) continue; OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n"; OS << " switch (Index) {\n"; OS << " default: return 0;\n"; - for (RegisterMaps::SubRegMap::const_iterator ii = SRM.begin(), + for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(), ie = SRM.end(); ii != ie; ++ii) OS << " case " << getQualifiedName(ii->first) - << ": return " << getQualifiedName(ii->second) << ";\n"; + << ": return " << getQualifiedName(ii->second->TheDef) << ";\n"; OS << " };\n" << " break;\n"; } OS << " };\n"; @@ -922,13 +767,13 @@ << " switch (RegNo) {\n" << " default:\n return 0;\n"; for (unsigned i = 0, e = Regs.size(); i != e; ++i) { - RegisterMaps::SubRegMap &SRM = RegMaps.SubReg[Regs[i].TheDef]; + const CodeGenRegister::SubRegMap &SRM = Regs[i].getSubRegs(); if (SRM.empty()) continue; OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n"; - for (RegisterMaps::SubRegMap::const_iterator ii = SRM.begin(), + for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(), ie = SRM.end(); ii != ie; ++ii) - OS << " if (SubRegNo == " << getQualifiedName(ii->second) + OS << " if (SubRegNo == " << getQualifiedName(ii->second->TheDef) << ") return " << getQualifiedName(ii->first) << ";\n"; OS << " return 0;\n"; } @@ -937,7 +782,6 @@ OS << "}\n\n"; // Emit composeSubRegIndices - RegMaps.computeComposites(); OS << "unsigned " << ClassName << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n" << " switch (IdxA) {\n" @@ -945,8 +789,8 @@ for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { bool Open = false; for (unsigned j = 0; j != e; ++j) { - if (Record *Comp = RegMaps.Composite.lookup( - std::make_pair(SubRegIndices[i], SubRegIndices[j]))) { + if (Record *Comp = RegBank.getCompositeSubRegIndex(SubRegIndices[i], + SubRegIndices[j])) { if (!Open) { OS << " case " << getQualifiedName(SubRegIndices[i]) << ": switch(IdxB) {\n default: return IdxB;\n"; From atrick at apple.com Fri Jun 10 18:05:22 2011 From: atrick at apple.com (Andrew Trick) Date: Sat, 11 Jun 2011 01:05:22 -0000 Subject: [llvm-commits] [llvm] r132867 - in /llvm/trunk: include/llvm/Analysis/BranchProbabilityInfo.h include/llvm/Support/BranchProbability.h lib/Analysis/BranchProbabilityInfo.cpp lib/Support/BranchProbability.cpp lib/Support/CMakeLists.txt Message-ID: <20110611010522.740002A6C12C@llvm.org> Author: atrick Date: Fri Jun 10 20:05:22 2011 New Revision: 132867 URL: http://llvm.org/viewvc/llvm-project?rev=132867&view=rev Log: Branch profiling: floating-point avoidance. Patch by: Jakub Staszak! Introduces BranchProbability. Changes unsigned to uint32_t all over and uint64_t only when overflow is expected. Added: llvm/trunk/include/llvm/Support/BranchProbability.h llvm/trunk/lib/Support/BranchProbability.cpp Modified: llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp llvm/trunk/lib/Support/CMakeLists.txt Modified: llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h?rev=132867&r1=132866&r2=132867&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h Fri Jun 10 20:05:22 2011 @@ -15,19 +15,24 @@ #define LLVM_ANALYSIS_BRANCHPROBABILITYINFO_H #include "llvm/InitializePasses.h" +#include "llvm/Support/BranchProbability.h" #include "llvm/Analysis/LoopInfo.h" -#include "llvm/Support/Debug.h" namespace llvm { +class raw_ostream; + class BranchProbabilityInfo : public FunctionPass { // Default weight value. Used when we don't have information about the edge. - static const unsigned int DEFAULT_WEIGHT = 16; + static const uint32_t DEFAULT_WEIGHT = 16; typedef std::pair Edge; - DenseMap Weights; + DenseMap Weights; + + // Get sum of the block successors' weights. + uint32_t getSumForBlock(BasicBlock *BB) const; public: static char ID; @@ -43,12 +48,12 @@ bool runOnFunction(Function &F); - // Returned value is between 1 and UINT_MAX. Look at BranchProbabilityInfo.cpp - // for details. - unsigned getEdgeWeight(BasicBlock *Src, BasicBlock *Dst) const; + // Returned value is between 1 and UINT32_MAX. Look at + // BranchProbabilityInfo.cpp for details. + uint32_t getEdgeWeight(BasicBlock *Src, BasicBlock *Dst) const; // Look at BranchProbabilityInfo.cpp for details. Use it with caution! - void setEdgeWeight(BasicBlock *Src, BasicBlock *Dst, unsigned Weight); + void setEdgeWeight(BasicBlock *Src, BasicBlock *Dst, uint32_t Weight); // A 'Hot' edge is an edge which probability is >= 80%. bool isEdgeHot(BasicBlock *Src, BasicBlock *Dst) const; @@ -56,11 +61,16 @@ // Return a hot successor for the block BB or null if there isn't one. BasicBlock *getHotSucc(BasicBlock *BB) const; + // Return a probability as a fraction between 0 (0% probability) and + // 1 (100% probability), however the value is never equal to 0, and can be 1 + // only iff SRC block has only one successor. + BranchProbability getEdgeProbability(BasicBlock *Src, BasicBlock *Dst) const; + // Print value between 0 (0% probability) and 1 (100% probability), // however the value is never equal to 0, and can be 1 only iff SRC block // has only one successor. raw_ostream &printEdgeProbability(raw_ostream &OS, BasicBlock *Src, - BasicBlock *Dst) const; + BasicBlock *Dst) const; }; } Added: llvm/trunk/include/llvm/Support/BranchProbability.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/BranchProbability.h?rev=132867&view=auto ============================================================================== --- llvm/trunk/include/llvm/Support/BranchProbability.h (added) +++ llvm/trunk/include/llvm/Support/BranchProbability.h Fri Jun 10 20:05:22 2011 @@ -0,0 +1,50 @@ +//===- BranchProbability.h - Branch Probability Analysis --------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// Definition of BranchProbability shared by IR and Machine Instructions. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_SUPPORT_BRANCHPROBABILITY_H +#define LLVM_SUPPORT_BRANCHPROBABILITY_H + +#include "llvm/Support/DataTypes.h" + +namespace llvm { + +class raw_ostream; +class BranchProbabilityInfo; +class MachineBranchProbabilityInfo; +class MachineBasicBlock; + +// This class represents Branch Probability as a non-negative fraction. +class BranchProbability { + friend class BranchProbabilityInfo; + friend class MachineBranchProbabilityInfo; + friend class MachineBasicBlock; + + // Numerator + uint32_t N; + + // Denominator + uint32_t D; + + BranchProbability(uint32_t n, uint32_t d); + +public: + raw_ostream &print(raw_ostream &OS) const; + + void dump() const; +}; + +raw_ostream &operator<<(raw_ostream &OS, const BranchProbability &Prob); + +} + +#endif Modified: llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp?rev=132867&r1=132866&r2=132867&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp (original) +++ llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp Fri Jun 10 20:05:22 2011 @@ -13,7 +13,7 @@ #include "llvm/Instructions.h" #include "llvm/Analysis/BranchProbabilityInfo.h" -#include +#include "llvm/Support/Debug.h" using namespace llvm; @@ -34,7 +34,7 @@ typedef std::pair Edge; - DenseMap *Weights; + DenseMap *Weights; BranchProbabilityInfo *BP; @@ -62,15 +62,15 @@ // Probability of the edge BB2->BB1 = 128 / (128 + 4) = 0.9696.. // Probability of the edge BB2->BB3 = 4 / (128 + 4) = 0.0303.. - static const unsigned int LBH_TAKEN_WEIGHT = 128; - static const unsigned int LBH_NONTAKEN_WEIGHT = 4; + static const uint32_t LBH_TAKEN_WEIGHT = 128; + static const uint32_t LBH_NONTAKEN_WEIGHT = 4; // Standard weight value. Used when none of the heuristics set weight for // the edge. - static const unsigned int NORMAL_WEIGHT = 16; + static const uint32_t NORMAL_WEIGHT = 16; // Minimum weight of an edge. Please note, that weight is NEVER 0. - static const unsigned int MIN_WEIGHT = 1; + static const uint32_t MIN_WEIGHT = 1; // Return TRUE if BB leads directly to a Return Instruction. static bool isReturningBlock(BasicBlock *BB) { @@ -101,8 +101,8 @@ // Multiply Edge Weight by two. void incEdgeWeight(BasicBlock *Src, BasicBlock *Dst) { - unsigned Weight = BP->getEdgeWeight(Src, Dst); - unsigned MaxWeight = getMaxWeightFor(Src); + uint32_t Weight = BP->getEdgeWeight(Src, Dst); + uint32_t MaxWeight = getMaxWeightFor(Src); if (Weight * 2 > MaxWeight) BP->setEdgeWeight(Src, Dst, MaxWeight); @@ -112,7 +112,7 @@ // Divide Edge Weight by two. void decEdgeWeight(BasicBlock *Src, BasicBlock *Dst) { - unsigned Weight = BP->getEdgeWeight(Src, Dst); + uint32_t Weight = BP->getEdgeWeight(Src, Dst); assert(Weight > 0); if (Weight / 2 < MIN_WEIGHT) @@ -122,12 +122,12 @@ } - unsigned getMaxWeightFor(BasicBlock *BB) const { - return UINT_MAX / BB->getTerminator()->getNumSuccessors(); + uint32_t getMaxWeightFor(BasicBlock *BB) const { + return UINT32_MAX / BB->getTerminator()->getNumSuccessors(); } public: - BranchProbabilityAnalysis(DenseMap *W, + BranchProbabilityAnalysis(DenseMap *W, BranchProbabilityInfo *BP, LoopInfo *LI) : Weights(W), BP(BP), LI(LI) { } @@ -195,7 +195,7 @@ // Calculate Edge Weights using "Loop Branch Heuristics". Predict backedges // as taken, exiting edges as not-taken. void BranchProbabilityAnalysis::calcLoopBranchHeuristics(BasicBlock *BB) { - unsigned numSuccs = BB->getTerminator()->getNumSuccessors(); + uint32_t numSuccs = BB->getTerminator()->getNumSuccessors(); Loop *L = LI->getLoopFor(BB); if (!L) @@ -213,8 +213,8 @@ BackEdges.push_back(Succ); } - if (unsigned numBackEdges = BackEdges.size()) { - unsigned backWeight = LBH_TAKEN_WEIGHT / numBackEdges; + if (uint32_t numBackEdges = BackEdges.size()) { + uint32_t backWeight = LBH_TAKEN_WEIGHT / numBackEdges; if (backWeight < NORMAL_WEIGHT) backWeight = NORMAL_WEIGHT; @@ -225,9 +225,9 @@ } } - unsigned numExitingEdges = ExitingEdges.size(); - if (unsigned numNonExitingEdges = numSuccs - numExitingEdges) { - unsigned exitWeight = LBH_NONTAKEN_WEIGHT / numNonExitingEdges; + uint32_t numExitingEdges = ExitingEdges.size(); + if (uint32_t numNonExitingEdges = numSuccs - numExitingEdges) { + uint32_t exitWeight = LBH_NONTAKEN_WEIGHT / numNonExitingEdges; if (exitWeight < MIN_WEIGHT) exitWeight = MIN_WEIGHT; @@ -260,36 +260,43 @@ bool BranchProbabilityInfo::runOnFunction(Function &F) { LoopInfo &LI = getAnalysis(); BranchProbabilityAnalysis BPA(&Weights, this, &LI); - bool ret = BPA.runOnFunction(F); - return ret; + return BPA.runOnFunction(F); } -// TODO: This currently hardcodes 80% as a fraction 4/5. We will soon add a -// BranchProbability class to encapsulate the fractional probability and -// define a few static instances of the class for use as predefined thresholds. -bool BranchProbabilityInfo::isEdgeHot(BasicBlock *Src, BasicBlock *Dst) const { - unsigned Sum = 0; - for (succ_iterator I = succ_begin(Src), E = succ_end(Src); I != E; ++I) { +uint32_t BranchProbabilityInfo::getSumForBlock(BasicBlock *BB) const { + uint32_t Sum = 0; + + for (succ_iterator I = succ_begin(BB), E = succ_end(BB); I != E; ++I) { BasicBlock *Succ = *I; - unsigned Weight = getEdgeWeight(Src, Succ); - unsigned PrevSum = Sum; + uint32_t Weight = getEdgeWeight(BB, Succ); + uint32_t PrevSum = Sum; Sum += Weight; assert(Sum > PrevSum); (void) PrevSum; } - return getEdgeWeight(Src, Dst) * 5 > Sum * 4; + return Sum; +} + +bool BranchProbabilityInfo::isEdgeHot(BasicBlock *Src, BasicBlock *Dst) const { + // Hot probability is at least 4/5 = 80% + uint32_t Weight = getEdgeWeight(Src, Dst); + uint32_t Sum = getSumForBlock(Src); + + // FIXME: Implement BranchProbability::compare then change this code to + // compare this BranchProbability against a static "hot" BranchProbability. + return (uint64_t)Weight * 5 > (uint64_t)Sum * 4; } BasicBlock *BranchProbabilityInfo::getHotSucc(BasicBlock *BB) const { - unsigned Sum = 0; - unsigned MaxWeight = 0; + uint32_t Sum = 0; + uint32_t MaxWeight = 0; BasicBlock *MaxSucc = 0; for (succ_iterator I = succ_begin(BB), E = succ_end(BB); I != E; ++I) { BasicBlock *Succ = *I; - unsigned Weight = getEdgeWeight(BB, Succ); - unsigned PrevSum = Sum; + uint32_t Weight = getEdgeWeight(BB, Succ); + uint32_t PrevSum = Sum; Sum += Weight; assert(Sum > PrevSum); (void) PrevSum; @@ -300,17 +307,18 @@ } } - if (MaxWeight * 5 > Sum * 4) + // FIXME: Use BranchProbability::compare. + if ((uint64_t)MaxWeight * 5 > (uint64_t)Sum * 4) return MaxSucc; return 0; } // Return edge's weight. If can't find it, return DEFAULT_WEIGHT value. -unsigned +uint32_t BranchProbabilityInfo::getEdgeWeight(BasicBlock *Src, BasicBlock *Dst) const { Edge E(Src, Dst); - DenseMap::const_iterator I = Weights.find(E); + DenseMap::const_iterator I = Weights.find(E); if (I != Weights.end()) return I->second; @@ -319,30 +327,31 @@ } void BranchProbabilityInfo::setEdgeWeight(BasicBlock *Src, BasicBlock *Dst, - unsigned Weight) { + uint32_t Weight) { Weights[std::make_pair(Src, Dst)] = Weight; - DEBUG(dbgs() << "setEdgeWeight: " << Src->getNameStr() << " -> " - << Dst->getNameStr() << " to " << Weight - << (isEdgeHot(Src, Dst) ? " [is HOT now]\n" : "\n")); + DEBUG(dbgs() << "set edge " << Src->getNameStr() << " -> " + << Dst->getNameStr() << " weight to " << Weight + << (isEdgeHot(Src, Dst) ? " [is HOT now]\n" : "\n")); } -raw_ostream & -BranchProbabilityInfo::printEdgeProbability(raw_ostream &OS, BasicBlock *Src, - BasicBlock *Dst) const { - unsigned Sum = 0; - for (succ_iterator I = succ_begin(Src), E = succ_end(Src); I != E; ++I) { - BasicBlock *Succ = *I; - unsigned Weight = getEdgeWeight(Src, Succ); - unsigned PrevSum = Sum; +BranchProbability BranchProbabilityInfo:: +getEdgeProbability(BasicBlock *Src, BasicBlock *Dst) const { - Sum += Weight; - assert(Sum > PrevSum); (void) PrevSum; - } + uint32_t N = getEdgeWeight(Src, Dst); + uint32_t D = getSumForBlock(Src); + + return BranchProbability(N, D); +} + +raw_ostream & +BranchProbabilityInfo::printEdgeProbability(raw_ostream &OS, BasicBlock *Src, + BasicBlock *Dst) const { + BranchProbability Prob = getEdgeProbability(Src, Dst); - double Prob = (double)getEdgeWeight(Src, Dst) / Sum; - OS << "probability (" << Src->getNameStr() << " --> " << Dst->getNameStr() - << ") = " << Prob << "\n"; + OS << "edge " << Src->getNameStr() << " -> " << Dst->getNameStr() + << " probability is " << Prob + << (isEdgeHot(Src, Dst) ? " [HOT edge]\n" : "\n"); return OS; } Added: llvm/trunk/lib/Support/BranchProbability.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/BranchProbability.cpp?rev=132867&view=auto ============================================================================== --- llvm/trunk/lib/Support/BranchProbability.cpp (added) +++ llvm/trunk/lib/Support/BranchProbability.cpp Fri Jun 10 20:05:22 2011 @@ -0,0 +1,44 @@ +//===-------------- lib/Support/BranchProbability.cpp -----------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements Branch Probability class. +// +//===----------------------------------------------------------------------===// + +#include "llvm/Support/BranchProbability.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/raw_ostream.h" + +using namespace llvm; + +BranchProbability::BranchProbability(uint32_t n, uint32_t d) { + assert(d > 0 && "Denomiator cannot be 0!"); + assert(n <= d && "Probability cannot be bigger than 1!"); + N = n; + D = d; +} + +raw_ostream &BranchProbability::print(raw_ostream &OS) const { + OS << N << " / " << D << " = " << ((double)N / D); + return OS; +} + +void BranchProbability::dump() const { + print(dbgs()); + dbgs() << "\n"; +} + +namespace llvm { + +raw_ostream &operator<<(raw_ostream &OS, const BranchProbability &Prob) { + Prob.print(OS); + return OS; +} + +} Modified: llvm/trunk/lib/Support/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/CMakeLists.txt?rev=132867&r1=132866&r2=132867&view=diff ============================================================================== --- llvm/trunk/lib/Support/CMakeLists.txt (original) +++ llvm/trunk/lib/Support/CMakeLists.txt Fri Jun 10 20:05:22 2011 @@ -9,6 +9,7 @@ APInt.cpp APSInt.cpp Allocator.cpp + BranchProbability.cpp circular_raw_ostream.cpp CommandLine.cpp ConstantRange.cpp From eli.friedman at gmail.com Fri Jun 10 18:55:07 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Sat, 11 Jun 2011 01:55:07 -0000 Subject: [llvm-commits] [llvm] r132869 - /llvm/trunk/lib/Target/X86/X86FastISel.cpp Message-ID: <20110611015507.4CD9F2A6C12C@llvm.org> Author: efriedma Date: Fri Jun 10 20:55:07 2011 New Revision: 132869 URL: http://llvm.org/viewvc/llvm-project?rev=132869&view=rev Log: Make sure to pass OpFlags into MachineInstrBuilder::addExternalSymbol; the memcpy/memset symbol doesn't get marked up correctly in PIC modes otherwise. Should fix llvm-x86_64-linux-checks buildbot. Followup to r132864. Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=132869&r1=132868&r2=132869&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Fri Jun 10 20:55:07 2011 @@ -1784,7 +1784,7 @@ MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc)); if (MemIntName) - MIB.addExternalSymbol(MemIntName); + MIB.addExternalSymbol(MemIntName, OpFlags); else MIB.addGlobalAddress(GV, 0, OpFlags); } From aggarwa4 at illinois.edu Fri Jun 10 19:03:59 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Sat, 11 Jun 2011 02:03:59 -0000 Subject: [llvm-commits] [poolalloc] r132870 - /poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Message-ID: <20110611020359.AC6402A6C12C@llvm.org> Author: aggarwa4 Date: Fri Jun 10 21:03:59 2011 New Revision: 132870 URL: http://llvm.org/viewvc/llvm-project?rev=132870&view=rev Log: Correctly handle cases where a function being transformed is used in an invoke instruction. Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=132870&r1=132869&r2=132870&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Fri Jun 10 21:03:59 2011 @@ -870,50 +870,87 @@ } } + std::vectortoDelete; // Find all uses of the function for(Value::use_iterator ui = F.use_begin(), ue = F.use_end(); - ui != ue;) { + ui != ue;ui ++) { // Check for call sites - if(isa(ui)) { - //FIXME - ui->dump(); - } - CallInst *CI = dyn_cast(ui++); - if(!CI) - continue; - std::vector Args; - inst_iterator InsPt = inst_begin(CI->getParent()->getParent()); - unsigned int i; - unsigned int NumArgs = CI->getNumOperands() - 1; - Value *NumArgsVal = ConstantInt::get(Int32Ty, NumArgs); - AllocaInst *AI = new AllocaInst(Int8Ty, NumArgsVal, "", &*CI); - // set the metadata for the varargs in AI - for(i = 1; i getNumOperands(); i++) { - Value *Idx[2]; - Idx[0] = ConstantInt::get(Int32Ty, i - 1 ); - // For each vararg argument, also add its type information - GetElementPtrInst *GEP = GetElementPtrInst::CreateInBounds(AI, - Idx, - Idx + 1, - "", CI); - Constant *C = getTypeMarkerConstant(CI->getOperand(i)); - new StoreInst(C, GEP, CI); - } + if(InvokeInst *II = dyn_cast(ui)) { + std::vector Args; + inst_iterator InsPt = inst_begin(II->getParent()->getParent()); + unsigned int i; + unsigned int NumArgs = II->getNumOperands() - 3; + Value *NumArgsVal = ConstantInt::get(Int32Ty, NumArgs); + AllocaInst *AI = new AllocaInst(Int8Ty, NumArgsVal, "", &*InsPt); + // set the metadata for the varargs in AI + for(i = 3; i getNumOperands(); i++) { + Value *Idx[2]; + Idx[0] = ConstantInt::get(Int32Ty, i - 3 ); + // For each vararg argument, also add its type information + GetElementPtrInst *GEP = GetElementPtrInst::CreateInBounds(AI, + Idx, + Idx + 1, + "", II); + Constant *C = getTypeMarkerConstant(II->getOperand(i)); + new StoreInst(C, GEP, II); + } - // As the first argument pass the number of var_arg arguments - Args.push_back(ConstantInt::get(Int64Ty, NumArgs)); - Args.push_back(AI); - for(i = 1 ;i < CI->getNumOperands(); i++) { - // Add the original argument - Args.push_back(CI->getOperand(i)); - } + // As the first argument pass the number of var_arg arguments + Args.push_back(ConstantInt::get(Int64Ty, NumArgs)); + Args.push_back(AI); + for(i = 3 ;i < II->getNumOperands(); i++) { + // Add the original argument + Args.push_back(II->getOperand(i)); + } + + // Create the new call + InvokeInst *II_New = InvokeInst::Create(NewF, + II->getNormalDest(), + II->getUnwindDest(), + Args.begin(), Args.end(), + "", II); + II->replaceAllUsesWith(II_New); + toDelete.push_back(II); + } else if (CallInst *CI = dyn_cast(ui)) { + std::vector Args; + inst_iterator InsPt = inst_begin(CI->getParent()->getParent()); + unsigned int i; + unsigned int NumArgs = CI->getNumOperands() - 1; + Value *NumArgsVal = ConstantInt::get(Int32Ty, NumArgs); + AllocaInst *AI = new AllocaInst(Int8Ty, NumArgsVal, "", &*InsPt); + // set the metadata for the varargs in AI + for(i = 1; i getNumOperands(); i++) { + Value *Idx[2]; + Idx[0] = ConstantInt::get(Int32Ty, i - 1 ); + // For each vararg argument, also add its type information + GetElementPtrInst *GEP = GetElementPtrInst::CreateInBounds(AI, + Idx, + Idx + 1, + "", CI); + Constant *C = getTypeMarkerConstant(CI->getOperand(i)); + new StoreInst(C, GEP, CI); + } + + // As the first argument pass the number of var_arg arguments + Args.push_back(ConstantInt::get(Int64Ty, NumArgs)); + Args.push_back(AI); + for(i = 1 ;i < CI->getNumOperands(); i++) { + // Add the original argument + Args.push_back(CI->getOperand(i)); + } - // Create the new call - CallInst *CI_New = CallInst::Create(NewF, - Args.begin(), Args.end(), - "", CI); - CI->replaceAllUsesWith(CI_New); - CI->eraseFromParent(); + // Create the new call + CallInst *CI_New = CallInst::Create(NewF, + Args.begin(), Args.end(), + "", CI); + CI->replaceAllUsesWith(CI_New); + toDelete.push_back(CI); + } + } + while(!toDelete.empty()) { + Instruction *I = toDelete.back(); + toDelete.pop_back(); + I->eraseFromParent(); } IndFunctionsMap[&F] = NewF; return true; @@ -964,17 +1001,60 @@ } // Update the call sites + std::vectortoDelete; for(Value::use_iterator ui = F.use_begin(), ue = F.use_end(); - ui != ue;) { - if(isa(ui)) { - //FIXME - ui->dump(); - } - if(!isa(ui)) { - ui->dump(); - } + ui != ue; ui++) { // Check that F is the called value - if(CallInst *CI = dyn_cast(ui++)) { + if(InvokeInst *II = dyn_cast(ui)) { + if(II->getCalledFunction() == &F) { + SmallVector Args; + SmallVector AttributesVec; + + // Get the initial attributes of the call + AttrListPtr CallPAL = II->getAttributes(); + Attributes RAttrs = CallPAL.getRetAttributes(); + Attributes FnAttrs = CallPAL.getFnAttributes(); + + if (RAttrs) + AttributesVec.push_back(AttributeWithIndex::get(0, RAttrs)); + + Function::arg_iterator NI = F.arg_begin(); + for(unsigned j =3;jgetNumOperands();j++, NI++) { + // Add the original argument + Args.push_back(II->getOperand(j)); + // If there are attributes on this argument, copy them to the correct + // position in the AttributesVec + //FIXME: copy the rest of the attributes. + if(NI->hasByValAttr()) + continue; + if (Attributes Attrs = CallPAL.getParamAttributes(j)) { + AttributesVec.push_back(AttributeWithIndex::get(j, Attrs)); + } + } + + // Create the new attributes vec. + if (FnAttrs != Attribute::None) + AttributesVec.push_back(AttributeWithIndex::get(~0, FnAttrs)); + + AttrListPtr NewCallPAL = AttrListPtr::get(AttributesVec.begin(), + AttributesVec.end()); + + + // Create the substitute call + InvokeInst *CallI = InvokeInst::Create(&F, + II->getNormalDest(), + II->getUnwindDest(), + Args.begin(), + Args.end(), + "", II); + + CallI->setCallingConv(II->getCallingConv()); + CallI->setAttributes(NewCallPAL); + II->replaceAllUsesWith(CallI); + toDelete.push_back(II); + + } + } else if(CallInst *CI = dyn_cast(ui)) { if(CI->getCalledFunction() == &F) { SmallVector Args; SmallVector AttributesVec; @@ -1018,10 +1098,15 @@ CallI->setCallingConv(CI->getCallingConv()); CallI->setAttributes(NewCallPAL); CI->replaceAllUsesWith(CallI); - CI->eraseFromParent(); + toDelete.push_back(CI); } } } + while(!toDelete.empty()) { + Instruction *I = toDelete.back(); + toDelete.pop_back(); + I->eraseFromParent(); + } // remove the byval attribute from the function for (Function::arg_iterator I = F.arg_begin(); I != F.arg_end(); ++I) { @@ -1091,7 +1176,7 @@ void TypeChecks::print(raw_ostream &OS, const Module *M) const { OS << "Types in use by this module:\n"; std::map::const_iterator I = UsedTypes.begin(), - E = UsedTypes.end(); + E = UsedTypes.end(); for (; I != E; ++I) { OS << " "; WriteTypeSymbolic(OS, I->first, M); @@ -1557,29 +1642,6 @@ bool TypeChecks::visitIndirectCallSite(Module &M, Instruction *I) { // add the number of arguments as the first argument - - unsigned int NumArgs = I->getNumOperands() - 1; - Value *NumArgsVal = ConstantInt::get(Int32Ty, NumArgs); - - inst_iterator InsPt = inst_begin(I->getParent()->getParent()); - AllocaInst *AI = new AllocaInst(Int8Ty, NumArgsVal, "", &*InsPt); - for(unsigned int i = 1; i < I->getNumOperands(); i++) { - Value *Idx[2]; - Idx[0] = ConstantInt::get(Int32Ty, i-1); - GetElementPtrInst *GEP = GetElementPtrInst::CreateInBounds(AI, - Idx, - Idx + 1, - "", I); - Constant *C = getTypeMarkerConstant(I->getOperand(i)); - new StoreInst(C, GEP, I); - } - std::vector Args; - Args.push_back(ConstantInt::get(Int64Ty, NumArgs)); - Args.push_back(AI); - - for(unsigned int i = 1; i < I->getNumOperands(); i++) - Args.push_back(I->getOperand(i)); - const Type* OrigType = I->getOperand(0)->getType(); assert(OrigType->isPointerTy()); const FunctionType *FOldType = cast((cast(OrigType))->getElementType()); @@ -1592,7 +1654,28 @@ const FunctionType *FTy = FunctionType::get(FOldType->getReturnType(), TP, FOldType->isVarArg()); CastInst *Func = CastInst::CreatePointerCast(I->getOperand(0), FTy->getPointerTo(), "", I); + + inst_iterator InsPt = inst_begin(I->getParent()->getParent()); + + + + if(isa(I)) { + unsigned int NumArgs = I->getNumOperands() - 1; + Value *NumArgsVal = ConstantInt::get(Int32Ty, NumArgs); + + AllocaInst *AI = new AllocaInst(Int8Ty, NumArgsVal, "", &*InsPt); + for(unsigned int i = 1; i < I->getNumOperands(); i++) { + Value *Idx[2]; + Idx[0] = ConstantInt::get(Int32Ty, i-1); + GetElementPtrInst *GEP = GetElementPtrInst::CreateInBounds(AI, + Idx, + Idx + 1, + "", I); + Constant *C = getTypeMarkerConstant(I->getOperand(i)); + new StoreInst(C, GEP, I); + } + std::vector Args; Args.push_back(ConstantInt::get(Int64Ty, NumArgs)); Args.push_back(AI); @@ -1606,6 +1689,20 @@ I->replaceAllUsesWith(CI_New); I->eraseFromParent(); } else if(InvokeInst *II = dyn_cast(I)) { + unsigned int NumArgs = I->getNumOperands() - 3; + Value *NumArgsVal = ConstantInt::get(Int32Ty, NumArgs); + + AllocaInst *AI = new AllocaInst(Int8Ty, NumArgsVal, "", &*InsPt); + for(unsigned int i = 3; i < I->getNumOperands(); i++) { + Value *Idx[2]; + Idx[0] = ConstantInt::get(Int32Ty, i-3); + GetElementPtrInst *GEP = GetElementPtrInst::CreateInBounds(AI, + Idx, + Idx + 1, + "", I); + Constant *C = getTypeMarkerConstant(I->getOperand(i)); + new StoreInst(C, GEP, I); + } std::vector Args; Args.push_back(ConstantInt::get(Int64Ty, NumArgs)); Args.push_back(AI); From mcrosier at apple.com Fri Jun 10 19:16:36 2011 From: mcrosier at apple.com (Chad Rosier) Date: Sat, 11 Jun 2011 02:16:36 -0000 Subject: [llvm-commits] [llvm] r132871 - /llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Message-ID: <20110611021636.323EE2A6C12C@llvm.org> Author: mcrosier Date: Fri Jun 10 21:16:36 2011 New Revision: 132871 URL: http://llvm.org/viewvc/llvm-project?rev=132871&view=rev Log: Typo. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=132871&r1=132870&r2=132871&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Fri Jun 10 21:16:36 2011 @@ -1175,7 +1175,7 @@ } /// SimplifyDemandedBits - Look at Op. At this point, we know that only the -/// DemandedMask bits of the result of Op are ever used downstream. If we can +/// DemandedMask bits of the result of Op are never used downstream. If we can /// use this information to simplify Op, create a new simplified DAG node and /// return true, returning the original and new nodes in Old and New. Otherwise, /// analyze the expression and return a mask of KnownOne and KnownZero bits for From mcrosier at apple.com Fri Jun 10 19:27:46 2011 From: mcrosier at apple.com (Chad Rosier) Date: Sat, 11 Jun 2011 02:27:46 -0000 Subject: [llvm-commits] [llvm] r132872 - /llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Message-ID: <20110611022746.EEF6A2A6C12C@llvm.org> Author: mcrosier Date: Fri Jun 10 21:27:46 2011 New Revision: 132872 URL: http://llvm.org/viewvc/llvm-project?rev=132872&view=rev Log: Revert r132871. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=132872&r1=132871&r2=132872&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Fri Jun 10 21:27:46 2011 @@ -1175,7 +1175,7 @@ } /// SimplifyDemandedBits - Look at Op. At this point, we know that only the -/// DemandedMask bits of the result of Op are never used downstream. If we can +/// DemandedMask bits of the result of Op are ever used downstream. If we can /// use this information to simplify Op, create a new simplified DAG node and /// return true, returning the original and new nodes in Old and New. Otherwise, /// analyze the expression and return a mask of KnownOne and KnownZero bits for From isanbard at gmail.com Sat Jun 11 02:37:41 2011 From: isanbard at gmail.com (Bill Wendling) Date: Sat, 11 Jun 2011 09:37:41 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r132875 - /llvm-gcc-4.2/trunk/gcc/testsuite/gcc.misc-tests/bprob.exp Message-ID: <20110611093741.0CCB32A6C12C@llvm.org> Author: void Date: Sat Jun 11 04:37:40 2011 New Revision: 132875 URL: http://llvm.org/viewvc/llvm-project?rev=132875&view=rev Log: Add -ftest-coverage flag so that we can get the GCNO file. Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.misc-tests/bprob.exp Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.misc-tests/bprob.exp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.misc-tests/bprob.exp?rev=132875&r1=132874&r2=132875&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.misc-tests/bprob.exp (original) +++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.misc-tests/bprob.exp Sat Jun 11 04:37:40 2011 @@ -47,7 +47,7 @@ # Load support procs. load_lib profopt.exp -set profile_options "-fprofile-arcs" +set profile_options "-fprofile-arcs -ftest-coverage" set feedback_options "-fbranch-probabilities" foreach profile_option $profile_options feedback_option $feedback_options { From isanbard at gmail.com Sat Jun 11 04:37:49 2011 From: isanbard at gmail.com (Bill Wendling) Date: Sat, 11 Jun 2011 11:37:49 -0000 Subject: [llvm-commits] [llvm] r132876 - /llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h Message-ID: <20110611113749.772632A6C12C@llvm.org> Author: void Date: Sat Jun 11 06:37:49 2011 New Revision: 132876 URL: http://llvm.org/viewvc/llvm-project?rev=132876&view=rev Log: Reformatting. Moving class definitions to more natural places. No functionalogical changes. Modified: llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h Modified: llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h?rev=132876&r1=132875&r2=132876&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h Sat Jun 11 06:37:49 2011 @@ -52,27 +52,13 @@ class Constant; class GlobalVariable; class MDNode; +class MMIAddrLabelMap; class MachineBasicBlock; class MachineFunction; class Module; class PointerType; class StructType; -/// MachineModuleInfoImpl - This class can be derived from and used by targets -/// to hold private target-specific information for each Module. Objects of -/// type are accessed/created with MMI::getInfo and destroyed when the -/// MachineModuleInfo is destroyed. -class MachineModuleInfoImpl { -public: - typedef PointerIntPair StubValueTy; - virtual ~MachineModuleInfoImpl(); - typedef std::vector > SymbolListTy; -protected: - static SymbolListTy GetSortedStubs(const DenseMap&); -}; - - - //===----------------------------------------------------------------------===// /// LandingPadInfo - This structure is used to retain landing pad info for /// the current function. @@ -89,7 +75,20 @@ : LandingPadBlock(MBB), LandingPadLabel(0), Personality(0) {} }; -class MMIAddrLabelMap; +//===----------------------------------------------------------------------===// +/// MachineModuleInfoImpl - This class can be derived from and used by targets +/// to hold private target-specific information for each Module. Objects of +/// type are accessed/created with MMI::getInfo and destroyed when the +/// MachineModuleInfo is destroyed. +/// +class MachineModuleInfoImpl { +public: + typedef PointerIntPair StubValueTy; + virtual ~MachineModuleInfoImpl(); + typedef std::vector > SymbolListTy; +protected: + static SymbolListTy GetSortedStubs(const DenseMap&); +}; //===----------------------------------------------------------------------===// /// MachineModuleInfo - This class contains meta information specific to a From hans at chromium.org Sat Jun 11 09:25:14 2011 From: hans at chromium.org (Hans Wennborg) Date: Sat, 11 Jun 2011 17:25:14 +0100 Subject: [llvm-commits] [Patch] SimplifyCFG: Forward switch condition value to phi node Message-ID: The attached patch is an attempt to fix PR10103. In cases such as the attached test, where the case value for a switch destination is used in a phi node that follows the destination, it might be better to replace that value with the condition value of the switch, so that more blocks can be folded away with TryToSimplifyUncondBranchFromEmptyBlock because there are less conflicts in the phi node. I'm not familiar with the optimizations code, so please take a look and let me know if this is a good idea or not. Your comments are most welcome. Thanks, Hans -------------- next part -------------- A non-text attachment was scrubbed... Name: forward-switch-condition-to-phi.patch Type: text/x-patch Size: 5402 bytes Desc: not available URL: From fvbommel at gmail.com Sat Jun 11 10:51:44 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Sat, 11 Jun 2011 19:51:44 +0200 Subject: [llvm-commits] [Patch] SimplifyCFG: Forward switch condition value to phi node In-Reply-To: References: Message-ID: On 11 June 2011 18:25, Hans Wennborg wrote: > The attached patch is an attempt to fix PR10103. > > In cases such as the attached test, where the case value for a switch > destination is used in a phi node that follows the destination, it > might be better to replace that value with the condition value of the > switch, so that more blocks can be folded away with > TryToSimplifyUncondBranchFromEmptyBlock because there are less > conflicts in the phi node. > > I'm not familiar with the optimizations code, so please take a look > and let me know if this is a good idea or not. Your comments are most > welcome. I can't comment on whether this transformation is a good idea, but I do have some remarks about your code: + BasicBlock *Succ = Branch->getSuccessor(0); + + for (BasicBlock::iterator I = Succ->begin(), E = Succ->end(); I != E; ++I) { + PHINode *PHI = dyn_cast(I); + if (!PHI) continue; All PHI nodes must be at the beginning of the basic block, before any other instructions, so you can replace 'continue' with 'break' here. + int Idx = PHI->getBasicBlockIndex(BB); + if (Idx < 0) continue; Since PHI is in a successor of BB, the IR would be invalid if the PHI didn't have an entry for it. You can replace the check with assert(Idx >= 0 && "PHI has no entry for predecessor?"); +static bool ForwardSwitchConditionToPHI(SwitchInst *SI) { + PHINode *ForwardingNode = NULL; + SmallVector ForwardingNodeIndexes; + + for (unsigned I = 1; I < SI->getNumCases(); ++I) { // 0 is the default case. + ConstantInt *CaseValue = SI->getCaseValue(I); + BasicBlock *CaseDest = SI->getSuccessor(I); + + int PhiIndex; + PHINode *PHI = FindPHIForConditionForwarding(CaseValue, CaseDest, + &PhiIndex); + if (!PHI) continue; + + if (!ForwardingNode) + ForwardingNode = PHI; + else if (PHI != ForwardingNode) + continue; + + ForwardingNodeIndexes.push_back(PhiIndex); + } + + if (ForwardingNodeIndexes.size() < 2) + return false; I think the use of ForwardingNode here makes this code dependent on the order of switch cases: if there are multiple blocks with eligible PHIs (in different blocks), but the first one your loop encounters happens to only have one switch case pointing at it then no change will be made even though the others might still be transformable. From cdavis at mines.edu Sat Jun 11 18:45:54 2011 From: cdavis at mines.edu (Charles Davis) Date: Sun, 12 Jun 2011 01:45:54 -0000 Subject: [llvm-commits] [llvm] r132880 - /llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Message-ID: <20110612014554.A9A792A6C12C@llvm.org> Author: cdavis Date: Sat Jun 11 20:45:54 2011 New Revision: 132880 URL: http://llvm.org/viewvc/llvm-project?rev=132880&view=rev Log: Put FrameSetup flag on x86 instructions that set up the call frame. No functionality change. Later on, we'll use the flag to emit SEH pseudo-ops that describe how the call frame was built. Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=132880&r1=132879&r2=132880&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Sat Jun 11 20:45:54 2011 @@ -160,8 +160,10 @@ Opc = isSub ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r) : (Is64Bit ? X86::POP64r : X86::POP32r); - BuildMI(MBB, MBBI, DL, TII.get(Opc)) + MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc)) .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub)); + if (isSub) + MI->setFlag(MachineInstr::FrameSetup); Offset -= ThisVal; continue; } @@ -171,6 +173,8 @@ BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) .addReg(StackPtr) .addImm(ThisVal); + if (isSub) + MI->setFlag(MachineInstr::FrameSetup); MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead. Offset -= ThisVal; } @@ -409,7 +413,8 @@ TII.get(getSUBriOpcode(Is64Bit, -TailCallReturnAddrDelta)), StackPtr) .addReg(StackPtr) - .addImm(-TailCallReturnAddrDelta); + .addImm(-TailCallReturnAddrDelta) + .setMIFlag(MachineInstr::FrameSetup); MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead. } @@ -447,7 +452,8 @@ // Save EBP/RBP into the appropriate stack slot. BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r)) - .addReg(FramePtr, RegState::Kill); + .addReg(FramePtr, RegState::Kill) + .setMIFlag(MachineInstr::FrameSetup); if (needsFrameMoves) { // Mark the place where EBP/RBP was saved. @@ -474,7 +480,8 @@ // Update EBP with the new base value... BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr) - .addReg(StackPtr); + .addReg(StackPtr) + .setMIFlag(MachineInstr::FrameSetup); if (needsFrameMoves) { // Mark effective beginning of when frame pointer becomes valid. @@ -919,7 +926,8 @@ // X86RegisterInfo::emitPrologue will handle spilling of frame register. continue; CalleeFrameSize += SlotSize; - BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill); + BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill) + .setMIFlag(MachineInstr::FrameSetup); } X86FI->setCalleeSavedFrameSize(CalleeFrameSize); From stoklund at 2pi.dk Sat Jun 11 20:05:52 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Sun, 12 Jun 2011 03:05:52 -0000 Subject: [llvm-commits] [llvm] r132881 - in /llvm/trunk: include/llvm/Target/TargetRegisterInfo.h utils/TableGen/CodeGenRegisters.cpp utils/TableGen/CodeGenRegisters.h utils/TableGen/RegisterInfoEmitter.cpp Message-ID: <20110612030552.BB5EB2A6C12C@llvm.org> Author: stoklund Date: Sat Jun 11 22:05:52 2011 New Revision: 132881 URL: http://llvm.org/viewvc/llvm-project?rev=132881&view=rev Log: Compute lists of sub-regs, super-regs, and overlapping regs. Besides moving structural computations to CodeGenRegisters.cpp, this also well-defines the order of these lists: - Sub-register lists come from a pre-order traversal of the graph defined by the SubRegs lists in the .td files. - Super-register lists are topologically ordered so no register comes before any of its sub-registers. When the sub-register graph is not a tree, independent super-registers appear in numerical order. - Lists of overlapping registers are ordered according to register number. This reverses the order of the super-regs lists, but nobody was depending on that. The previous order of the overlaps lists was odd, and it may have depended on the precise behavior of std::stable_sort. The old computations are still there, but will be removed shortly. Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h llvm/trunk/utils/TableGen/CodeGenRegisters.cpp llvm/trunk/utils/TableGen/CodeGenRegisters.h llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=132881&r1=132880&r2=132881&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Sat Jun 11 22:05:52 2011 @@ -434,7 +434,7 @@ /// getSuperRegisters - Return the list of registers that are super-registers /// of the specified register, or a null list of there are none. The list /// returned is zero terminated and sorted according to super-sub register - /// relations. e.g. X86::AL's super-register list is RAX, EAX, AX. + /// relations. e.g. X86::AL's super-register list is AX, EAX, RAX. /// const unsigned *getSuperRegisters(unsigned RegNo) const { return get(RegNo).SuperRegs; Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.cpp?rev=132881&r1=132880&r2=132881&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenRegisters.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenRegisters.cpp Sat Jun 11 22:05:52 2011 @@ -72,10 +72,21 @@ for (unsigned i = 0, e = SubList.size(); i != e; ++i) { CodeGenRegister *SR = RegBank.getReg(SubList[i]); const SubRegMap &Map = SR->getSubRegs(RegBank); + + // Add this as a super-register of SR now all sub-registers are in the list. + // This creates a topological ordering, the exact order depends on the + // order getSubRegs is called on all registers. + SR->SuperRegs.push_back(this); + for (SubRegMap::const_iterator SI = Map.begin(), SE = Map.end(); SI != SE; - ++SI) + ++SI) { if (!SubRegs.insert(*SI).second) Orphans.push_back(Orphan(SI->second, Indices[i], SI->first)); + + // Noop sub-register indexes are possible, so avoid duplicates. + if (SI->second != SR) + SI->second->SuperRegs.push_back(this); + } } // Process the composites. @@ -128,6 +139,17 @@ return SubRegs; } +void +CodeGenRegister::addSubRegsPreOrder(SetVector &OSet) const { + assert(SubRegsComplete && "Must precompute sub-registers"); + std::vector Indices = TheDef->getValueAsListOfDefs("SubRegIndices"); + for (unsigned i = 0, e = Indices.size(); i != e; ++i) { + CodeGenRegister *SR = SubRegs.find(Indices[i])->second; + if (OSet.insert(SR)) + SR->addSubRegsPreOrder(OSet); + } +} + //===----------------------------------------------------------------------===// // CodeGenRegisterClass //===----------------------------------------------------------------------===// @@ -258,7 +280,7 @@ for (unsigned i = 0, e = Registers.size(); i != e; ++i) { CodeGenRegister *Reg1 = &Registers[i]; - const CodeGenRegister::SubRegMap &SRM1 = Reg1->getSubRegs(*this); + const CodeGenRegister::SubRegMap &SRM1 = Reg1->getSubRegs(); for (CodeGenRegister::SubRegMap::const_iterator i1 = SRM1.begin(), e1 = SRM1.end(); i1 != e1; ++i1) { Record *Idx1 = i1->first; @@ -266,7 +288,7 @@ // Ignore identity compositions. if (Reg1 == Reg2) continue; - const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs(*this); + const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs(); // Try composing Idx1 with another SubRegIndex. for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM2.begin(), e2 = SRM2.end(); i2 != e2; ++i2) { @@ -306,6 +328,80 @@ } } +// Compute sets of overlapping registers. +// +// The standard set is all super-registers and all sub-registers, but the +// target description can add arbitrary overlapping registers via the 'Aliases' +// field. This complicates things, but we can compute overlapping sets using +// the following rules: +// +// 1. The relation overlap(A, B) is reflexive and symmetric but not transitive. +// +// 2. overlap(A, B) implies overlap(A, S) for all S in supers(B). +// +// Alternatively: +// +// overlap(A, B) iff there exists: +// A' in { A, subregs(A) } and B' in { B, subregs(B) } such that: +// A' = B' or A' in aliases(B') or B' in aliases(A'). +// +// Here subregs(A) is the full flattened sub-register set returned by +// A.getSubRegs() while aliases(A) is simply the special 'Aliases' field in the +// description of register A. +// +// This also implies that registers with a common sub-register are considered +// overlapping. This can happen when forming register pairs: +// +// P0 = (R0, R1) +// P1 = (R1, R2) +// P2 = (R2, R3) +// +// In this case, we will infer an overlap between P0 and P1 because of the +// shared sub-register R1. There is no overlap between P0 and P2. +// +void CodeGenRegBank:: +computeOverlaps(std::map &Map) { + assert(Map.empty()); + + // Collect overlaps that don't follow from rule 2. + for (unsigned i = 0, e = Registers.size(); i != e; ++i) { + CodeGenRegister *Reg = &Registers[i]; + CodeGenRegister::Set &Overlaps = Map[Reg]; + + // Reg overlaps itself. + Overlaps.insert(Reg); + + // All super-registers overlap. + const CodeGenRegister::SuperRegList &Supers = Reg->getSuperRegs(); + Overlaps.insert(Supers.begin(), Supers.end()); + + // Form symmetrical relations from the special Aliases[] lists. + std::vector RegList = Reg->TheDef->getValueAsListOfDefs("Aliases"); + for (unsigned i2 = 0, e2 = RegList.size(); i2 != e2; ++i2) { + CodeGenRegister *Reg2 = getReg(RegList[i2]); + CodeGenRegister::Set &Overlaps2 = Map[Reg2]; + const CodeGenRegister::SuperRegList &Supers2 = Reg2->getSuperRegs(); + // Reg overlaps Reg2 which implies it overlaps supers(Reg2). + Overlaps.insert(Reg2); + Overlaps.insert(Supers2.begin(), Supers2.end()); + Overlaps2.insert(Reg); + Overlaps2.insert(Supers.begin(), Supers.end()); + } + } + + // Apply rule 2. and inherit all sub-register overlaps. + for (unsigned i = 0, e = Registers.size(); i != e; ++i) { + CodeGenRegister *Reg = &Registers[i]; + CodeGenRegister::Set &Overlaps = Map[Reg]; + const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs(); + for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM.begin(), + e2 = SRM.end(); i2 != e2; ++i2) { + CodeGenRegister::Set &Overlaps2 = Map[i2->second]; + Overlaps.insert(Overlaps2.begin(), Overlaps2.end()); + } + } +} + void CodeGenRegBank::computeDerivedInfo() { computeComposites(); } Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.h?rev=132881&r1=132880&r2=132881&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenRegisters.h (original) +++ llvm/trunk/utils/TableGen/CodeGenRegisters.h Sat Jun 11 22:05:52 2011 @@ -18,6 +18,7 @@ #include "Record.h" #include "llvm/CodeGen/ValueTypes.h" #include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/SetVector.h" #include #include #include @@ -49,9 +50,33 @@ return SubRegs; } + // Add sub-registers to OSet following a pre-order defined by the .td file. + void addSubRegsPreOrder(SetVector &OSet) const; + + // List of super-registers in topological order, small to large. + typedef std::vector SuperRegList; + + // Get the list of super-registers. + // This is only valid after computeDerivedInfo has visited all registers. + const SuperRegList &getSuperRegs() const { + assert(SubRegsComplete && "Must precompute sub-registers"); + return SuperRegs; + } + + // Order CodeGenRegister pointers by EnumValue. + struct Less { + bool operator()(const CodeGenRegister *A, const CodeGenRegister *B) { + return A->EnumValue < B->EnumValue; + } + }; + + // Canonically ordered set. + typedef std::set Set; + private: bool SubRegsComplete; SubRegMap SubRegs; + SuperRegList SuperRegs; }; @@ -158,6 +183,15 @@ // Computed derived records such as missing sub-register indices. void computeDerivedInfo(); + + // Compute full overlap sets for every register. These sets include the + // rarely used aliases that are neither sub nor super-registers. + // + // Map[R1].count(R2) is reflexive and symmetric, but not transitive. + // + // If R1 is a sub-register of R2, Map[R1] is a subset of Map[R2]. + void computeOverlaps(std::map &Map); }; } Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=132881&r1=132880&r2=132881&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Sat Jun 11 22:05:52 2011 @@ -168,26 +168,15 @@ addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases); } -class RegisterSorter { -private: - std::map, LessRecord> &RegisterSubRegs; - -public: - RegisterSorter(std::map, LessRecord> &RS) - : RegisterSubRegs(RS) {} - - bool operator()(Record *RegA, Record *RegB) { - // B is sub-register of A. - return RegisterSubRegs.count(RegA) && RegisterSubRegs[RegA].count(RegB); - } -}; - // RegisterInfoEmitter::run - Main register file description emitter. // void RegisterInfoEmitter::run(raw_ostream &OS) { CodeGenTarget Target(Records); CodeGenRegBank &RegBank = Target.getRegBank(); RegBank.computeDerivedInfo(); + std::map Overlaps; + RegBank.computeOverlaps(Overlaps); + EmitSourceFileHeader("Register Information Source Fragment", OS); OS << "namespace llvm {\n\n"; @@ -632,60 +621,48 @@ OS << "\n\n // Register Overlap Lists...\n"; // Emit an overlap list for all registers. - for (std::map, LessRecord >::iterator - I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) { - OS << " const unsigned " << I->first->getName() << "_Overlaps[] = { " - << getQualifiedName(I->first) << ", "; - for (std::set::iterator ASI = I->second.begin(), - E = I->second.end(); ASI != E; ++ASI) - OS << getQualifiedName(*ASI) << ", "; + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { + const CodeGenRegister *Reg = &Regs[i]; + const CodeGenRegister::Set &O = Overlaps[Reg]; + // Move Reg to the front so TRI::getAliasSet can share the list. + OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { " + << getQualifiedName(Reg->TheDef) << ", "; + for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end(); + I != E; ++I) + if (*I != Reg) + OS << getQualifiedName((*I)->TheDef) << ", "; OS << "0 };\n"; } - if (!RegisterSubRegs.empty()) - OS << "\n\n // Register Sub-registers Sets...\n"; - // Emit the empty sub-registers list OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n"; // Loop over all of the registers which have sub-registers, emitting the // sub-registers list to memory. - for (std::map, LessRecord>::iterator - I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) { - if (I->second.empty()) + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { + const CodeGenRegister &Reg = Regs[i]; + if (Reg.getSubRegs().empty()) continue; - OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { "; - std::vector SubRegsVector; - for (std::set::iterator ASI = I->second.begin(), - E = I->second.end(); ASI != E; ++ASI) - SubRegsVector.push_back(*ASI); - RegisterSorter RS(RegisterSubRegs); - std::stable_sort(SubRegsVector.begin(), SubRegsVector.end(), RS); - for (unsigned i = 0, e = SubRegsVector.size(); i != e; ++i) - OS << getQualifiedName(SubRegsVector[i]) << ", "; + // getSubRegs() orders by SubRegIndex. We want a topological order. + SetVector SR; + Reg.addSubRegsPreOrder(SR); + OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { "; + for (unsigned j = 0, je = SR.size(); j != je; ++j) + OS << getQualifiedName(SR[j]->TheDef) << ", "; OS << "0 };\n"; } - if (!RegisterSuperRegs.empty()) - OS << "\n\n // Register Super-registers Sets...\n"; - // Emit the empty super-registers list OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n"; // Loop over all of the registers which have super-registers, emitting the // super-registers list to memory. - for (std::map, LessRecord >::iterator - I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) { - if (I->second.empty()) + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { + const CodeGenRegister &Reg = Regs[i]; + const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs(); + if (SR.empty()) continue; - OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { "; - - std::vector SuperRegsVector; - for (std::set::iterator ASI = I->second.begin(), - E = I->second.end(); ASI != E; ++ASI) - SuperRegsVector.push_back(*ASI); - RegisterSorter RS(RegisterSubRegs); - std::stable_sort(SuperRegsVector.begin(), SuperRegsVector.end(), RS); - for (unsigned i = 0, e = SuperRegsVector.size(); i != e; ++i) - OS << getQualifiedName(SuperRegsVector[i]) << ", "; + OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { "; + for (unsigned j = 0, je = SR.size(); j != je; ++j) + OS << getQualifiedName(SR[j]->TheDef) << ", "; OS << "0 };\n"; } @@ -698,11 +675,11 @@ const CodeGenRegister &Reg = Regs[i]; OS << " { \""; OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t"; - if (!RegisterSubRegs[Reg.TheDef].empty()) + if (!Reg.getSubRegs().empty()) OS << Reg.getName() << "_SubRegsSet,\t"; else OS << "Empty_SubRegsSet,\t"; - if (!RegisterSuperRegs[Reg.TheDef].empty()) + if (!Reg.getSuperRegs().empty()) OS << Reg.getName() << "_SuperRegsSet,\t"; else OS << "Empty_SuperRegsSet,\t"; From rafael.espindola at gmail.com Sat Jun 11 20:20:32 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Sun, 12 Jun 2011 03:20:32 -0000 Subject: [llvm-commits] [llvm] r132882 - in /llvm/trunk: lib/CodeGen/AsmPrinter/AsmPrinter.cpp lib/Target/X86/X86InstrInfo.cpp test/CodeGen/Thumb2/machine-licm.ll Message-ID: <20110612032033.086FB2A6C12C@llvm.org> Author: rafael Date: Sat Jun 11 22:20:32 2011 New Revision: 132882 URL: http://llvm.org/viewvc/llvm-project?rev=132882&view=rev Log: AnalyzeBranch doesn't change which successors a bb has, just the order we try to branch to them. Before we were creating successor lists with duplicated entries. Fixing that found a bug in isBlockOnlyReachableByFallthrough that would causes it to return the wrong answer for ----------- ... jne foo jmp bar foo: ---------- Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.cpp llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=132882&r1=132881&r2=132882&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Sat Jun 11 22:20:32 2011 @@ -1925,7 +1925,7 @@ return false; // The predecessor has to be immediately before this block. - const MachineBasicBlock *Pred = *PI; + MachineBasicBlock *Pred = *PI; if (!Pred->isLayoutSuccessor(MBB)) return false; @@ -1934,9 +1934,16 @@ if (Pred->empty()) return true; - // Otherwise, check the last instruction. - const MachineInstr &LastInst = Pred->back(); - return !LastInst.getDesc().isBarrier(); + // Otherwise, ask the backend. + const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); + MachineBasicBlock *PredTBB = NULL, *PredFBB = NULL; + SmallVector PredCond; + if (TII->AnalyzeBranch(*Pred, PredTBB, PredFBB, PredCond)) + return false; + + if (PredCond.empty()) + return true; + return !PredFBB || PredFBB == MBB; } Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=132882&r1=132881&r2=132882&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Sat Jun 11 22:20:32 2011 @@ -1789,7 +1789,6 @@ .addMBB(UnCondBrIter->getOperand(0).getMBB()); BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4)) .addMBB(TargetBB); - MBB.addSuccessor(TargetBB); OldInst->eraseFromParent(); UnCondBrIter->eraseFromParent(); Modified: llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll?rev=132882&r1=132881&r2=132882&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll Sat Jun 11 22:20:32 2011 @@ -13,7 +13,7 @@ br i1 %0, label %return, label %bb.nph bb.nph: ; preds = %entry -; CHECK: BB#1 +; CHECK: LBB0_1: ; CHECK: movw r[[R2:[0-9]+]], :lower16:L_GV$non_lazy_ptr ; CHECK: movt r[[R2]], :upper16:L_GV$non_lazy_ptr ; CHECK: ldr{{(.w)?}} r[[R2b:[0-9]+]], [r[[R2]] @@ -21,7 +21,7 @@ ; CHECK: LBB0_2 ; CHECK-NOT: LCPI0_0: -; PIC: BB#1 +; PIC: LBB0_1: ; PIC: movw r[[R2:[0-9]+]], :lower16:(L_GV$non_lazy_ptr-(LPC0_0+4)) ; PIC: movt r[[R2]], :upper16:(L_GV$non_lazy_ptr-(LPC0_0+4)) ; PIC: add r[[R2]], pc From rafael.espindola at gmail.com Sat Jun 11 22:26:32 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Sun, 12 Jun 2011 05:26:32 -0000 Subject: [llvm-commits] [llvm] r132883 - /llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Message-ID: <20110612052632.923B92A6C12C@llvm.org> Author: rafael Date: Sun Jun 12 00:26:32 2011 New Revision: 132883 URL: http://llvm.org/viewvc/llvm-project?rev=132883&view=rev Log: Fix silly bug I introduce in the previous commit. Fixes debug builds. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=132883&r1=132882&r2=132883&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Sun Jun 12 00:26:32 2011 @@ -1941,9 +1941,9 @@ if (TII->AnalyzeBranch(*Pred, PredTBB, PredFBB, PredCond)) return false; - if (PredCond.empty()) - return true; - return !PredFBB || PredFBB == MBB; + // This is a fall through if there is no conditions in the bb + // or if there is no explicit false branch. + return PredCond.empty() || !PredFBB; } From rafael.espindola at gmail.com Sat Jun 11 22:35:39 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Sun, 12 Jun 2011 05:35:39 -0000 Subject: [llvm-commits] [llvm] r132884 - /llvm/trunk/test/CodeGen/X86/asm-label.ll Message-ID: <20110612053539.5E68C2A6C12C@llvm.org> Author: rafael Date: Sun Jun 12 00:35:39 2011 New Revision: 132884 URL: http://llvm.org/viewvc/llvm-project?rev=132884&view=rev Log: Test for the previous commit. Added: llvm/trunk/test/CodeGen/X86/asm-label.ll Added: llvm/trunk/test/CodeGen/X86/asm-label.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/asm-label.ll?rev=132884&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/asm-label.ll (added) +++ llvm/trunk/test/CodeGen/X86/asm-label.ll Sun Jun 12 00:35:39 2011 @@ -0,0 +1,40 @@ +; RUN: llc -O0 < %s | FileCheck %s + +; test that we print a label that we use. We had a bug where +; we would print the jump, but not the label because it was considered +; a fall through. + +; CHECK: jmp LBB0_9 +; CHECK: LBB0_9: ## %cleanup + +define void @foo() { +entry: + br i1 undef, label %land.lhs.true, label %if.end11 + +land.lhs.true: ; preds = %entry + br i1 undef, label %if.then, label %if.end11 + +if.then: ; preds = %land.lhs.true + br i1 undef, label %if.then9, label %if.end + +if.then9: ; preds = %if.then + br label %cleanup + +if.end: ; preds = %if.then + br label %cleanup + +cleanup: ; preds = %if.end, %if.then9 + switch i32 undef, label %unreachable [ + i32 0, label %cleanup.cont + i32 1, label %if.end11 + ] + +cleanup.cont: ; preds = %cleanup + br label %if.end11 + +if.end11: ; preds = %cleanup.cont, %cleanup, %land.lhs.true, %entry + ret void + +unreachable: ; preds = %cleanup + unreachable +} From rafael.espindola at gmail.com Sat Jun 11 22:57:01 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Sun, 12 Jun 2011 05:57:01 -0000 Subject: [llvm-commits] [llvm] r132885 - in /llvm/trunk: lib/CodeGen/AsmPrinter/AsmPrinter.cpp test/CodeGen/X86/asm-label.ll test/CodeGen/X86/asm-label2.ll Message-ID: <20110612055701.5912E2A6C12C@llvm.org> Author: rafael Date: Sun Jun 12 00:57:01 2011 New Revision: 132885 URL: http://llvm.org/viewvc/llvm-project?rev=132885&view=rev Log: Really fix the fall-through logic. Add a triple to the tests. Added: llvm/trunk/test/CodeGen/X86/asm-label2.ll Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp llvm/trunk/test/CodeGen/X86/asm-label.ll Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=132885&r1=132884&r2=132885&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Sun Jun 12 00:57:01 2011 @@ -1941,6 +1941,9 @@ if (TII->AnalyzeBranch(*Pred, PredTBB, PredFBB, PredCond)) return false; + if (PredTBB == MBB || PredFBB == MBB) + return false; + // This is a fall through if there is no conditions in the bb // or if there is no explicit false branch. return PredCond.empty() || !PredFBB; Modified: llvm/trunk/test/CodeGen/X86/asm-label.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/asm-label.ll?rev=132885&r1=132884&r2=132885&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/asm-label.ll (original) +++ llvm/trunk/test/CodeGen/X86/asm-label.ll Sun Jun 12 00:57:01 2011 @@ -1,4 +1,4 @@ -; RUN: llc -O0 < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-apple-darwin10 -O0 < %s | FileCheck %s ; test that we print a label that we use. We had a bug where ; we would print the jump, but not the label because it was considered Added: llvm/trunk/test/CodeGen/X86/asm-label2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/asm-label2.ll?rev=132885&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/asm-label2.ll (added) +++ llvm/trunk/test/CodeGen/X86/asm-label2.ll Sun Jun 12 00:57:01 2011 @@ -0,0 +1,22 @@ +; RUN: llc -mtriple=x86_64-apple-darwin10 -O0 < %s | FileCheck %s + +; test that we print a label that we use. We had a bug where +; we would print the jump, but not the label because it was considered +; a fall through. + +; CHECK: jmp LBB0_1 +; CHECK: LBB0_1: + +define void @foobar() { +entry: + invoke void @_zed() + to label %invoke.cont unwind label %lpad + +invoke.cont: ; preds = %entry + ret void + +lpad: ; preds = %entry + unreachable +} + +declare void @_zed() ssp align 2 From stoklund at 2pi.dk Sat Jun 11 23:58:42 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Sat, 11 Jun 2011 23:58:42 -0700 Subject: [llvm-commits] [llvm] r132882 - in /llvm/trunk: lib/CodeGen/AsmPrinter/AsmPrinter.cpp lib/Target/X86/X86InstrInfo.cpp test/CodeGen/Thumb2/machine-licm.ll In-Reply-To: <20110612032033.086FB2A6C12C@llvm.org> References: <20110612032033.086FB2A6C12C@llvm.org> Message-ID: <22E522CD-27D8-4C2D-A89E-3F9004CC9D3C@2pi.dk> On Jun 11, 2011, at 8:20 PM, Rafael Espindola wrote: > - // Otherwise, check the last instruction. > - const MachineInstr &LastInst = Pred->back(); > - return !LastInst.getDesc().isBarrier(); > + // Otherwise, ask the backend. > + const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); > + MachineBasicBlock *PredTBB = NULL, *PredFBB = NULL; > + SmallVector PredCond; > + if (TII->AnalyzeBranch(*Pred, PredTBB, PredFBB, PredCond)) > + return false; > + > + if (PredCond.empty()) > + return true; > + return !PredFBB || PredFBB == MBB; > } The double-CFG-edge hack was added as a compile time optimization. While I like to see it go, we should at least confirm that it was a premature optimization. Did you measure before/after compile times? The -O0 compile times are extra interesting. /jakob -------------- next part -------------- An HTML attachment was scrubbed... URL: From stoklund at 2pi.dk Sun Jun 12 00:04:26 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Sun, 12 Jun 2011 07:04:26 -0000 Subject: [llvm-commits] [llvm] r132886 - /llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Message-ID: <20110612070426.910B32A6C12C@llvm.org> Author: stoklund Date: Sun Jun 12 02:04:26 2011 New Revision: 132886 URL: http://llvm.org/viewvc/llvm-project?rev=132886&view=rev Log: Extract the generateHashTable function. The constant hash tables for sub-registers and overlaps are generated the same way, so extract a function to generate and print the hash table. Also use the information computed by CodeGenRegisters.cpp instead of the locally data. Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=132886&r1=132885&r2=132886&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Sun Jun 12 02:04:26 2011 @@ -19,6 +19,7 @@ #include "Record.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/Support/Format.h" #include #include using namespace llvm; @@ -168,6 +169,51 @@ addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases); } +typedef std::pair UUPair; +typedef std::vector UUVector; + +// Generate and print a quadratically probed hash table of unsigned pairs. +// The pair (0,0) is used as a sentinel, so it cannot be a data point. +static void generateHashTable(raw_ostream &OS, const char *Name, + const UUVector &Data) { + const UUPair Sentinel(0, 0); + unsigned HSize = Data.size(); + UUVector HT; + + // Hashtable size must be a power of two. + HSize = 2 * NextPowerOf2(2 * HSize); + HT.assign(HSize, Sentinel); + + // Insert all entries. + unsigned MaxProbes = 0; + for (unsigned i = 0, e = Data.size(); i != e; ++i) { + UUPair D = Data[i]; + unsigned Idx = (D.first + D.second * 37) & (HSize - 1); + unsigned ProbeAmt = 2; + while (HT[Idx] != Sentinel) { + Idx = (Idx + ProbeAmt) & (HSize - 1); + ProbeAmt += 2; + } + HT[Idx] = D; + MaxProbes = std::max(MaxProbes, ProbeAmt/2); + } + + // Print the hash table. + OS << "\n\n // Max number of probes: " << MaxProbes + << "\n // Used entries: " << Data.size() + << "\n const unsigned " << Name << "Size = " << HSize << ';' + << "\n const unsigned " << Name << "[] = {\n"; + + for (unsigned i = 0, e = HSize; i != e; ++i) { + UUPair D = HT[i]; + OS << format(" %3u,%3u,", D.first, D.second); + if (i % 8 == 7 && i + 1 != e) + OS << '\n'; + } + OS << "\n };\n"; +} + +// // RegisterInfoEmitter::run - Main register file description emitter. // void RegisterInfoEmitter::run(raw_ostream &OS) { @@ -468,157 +514,28 @@ // Print the SubregHashTable, a simple quadratically probed // hash table for determining if a register is a subregister // of another register. - unsigned NumSubRegs = 0; - std::map RegNo; + UUVector HTData; for (unsigned i = 0, e = Regs.size(); i != e; ++i) { - RegNo[Regs[i].TheDef] = i; - NumSubRegs += RegisterSubRegs[Regs[i].TheDef].size(); - } - - unsigned SubregHashTableSize = 2 * NextPowerOf2(2 * NumSubRegs); - unsigned* SubregHashTable = new unsigned[2 * SubregHashTableSize]; - std::fill(SubregHashTable, SubregHashTable + 2 * SubregHashTableSize, ~0U); - - unsigned hashMisses = 0; - - for (unsigned i = 0, e = Regs.size(); i != e; ++i) { - Record* R = Regs[i].TheDef; - for (std::set::iterator I = RegisterSubRegs[R].begin(), - E = RegisterSubRegs[R].end(); I != E; ++I) { - Record* RJ = *I; - // We have to increase the indices of both registers by one when - // computing the hash because, in the generated code, there - // will be an extra empty slot at register 0. - size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SubregHashTableSize-1); - unsigned ProbeAmt = 2; - while (SubregHashTable[index*2] != ~0U && - SubregHashTable[index*2+1] != ~0U) { - index = (index + ProbeAmt) & (SubregHashTableSize-1); - ProbeAmt += 2; - - hashMisses++; - } - - SubregHashTable[index*2] = i; - SubregHashTable[index*2+1] = RegNo[RJ]; - } + unsigned RegNo = Regs[i].EnumValue; + const CodeGenRegister::SuperRegList &SR = Regs[i].getSuperRegs(); + for (CodeGenRegister::SuperRegList::const_iterator I = SR.begin(), + E = SR.end(); I != E; ++I) + HTData.push_back(UUPair((*I)->EnumValue, RegNo)); } - - OS << "\n\n // Number of hash collisions: " << hashMisses << "\n"; - - if (SubregHashTableSize) { - std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace"); - - OS << " const unsigned SubregHashTable[] = { "; - for (unsigned i = 0; i < SubregHashTableSize - 1; ++i) { - if (i != 0) - // Insert spaces for nice formatting. - OS << " "; - - if (SubregHashTable[2*i] != ~0U) { - OS << getQualifiedName(Regs[SubregHashTable[2*i]].TheDef) << ", " - << getQualifiedName(Regs[SubregHashTable[2*i+1]].TheDef) << ", \n"; - } else { - OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n"; - } - } - - unsigned Idx = SubregHashTableSize*2-2; - if (SubregHashTable[Idx] != ~0U) { - OS << " " - << getQualifiedName(Regs[SubregHashTable[Idx]].TheDef) << ", " - << getQualifiedName(Regs[SubregHashTable[Idx+1]].TheDef) << " };\n"; - } else { - OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n"; - } - - OS << " const unsigned SubregHashTableSize = " - << SubregHashTableSize << ";\n"; - } else { - OS << " const unsigned SubregHashTable[] = { ~0U, ~0U };\n" - << " const unsigned SubregHashTableSize = 1;\n"; - } - - delete [] SubregHashTable; - + generateHashTable(OS, "SubregHashTable", HTData); // Print the AliasHashTable, a simple quadratically probed // hash table for determining if a register aliases another register. - unsigned NumAliases = 0; - RegNo.clear(); + HTData.clear(); for (unsigned i = 0, e = Regs.size(); i != e; ++i) { - RegNo[Regs[i].TheDef] = i; - NumAliases += RegisterAliases[Regs[i].TheDef].size(); - } - - unsigned AliasesHashTableSize = 2 * NextPowerOf2(2 * NumAliases); - unsigned* AliasesHashTable = new unsigned[2 * AliasesHashTableSize]; - std::fill(AliasesHashTable, AliasesHashTable + 2 * AliasesHashTableSize, ~0U); - - hashMisses = 0; - - for (unsigned i = 0, e = Regs.size(); i != e; ++i) { - Record* R = Regs[i].TheDef; - for (std::set::iterator I = RegisterAliases[R].begin(), - E = RegisterAliases[R].end(); I != E; ++I) { - Record* RJ = *I; - // We have to increase the indices of both registers by one when - // computing the hash because, in the generated code, there - // will be an extra empty slot at register 0. - size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (AliasesHashTableSize-1); - unsigned ProbeAmt = 2; - while (AliasesHashTable[index*2] != ~0U && - AliasesHashTable[index*2+1] != ~0U) { - index = (index + ProbeAmt) & (AliasesHashTableSize-1); - ProbeAmt += 2; - - hashMisses++; - } - - AliasesHashTable[index*2] = i; - AliasesHashTable[index*2+1] = RegNo[RJ]; - } - } - - OS << "\n\n // Number of hash collisions: " << hashMisses << "\n"; - - if (AliasesHashTableSize) { - std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace"); - - OS << " const unsigned AliasesHashTable[] = { "; - for (unsigned i = 0; i < AliasesHashTableSize - 1; ++i) { - if (i != 0) - // Insert spaces for nice formatting. - OS << " "; - - if (AliasesHashTable[2*i] != ~0U) { - OS << getQualifiedName(Regs[AliasesHashTable[2*i]].TheDef) << ", " - << getQualifiedName(Regs[AliasesHashTable[2*i+1]].TheDef) << ", \n"; - } else { - OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n"; - } - } - - unsigned Idx = AliasesHashTableSize*2-2; - if (AliasesHashTable[Idx] != ~0U) { - OS << " " - << getQualifiedName(Regs[AliasesHashTable[Idx]].TheDef) << ", " - << getQualifiedName(Regs[AliasesHashTable[Idx+1]].TheDef) << " };\n"; - } else { - OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n"; - } - - OS << " const unsigned AliasesHashTableSize = " - << AliasesHashTableSize << ";\n"; - } else { - OS << " const unsigned AliasesHashTable[] = { ~0U, ~0U };\n" - << " const unsigned AliasesHashTableSize = 1;\n"; + unsigned RegNo = Regs[i].EnumValue; + const CodeGenRegister::Set &O = Overlaps[&Regs[i]]; + for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end(); + I != E; ++I) + if (*I != &Regs[i]) + HTData.push_back(UUPair(RegNo, (*I)->EnumValue)); } - - delete [] AliasesHashTable; - - if (!RegisterAliases.empty()) - OS << "\n\n // Register Overlap Lists...\n"; + generateHashTable(OS, "AliasesHashTable", HTData); // Emit an overlap list for all registers. for (unsigned i = 0, e = Regs.size(); i != e; ++i) { From stoklund at 2pi.dk Sun Jun 12 00:04:29 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Sun, 12 Jun 2011 07:04:29 -0000 Subject: [llvm-commits] [llvm] r132887 - /llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Message-ID: <20110612070429.0C7682A6C12D@llvm.org> Author: stoklund Date: Sun Jun 12 02:04:28 2011 New Revision: 132887 URL: http://llvm.org/viewvc/llvm-project?rev=132887&view=rev Log: Remove now dead code. These computations have been moved to CodeGenRegisters.cpp. Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=132887&r1=132886&r2=132887&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Sun Jun 12 02:04:28 2011 @@ -126,49 +126,6 @@ OS << "} // End llvm namespace \n"; } -static void addSuperReg(Record *R, Record *S, - std::map, LessRecord> &SubRegs, - std::map, LessRecord> &SuperRegs, - std::map, LessRecord> &Aliases) { - if (R == S) { - errs() << "Error: recursive sub-register relationship between" - << " register " << getQualifiedName(R) - << " and its sub-registers?\n"; - abort(); - } - if (!SuperRegs[R].insert(S).second) - return; - SubRegs[S].insert(R); - Aliases[R].insert(S); - Aliases[S].insert(R); - if (SuperRegs.count(S)) - for (std::set::iterator I = SuperRegs[S].begin(), - E = SuperRegs[S].end(); I != E; ++I) - addSuperReg(R, *I, SubRegs, SuperRegs, Aliases); -} - -static void addSubSuperReg(Record *R, Record *S, - std::map, LessRecord> &SubRegs, - std::map, LessRecord> &SuperRegs, - std::map, LessRecord> &Aliases) { - if (R == S) { - errs() << "Error: recursive sub-register relationship between" - << " register " << getQualifiedName(R) - << " and its sub-registers?\n"; - abort(); - } - - if (!SubRegs[R].insert(S).second) - return; - addSuperReg(S, R, SubRegs, SuperRegs, Aliases); - Aliases[R].insert(S); - Aliases[S].insert(R); - if (SubRegs.count(S)) - for (std::set::iterator I = SubRegs[S].begin(), - E = SubRegs[S].end(); I != E; ++I) - addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases); -} - typedef std::pair UUPair; typedef std::vector UUVector; @@ -465,52 +422,10 @@ << "RegClass,\n"; OS << " };\n"; - // Emit register sub-registers / super-registers, aliases... - std::map, LessRecord> RegisterSubRegs; - std::map, LessRecord> RegisterSuperRegs; - std::map, LessRecord> RegisterAliases; typedef std::map, LessRecord> DwarfRegNumsMapTy; DwarfRegNumsMapTy DwarfRegNums; - const std::vector &Regs = Target.getRegisters(); - for (unsigned i = 0, e = Regs.size(); i != e; ++i) { - Record *R = Regs[i].TheDef; - std::vector LI = Regs[i].TheDef->getValueAsListOfDefs("Aliases"); - // Add information that R aliases all of the elements in the list... and - // that everything in the list aliases R. - for (unsigned j = 0, e = LI.size(); j != e; ++j) { - Record *Reg = LI[j]; - if (RegisterAliases[R].count(Reg)) - errs() << "Warning: register alias between " << getQualifiedName(R) - << " and " << getQualifiedName(Reg) - << " specified multiple times!\n"; - RegisterAliases[R].insert(Reg); - - if (RegisterAliases[Reg].count(R)) - errs() << "Warning: register alias between " << getQualifiedName(R) - << " and " << getQualifiedName(Reg) - << " specified multiple times!\n"; - RegisterAliases[Reg].insert(R); - } - } - - // Process sub-register sets. - for (unsigned i = 0, e = Regs.size(); i != e; ++i) { - Record *R = Regs[i].TheDef; - std::vector LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs"); - // Process sub-register set and add aliases information. - for (unsigned j = 0, e = LI.size(); j != e; ++j) { - Record *SubReg = LI[j]; - if (RegisterSubRegs[R].count(SubReg)) - errs() << "Warning: register " << getQualifiedName(SubReg) - << " specified as a sub-register of " << getQualifiedName(R) - << " multiple times!\n"; - addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs, - RegisterAliases); - } - } - // Print the SubregHashTable, a simple quadratically probed // hash table for determining if a register is a subregister // of another register. From stoklund at 2pi.dk Sun Jun 12 00:04:32 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Sun, 12 Jun 2011 07:04:32 -0000 Subject: [llvm-commits] [llvm] r132888 - in /llvm/trunk: include/llvm/Target/TargetRegisterInfo.h utils/TableGen/RegisterInfoEmitter.cpp Message-ID: <20110612070432.4CAC82A6C12E@llvm.org> Author: stoklund Date: Sun Jun 12 02:04:32 2011 New Revision: 132888 URL: http://llvm.org/viewvc/llvm-project?rev=132888&view=rev Log: Tweak hash function and compress hash tables. Make the hash tables as small as possible while ensuring that all lookups can be done in less than 8 probes. Cut the aliases hash table in half by only storing a < b pairs - it is a symmetric relation. Use larger multipliers on the initial hash function to ensure that it properly covers the whole table, and to resolve some clustering in the very regular ARM register bank. This reduces the size of most of these tables by 4x - 8x. For instance, the ARM tables shrink from 48 KB to 8 KB. Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=132888&r1=132887&r2=132888&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Sun Jun 12 02:04:32 2011 @@ -471,19 +471,21 @@ if (regA == regB) return true; + if (regA > regB) + std::swap(regA, regB); + if (isVirtualRegister(regA) || isVirtualRegister(regB)) return false; // regA and regB are distinct physical registers. Do they alias? - size_t index = (regA + regB * 37) & (AliasesHashSize-1); - unsigned ProbeAmt = 0; - while (AliasesHash[index*2] != 0 && - AliasesHash[index*2+1] != 0) { + size_t index = (regA * 11 + regB * 97) & (AliasesHashSize-1); + unsigned ProbeAmt = 1; + while (AliasesHash[index*2] != 0 && AliasesHash[index*2+1] != 0) { if (AliasesHash[index*2] == regA && AliasesHash[index*2+1] == regB) return true; index = (index + ProbeAmt) & (AliasesHashSize-1); - ProbeAmt += 2; + ProbeAmt += 1; } return false; @@ -493,15 +495,14 @@ /// bool isSubRegister(unsigned regA, unsigned regB) const { // SubregHash is a simple quadratically probed hash table. - size_t index = (regA + regB * 37) & (SubregHashSize-1); - unsigned ProbeAmt = 2; - while (SubregHash[index*2] != 0 && - SubregHash[index*2+1] != 0) { + size_t index = (regA * 11 + regB * 97) & (SubregHashSize-1); + unsigned ProbeAmt = 1; + while (SubregHash[index*2] != 0 && SubregHash[index*2+1] != 0) { if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB) return true; index = (index + ProbeAmt) & (SubregHashSize-1); - ProbeAmt += 2; + ProbeAmt += 1; } return false; Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=132888&r1=132887&r2=132888&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Sun Jun 12 02:04:32 2011 @@ -137,27 +137,31 @@ unsigned HSize = Data.size(); UUVector HT; - // Hashtable size must be a power of two. - HSize = 2 * NextPowerOf2(2 * HSize); - HT.assign(HSize, Sentinel); - - // Insert all entries. - unsigned MaxProbes = 0; - for (unsigned i = 0, e = Data.size(); i != e; ++i) { - UUPair D = Data[i]; - unsigned Idx = (D.first + D.second * 37) & (HSize - 1); - unsigned ProbeAmt = 2; - while (HT[Idx] != Sentinel) { - Idx = (Idx + ProbeAmt) & (HSize - 1); - ProbeAmt += 2; + // Grow the hash table until all entries can be found in less than 8 probes. + unsigned MaxProbes; + do { + // Hashtable size must be a power of two. + HSize = NextPowerOf2(HSize); + HT.assign(HSize, Sentinel); + + // Insert all entries. + MaxProbes = 0; + for (unsigned i = 0, e = Data.size(); i != e; ++i) { + UUPair D = Data[i]; + unsigned Idx = (D.first * 11 + D.second * 97) & (HSize - 1); + unsigned ProbeAmt = 1; + while (HT[Idx] != Sentinel) { + Idx = (Idx + ProbeAmt) & (HSize - 1); + ProbeAmt += 1; + } + HT[Idx] = D; + MaxProbes = std::max(MaxProbes, ProbeAmt); } - HT[Idx] = D; - MaxProbes = std::max(MaxProbes, ProbeAmt/2); - } + OS << "\n // Max number of probes: " << MaxProbes; + } while (MaxProbes >= 8); // Print the hash table. - OS << "\n\n // Max number of probes: " << MaxProbes - << "\n // Used entries: " << Data.size() + OS << "\n // Used entries: " << Data.size() << "\n const unsigned " << Name << "Size = " << HSize << ';' << "\n const unsigned " << Name << "[] = {\n"; @@ -441,13 +445,14 @@ // Print the AliasHashTable, a simple quadratically probed // hash table for determining if a register aliases another register. + // Since the overlaps() relation is symmetric, only store a < b pairs. HTData.clear(); for (unsigned i = 0, e = Regs.size(); i != e; ++i) { unsigned RegNo = Regs[i].EnumValue; const CodeGenRegister::Set &O = Overlaps[&Regs[i]]; for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end(); I != E; ++I) - if (*I != &Regs[i]) + if (RegNo < (*I)->EnumValue) HTData.push_back(UUPair(RegNo, (*I)->EnumValue)); } generateHashTable(OS, "AliasesHashTable", HTData); From rafael.espindola at gmail.com Sun Jun 12 00:38:02 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Sun, 12 Jun 2011 03:38:02 -0400 Subject: [llvm-commits] [llvm] r132882 - in /llvm/trunk: lib/CodeGen/AsmPrinter/AsmPrinter.cpp lib/Target/X86/X86InstrInfo.cpp test/CodeGen/Thumb2/machine-licm.ll In-Reply-To: <22E522CD-27D8-4C2D-A89E-3F9004CC9D3C@2pi.dk> References: <20110612032033.086FB2A6C12C@llvm.org> <22E522CD-27D8-4C2D-A89E-3F9004CC9D3C@2pi.dk> Message-ID: <4DF46CDA.9030509@gmail.com> > The double-CFG-edge hack was added as a compile time optimization. > > While I like to see it go, we should at least confirm that it was a > premature optimization. > > Did you measure before/after compile times? The -O0 compile times are > extra interesting. I compiled two release versions of clang. One before my first patch and one after the last one. I then used those to build a debug version of clang. The current trunk took 5m13.630s to build a debug version of clang. The old revision took 5m11.130s. Is there some other test you would like me to run? > /jakob > Cheers, Rafael From stoklund at 2pi.dk Sun Jun 12 00:57:06 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Sun, 12 Jun 2011 00:57:06 -0700 Subject: [llvm-commits] [llvm] r132882 - in /llvm/trunk: lib/CodeGen/AsmPrinter/AsmPrinter.cpp lib/Target/X86/X86InstrInfo.cpp test/CodeGen/Thumb2/machine-licm.ll In-Reply-To: <4DF46CDA.9030509@gmail.com> References: <20110612032033.086FB2A6C12C@llvm.org> <22E522CD-27D8-4C2D-A89E-3F9004CC9D3C@2pi.dk> <4DF46CDA.9030509@gmail.com> Message-ID: <5EA38794-3EAE-4F93-90AB-7683CEF05AFF@2pi.dk> On Jun 12, 2011, at 12:38 AM, Rafael Ávila de Espíndola wrote: > > The double-CFG-edge hack was added as a compile time optimization. >> >> While I like to see it go, we should at least confirm that it was a >> premature optimization. >> >> Did you measure before/after compile times? The -O0 compile times are >> extra interesting. > > I compiled two release versions of clang. One before my first patch and one after the last one. I then used those to build a debug version of clang. > > The current trunk took 5m13.630s to build a debug version of clang. The old revision took 5m11.130s. > > Is there some other test you would like me to run? It think it's OK. Here is what I measure on 403.gcc with llc -O0 -time-passes: Before: 0.6719 ( 12.9%) 0.0624 ( 14.7%) 0.7343 ( 13.0%) 0.7345 ( 13.0%) X86 AT&T-Style Assembly Printer After: 0.6873 ( 13.1%) 0.0628 ( 14.8%) 0.7501 ( 13.3%) 0.7501 ( 13.3%) X86 AT&T-Style Assembly Printer Thanks, /jakob From rafael.espindola at gmail.com Sun Jun 12 07:43:25 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Sun, 12 Jun 2011 10:43:25 -0400 Subject: [llvm-commits] [llvm] r132882 - in /llvm/trunk: lib/CodeGen/AsmPrinter/AsmPrinter.cpp lib/Target/X86/X86InstrInfo.cpp test/CodeGen/Thumb2/machine-licm.ll In-Reply-To: <5EA38794-3EAE-4F93-90AB-7683CEF05AFF@2pi.dk> References: <20110612032033.086FB2A6C12C@llvm.org> <22E522CD-27D8-4C2D-A89E-3F9004CC9D3C@2pi.dk> <4DF46CDA.9030509@gmail.com> <5EA38794-3EAE-4F93-90AB-7683CEF05AFF@2pi.dk> Message-ID: <4DF4D08D.8040409@gmail.com> > It think it's OK. Here is what I measure on 403.gcc with llc -O0 -time-passes: > > Before: > 0.6719 ( 12.9%) 0.0624 ( 14.7%) 0.7343 ( 13.0%) 0.7345 ( 13.0%) X86 AT&T-Style Assembly Printer > After: > 0.6873 ( 13.1%) 0.0628 ( 14.8%) 0.7501 ( 13.3%) 0.7501 ( 13.3%) X86 AT&T-Style Assembly Printer If needed, we could try adding a dedicated backend callback (with a default implementation). What I found really scary about it is that grep found 29 uses of succ_size in lib. In most cases I think it might just disable optimizations when they see a 3 instead of a 2, but it is hard to be sure. > Thanks, > /jakob > Cheers, Rafael From nadav.rotem at intel.com Sun Jun 12 07:40:30 2011 From: nadav.rotem at intel.com (Nadav Rotem) Date: Sun, 12 Jun 2011 14:40:30 -0000 Subject: [llvm-commits] [llvm] r132891 - /llvm/trunk/include/llvm/Target/TargetLowering.h Message-ID: <20110612144030.A53A92A6C12C@llvm.org> Author: nadav Date: Sun Jun 12 09:40:30 2011 New Revision: 132891 URL: http://llvm.org/viewvc/llvm-project?rev=132891&view=rev Log: Bugfix: When looking for a legal vector type, stop looking when a non-simple element type is found. This fix addresses some of the tests in Duncan's testcase (forthcoming). Modified: llvm/trunk/include/llvm/Target/TargetLowering.h Modified: llvm/trunk/include/llvm/Target/TargetLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=132891&r1=132890&r2=132891&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetLowering.h Sun Jun 12 09:40:30 2011 @@ -1853,6 +1853,7 @@ // If there is no simple vector type with this many elements then there // cannot be a larger legal vector type. Note that this assumes that // there are no skipped intermediate vector types in the simple types. + if (!EltVT.isSimple()) break; MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); if (LargerVector == MVT()) break; From nadav.rotem at intel.com Sun Jun 12 07:49:38 2011 From: nadav.rotem at intel.com (Nadav Rotem) Date: Sun, 12 Jun 2011 14:49:38 -0000 Subject: [llvm-commits] [llvm] r132892 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Message-ID: <20110612144938.D0C6E2A6C12C@llvm.org> Author: nadav Date: Sun Jun 12 09:49:38 2011 New Revision: 132892 URL: http://llvm.org/viewvc/llvm-project?rev=132892&view=rev Log: Improve the generated code by getCopyFromPartsVector for promoted integer types. Instead of scalarizing, and doing an element-by-element truncat, use vector truncate. Add support for scalarization of vectors: i8 -> <1 x i1> (from Duncan's testcase). Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=132892&r1=132891&r2=132892&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Sun Jun 12 09:49:38 2011 @@ -286,22 +286,10 @@ assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() && "Cannot handle this kind of promotion"); // Promoted vector extract - unsigned NumElts = ValueVT.getVectorNumElements(); - SmallVector NewOps; - for (unsigned i = 0; i < NumElts; ++i) { - SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, - PartVT.getScalarType(), Val ,DAG.getIntPtrConstant(i)); - SDValue Cast; + bool Smaller = ValueVT.bitsLE(PartVT); + return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), + DL, ValueVT, Val); - bool Smaller = ValueVT.bitsLE(PartVT); - - Cast = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), - DL, ValueVT.getScalarType(), Ext); - - NewOps.push_back(Cast); - } - return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, - &NewOps[0], NewOps.size()); } // Trivial bitcast if the types are the same size and the destination @@ -310,9 +298,17 @@ TLI.isTypeLegal(ValueVT)) return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); - assert(ValueVT.getVectorElementType() == PartVT && - ValueVT.getVectorNumElements() == 1 && + // Handle cases such as i8 -> <1 x i1> + assert(ValueVT.getVectorNumElements() == 1 && "Only trivial scalar-to-vector conversions should get here!"); + + if (ValueVT.getVectorNumElements() == 1 && + ValueVT.getVectorElementType() != PartVT) { + bool Smaller = ValueVT.bitsLE(PartVT); + Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), + DL, ValueVT.getScalarType(), Val); + } + return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); } @@ -453,7 +449,7 @@ // Bitconvert vector->vector case. Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); } else if (PartVT.isVector() && - PartVT.getVectorElementType() == ValueVT.getVectorElementType()&& + PartVT.getVectorElementType() == ValueVT.getVectorElementType() && PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { EVT ElementVT = PartVT.getVectorElementType(); // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in @@ -475,7 +471,7 @@ //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); } else if (PartVT.isVector() && PartVT.getVectorElementType().bitsGE( - ValueVT.getVectorElementType())&& + ValueVT.getVectorElementType()) && PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) { // Promoted vector extract @@ -492,11 +488,14 @@ &NewOps[0], NewOps.size()); } else{ // Vector -> scalar conversion. - assert(ValueVT.getVectorElementType() == PartVT && - ValueVT.getVectorNumElements() == 1 && + assert(ValueVT.getVectorNumElements() == 1 && "Only trivial vector-to-scalar conversions should get here!"); Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val, DAG.getIntPtrConstant(0)); + + bool Smaller = ValueVT.bitsLE(PartVT); + Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), + DL, PartVT, Val); } Parts[0] = Val; From nadav.rotem at intel.com Sun Jun 12 07:56:55 2011 From: nadav.rotem at intel.com (Nadav Rotem) Date: Sun, 12 Jun 2011 14:56:55 -0000 Subject: [llvm-commits] [llvm] r132893 - /llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Message-ID: <20110612145655.7446E2A6C12C@llvm.org> Author: nadav Date: Sun Jun 12 09:56:55 2011 New Revision: 132893 URL: http://llvm.org/viewvc/llvm-project?rev=132893&view=rev Log: Fix a bug in the calculation of the vectorTypeBreakdown into registers. Odd types such as i33 were rounded to i32. Originated from Duncan's testcase. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=132893&r1=132892&r2=132893&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Sun Jun 12 09:56:55 2011 @@ -673,10 +673,16 @@ NewVT = EltTy; IntermediateVT = NewVT; + unsigned NewVTSize = NewVT.getSizeInBits(); + + // Convert sizes such as i33 to i64. + if (!isPowerOf2_32(NewVTSize)) + NewVTSize = NextPowerOf2(NewVTSize); + EVT DestVT = TLI->getRegisterType(NewVT); RegisterVT = DestVT; if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. - return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); + return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); // Otherwise, promotion or legal types use the same number of registers as // the vector decimated to the appropriate level. @@ -965,8 +971,14 @@ EVT DestVT = getRegisterType(Context, NewVT); RegisterVT = DestVT; + unsigned NewVTSize = NewVT.getSizeInBits(); + + // Convert sizes such as i33 to i64. + if (!isPowerOf2_32(NewVTSize)) + NewVTSize = NextPowerOf2(NewVTSize); + if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. - return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); + return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); // Otherwise, promotion or legal types use the same number of registers as // the vector decimated to the appropriate level. @@ -1762,9 +1774,9 @@ case ISD::BITCAST: // If this is an FP->Int bitcast and if the sign bit is the only // thing demanded, turn this into a FGETSIGN. - if (NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) && - Op.getOperand(0).getValueType().isFloatingPoint() && - !Op.getOperand(0).getValueType().isVector()) { + if (!Op.getOperand(0).getValueType().isVector() && + NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) && + Op.getOperand(0).getValueType().isFloatingPoint()) { bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType()); bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) { From syoyofujita at gmail.com Sun Jun 12 08:15:05 2011 From: syoyofujita at gmail.com (Syoyo Fujita) Date: Mon, 13 Jun 2011 00:15:05 +0900 Subject: [llvm-commits] Fix sitofp and fpextend codegen for x86/AVX[PR9473] In-Reply-To: References: Message-ID: Hello Bruno, Attached is a modified patch for fpextend codegen. +let Predicates = [HasAVX] in + def : Pat<(fextend (loadf32 addr:$src)), + (VCVTSS2SDrm (f32 (EXTRACT_SUBREG (AVX_SET0PS), sub_ss)), addr:$src)>; + I've removed VCVTSS2SDrm_alt and use (f32 (EXTRACT_SUBREG (AVX_SET0PS), sub_ss)) to provide ZERO-filled register. I know this is redundant, but it works and I cannot find any good way so far( (f32 0) cause TblGen error btw). >> A better solution, since this instruction is dealing with F32 reg >> classes and the high bits won't be touched, is to declare VCVTSS2SDrm >> as having Constraints = "$src1 = $dst", but keep printing its operands >> as usual. Also, you can do the pattern matching inline in the >> instruction definition, no need to do it as a Pat here. I believe you >> can do something similar to VCVTSI2SD_alt. Unfortunately, Constraints = "$src1 = $dst" for VCVTSS2SD cause TblGen error. It seems that with VEX_4 attribute, you must specify different (virtual) registers. In the next, I'll send a modified patch of sitofp codegen for x86/AVX codegen. -- Syoyo On Fri, Jun 3, 2011 at 1:12 AM, Syoyo Fujita wrote: > Hello Bruno, > > Thanks for the advice, > >> From the intel manual: >> >> VCVTSS2SD- Convert one single-precision floating-point value in >> xmm3/m32 to one double-precision floating- point value and merge with >> high bits of xmm2. >> >> And, according to your patch: >> >> +let isAsmParserOnly = 1 in { >> +  def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), >> +                      (ins FR32:$src1, f32mem:$src2), >> +                      "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}", >> +                      []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>; >> +} >> + >> +def VCVTSS2SDrm_alt : I<0x5A, MRMSrcMem, (outs FR64:$dst), >> +                    (ins f32mem:$src), >> +                    "vcvtss2sd\t{$src, $src, $dst|$dst, $src, $src}", >> +                    []>, XS, VEX, Requires<[HasAVX, OptForSize]>; >> >> The "alt" version is using a different encoding, this isn't correct, >> since there's only one encoding for the "rm" version, which is the >> "VEX_4V" one. There is no need for the "alt" version actually, but to >> follow the manual "merge with high bits of xmm2": >> >> Instead of doing: >> >> +def : Pat<(extloadf32 addr:$src), >> +          (VCVTSS2SDrm_alt addr:$src)>, >> >> You can do: >> >> def : Pat<(extloadf32 addr:$src2), >>          (VCVTSS2SDrm 0, addr:$src2)>, >> >> or something like that... > > > Ah, Its new for me. > Since I had no idea how to use 'dummy' rester in .td, I just tried to > solve the problem as in my patch. > I'll investigate to rewrite my patch with above expression('0' in > input register) > > >> A better solution, since this instruction is dealing with F32 reg >> classes and the high bits won't be touched, is to declare VCVTSS2SDrm >> as having Constraints = "$src1 = $dst", but keep printing its operands >> as usual. Also, you can do the pattern matching inline in the >> instruction definition, no need to do it as a Pat here. I believe you >> can do something similar to VCVTSI2SD_alt. >> > > Okay, I'll try it and resend my (modified) patch. > > -- > Syoyo > -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-Fix-isel-fail-when-codegen-ing-fpext-instruction-for.patch Type: application/octet-stream Size: 2250 bytes Desc: not available URL: From benny.kra at googlemail.com Sun Jun 12 08:26:54 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Sun, 12 Jun 2011 15:26:54 -0000 Subject: [llvm-commits] [llvm] r132895 - in /llvm/trunk: LICENSE.TXT autoconf/configure.ac configure Message-ID: <20110612152655.05A2A2A6C12D@llvm.org> Author: d0k Date: Sun Jun 12 10:26:54 2011 New Revision: 132895 URL: http://llvm.org/viewvc/llvm-project?rev=132895&view=rev Log: Happy new year. Only 163 days late! Modified: llvm/trunk/LICENSE.TXT llvm/trunk/autoconf/configure.ac llvm/trunk/configure Modified: llvm/trunk/LICENSE.TXT URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/LICENSE.TXT?rev=132895&r1=132894&r2=132895&view=diff ============================================================================== --- llvm/trunk/LICENSE.TXT (original) +++ llvm/trunk/LICENSE.TXT Sun Jun 12 10:26:54 2011 @@ -4,7 +4,7 @@ University of Illinois/NCSA Open Source License -Copyright (c) 2003-2010 University of Illinois at Urbana-Champaign. +Copyright (c) 2003-2011 University of Illinois at Urbana-Champaign. All rights reserved. Developed by: Modified: llvm/trunk/autoconf/configure.ac URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=132895&r1=132894&r2=132895&view=diff ============================================================================== --- llvm/trunk/autoconf/configure.ac (original) +++ llvm/trunk/autoconf/configure.ac Sun Jun 12 10:26:54 2011 @@ -35,8 +35,8 @@ dnl Provide a copyright substitution and ensure the copyright notice is included dnl in the output of --version option of the generated configure script. -AC_SUBST(LLVM_COPYRIGHT,["Copyright (c) 2003-2010 University of Illinois at Urbana-Champaign."]) -AC_COPYRIGHT([Copyright (c) 2003-2010 University of Illinois at Urbana-Champaign.]) +AC_SUBST(LLVM_COPYRIGHT,["Copyright (c) 2003-2011 University of Illinois at Urbana-Champaign."]) +AC_COPYRIGHT([Copyright (c) 2003-2011 University of Illinois at Urbana-Champaign.]) dnl Indicate that we require autoconf 2.59 or later. Ths is needed because we dnl use some autoconf macros only available in 2.59. Modified: llvm/trunk/configure URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=132895&r1=132894&r2=132895&view=diff ============================================================================== --- llvm/trunk/configure (original) +++ llvm/trunk/configure Sun Jun 12 10:26:54 2011 @@ -9,7 +9,7 @@ # This configure script is free software; the Free Software Foundation # gives unlimited permission to copy, distribute and modify it. # -# Copyright (c) 2003-2010 University of Illinois at Urbana-Champaign. +# Copyright (c) 2003-2011 University of Illinois at Urbana-Champaign. ## --------------------- ## ## M4sh Initialization. ## ## --------------------- ## @@ -1559,7 +1559,7 @@ This configure script is free software; the Free Software Foundation gives unlimited permission to copy, distribute and modify it. -Copyright (c) 2003-2010 University of Illinois at Urbana-Champaign. +Copyright (c) 2003-2011 University of Illinois at Urbana-Champaign. _ACEOF exit fi @@ -1921,7 +1921,7 @@ -LLVM_COPYRIGHT="Copyright (c) 2003-2010 University of Illinois at Urbana-Champaign." +LLVM_COPYRIGHT="Copyright (c) 2003-2011 University of Illinois at Urbana-Champaign." From baldrick at free.fr Sun Jun 12 08:48:43 2011 From: baldrick at free.fr (Duncan Sands) Date: Sun, 12 Jun 2011 17:48:43 +0200 Subject: [llvm-commits] [llvm] r132892 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp In-Reply-To: <20110612144938.D0C6E2A6C12C@llvm.org> References: <20110612144938.D0C6E2A6C12C@llvm.org> Message-ID: <4DF4DFDB.3070406@free.fr> Hi Nadav, > Improve the generated code by getCopyFromPartsVector for promoted integer types. > Instead of scalarizing, and doing an element-by-element truncat, use vector > truncate. > Add support for scalarization of vectors: i8 -> <1 x i1> (from Duncan's > testcase). thanks for working on this. What about getCopyToPartsVector? > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Sun Jun 12 09:49:38 2011 > @@ -310,9 +298,17 @@ > TLI.isTypeLegal(ValueVT)) > return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); > > - assert(ValueVT.getVectorElementType() == PartVT&& > - ValueVT.getVectorNumElements() == 1&& > + // Handle cases such as i8 -> <1 x i1> > + assert(ValueVT.getVectorNumElements() == 1&& > "Only trivial scalar-to-vector conversions should get here!"); > + > + if (ValueVT.getVectorNumElements() == 1&& No need to test for ValueVT.getVectorNumElements() == 1; you just checked this with an assertion. > @@ -492,11 +488,14 @@ > &NewOps[0], NewOps.size()); > } else{ > // Vector -> scalar conversion. > - assert(ValueVT.getVectorElementType() == PartVT&& > - ValueVT.getVectorNumElements() == 1&& > + assert(ValueVT.getVectorNumElements() == 1&& > "Only trivial vector-to-scalar conversions should get here!"); > Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, > PartVT, Val, DAG.getIntPtrConstant(0)); > + > + bool Smaller = ValueVT.bitsLE(PartVT); > + Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), > + DL, PartVT, Val); As a micro-optimization, I suggest you only do this if ValueVT.getVectorElementType() != PartVT. Ciao, Duncan. From Yousef.Shajrawi at amd.com Sun Jun 12 00:50:34 2011 From: Yousef.Shajrawi at amd.com (Shajrawi, Yousef) Date: Sun, 12 Jun 2011 03:50:34 -0400 Subject: [llvm-commits] patch for Bug #10125 Message-ID: Hi, I've reported bug #10125 about debug variables incorrectly deleted by LLVM in the Live Debug Variables pass: http://llvm.org/bugs/show_bug.cgi?id=10125 Attached is a patch resolving this bug via adding a check to live ins of a basic block (description is in bugzilla) Please see if this is suitable for adding to LLVM and/or please advise on what to do next, This is my first contribution to LLVM so I don't know the procedure... Thanks & Regards, ---Yousef -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: missing_var.patch Type: application/octet-stream Size: 585 bytes Desc: missing_var.patch URL: From hans at chromium.org Sun Jun 12 08:47:15 2011 From: hans at chromium.org (Hans Wennborg) Date: Sun, 12 Jun 2011 16:47:15 +0100 Subject: [llvm-commits] [Patch] SimplifyCFG: Forward switch condition value to phi node In-Reply-To: References: Message-ID: Hi Frits, Thanks for your comments! Attaching new patch that addresses the issue you pointed out. On Sat, Jun 11, 2011 at 6:51 PM, Frits van Bommel wrote: > I can't comment on whether this transformation is a good idea, but I > do have some remarks about your code: > > +  BasicBlock *Succ = Branch->getSuccessor(0); > + > +  for (BasicBlock::iterator I = Succ->begin(), E = Succ->end(); I != E; ++I) { > +    PHINode *PHI = dyn_cast(I); > +    if (!PHI) continue; > > All PHI nodes must be at the beginning of the basic block, before any > other instructions, so you can replace 'continue' with 'break' here. Ah, I forgot about that. > > +    int Idx = PHI->getBasicBlockIndex(BB); > +    if (Idx < 0) continue; > > Since PHI is in a successor of BB, the IR would be invalid if the PHI > didn't have an entry for it. You can replace the check with >  assert(Idx >= 0 && "PHI has no entry for predecessor?"); Fixed. > > +static bool ForwardSwitchConditionToPHI(SwitchInst *SI) { > +  PHINode *ForwardingNode = NULL; > +  SmallVector ForwardingNodeIndexes; > + > +  for (unsigned I = 1; I < SI->getNumCases(); ++I) { // 0 is the default case. > +    ConstantInt *CaseValue = SI->getCaseValue(I); > +    BasicBlock *CaseDest = SI->getSuccessor(I); > + > +    int PhiIndex; > +    PHINode *PHI = FindPHIForConditionForwarding(CaseValue, CaseDest, > +                                                 &PhiIndex); > +    if (!PHI) continue; > + > +    if (!ForwardingNode) > +      ForwardingNode = PHI; > +    else if (PHI != ForwardingNode) > +      continue; > + > +    ForwardingNodeIndexes.push_back(PhiIndex); > +  } > + > +  if (ForwardingNodeIndexes.size() < 2) > +    return false; > > I think the use of ForwardingNode here makes this code dependent on > the order of switch cases: if there are multiple blocks with eligible > PHIs (in different blocks), but the first one your loop encounters > happens to only have one switch case pointing at it then no change > will be made even though the others might still be transformable. > You're right. It should be easy enough to find and keep track of all eligible targets. -------------- next part -------------- A non-text attachment was scrubbed... Name: forward-switch-condition-to-phi2.patch Type: text/x-patch Size: 5508 bytes Desc: not available URL: From fvbommel at gmail.com Sun Jun 12 10:03:27 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Sun, 12 Jun 2011 19:03:27 +0200 Subject: [llvm-commits] patch for Bug #10125 In-Reply-To: References: Message-ID: On 12 June 2011 09:50, Shajrawi, Yousef wrote: > I’ve reported bug #10125 about debug variables incorrectly deleted by LLVM > in the Live Debug Variables pass: http://llvm.org/bugs/show_bug.cgi?id=10125 > > Attached is a patch resolving this bug via adding a check to live ins of a > basic block (description is in bugzilla) > > Please see if this is suitable for adding to LLVM and/or please advise on > what to do next, This is my first contribution to LLVM so I don’t know the > procedure… Looks like you're well on your way: you've identified a problem, tried to fix it, and sent a patch to the correct mailing list. I don't know this part of the code, but I do know you shouldn't use tabs in the LLVM code... From stoklund at 2pi.dk Sun Jun 12 10:44:37 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Sun, 12 Jun 2011 10:44:37 -0700 Subject: [llvm-commits] patch for Bug #10125 In-Reply-To: References: Message-ID: On Jun 12, 2011, at 12:50 AM, Shajrawi, Yousef wrote: > I’ve reported bug #10125 about debug variables incorrectly deleted by LLVM in the Live Debug Variables pass: http://llvm.org/bugs/show_bug.cgi?id=10125 > > Attached is a patch resolving this bug via adding a check to live ins of a basic block (description is in bugzilla) Hi Yousef, I think you are misunderstanding the purpose of the Live Debug Variables pass. It is supposed to remove all DBG_VALUE instructions. It builds a data structure that is easier to work with for the register allocator passes. After register allocation, the DBG_VALUE instructions are written back with references to the correct physical registers and spill slots. This is all necessary to keep track of debug variables while the register allocator coalesces and splits and spills live ranges. > Please see if this is suitable for adding to LLVM and/or please advise on what to do next, This is my first contribution to LLVM so I don’t know the procedure… You are on the right track, but please make sure that you describe the actual symptoms when you file a bug report. The behavior you describe sounds correct to me, and when I run your IR through the ARM backend, the result looks fine. So what caused you to file a bug in the first place? /jakob -------------- next part -------------- An HTML attachment was scrubbed... URL: From rafael.espindola at gmail.com Sun Jun 12 10:45:46 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Sun, 12 Jun 2011 13:45:46 -0400 Subject: [llvm-commits] [llvm] r132882 - in /llvm/trunk: lib/CodeGen/AsmPrinter/AsmPrinter.cpp lib/Target/X86/X86InstrInfo.cpp test/CodeGen/Thumb2/machine-licm.ll In-Reply-To: <5EA38794-3EAE-4F93-90AB-7683CEF05AFF@2pi.dk> References: <20110612032033.086FB2A6C12C@llvm.org> <22E522CD-27D8-4C2D-A89E-3F9004CC9D3C@2pi.dk> <4DF46CDA.9030509@gmail.com> <5EA38794-3EAE-4F93-90AB-7683CEF05AFF@2pi.dk> Message-ID: <4DF4FB4A.1050201@gmail.com> > It think it's OK. Here is what I measure on 403.gcc with llc -O0 -time-passes: > > Before: > 0.6719 ( 12.9%) 0.0624 ( 14.7%) 0.7343 ( 13.0%) 0.7345 ( 13.0%) X86 AT&T-Style Assembly Printer > After: > 0.6873 ( 13.1%) 0.0628 ( 14.8%) 0.7501 ( 13.3%) 0.7501 ( 13.3%) X86 AT&T-Style Assembly Printer Just to be sure, I decided to give the "gcc as a single file a try" the .bc file is in http://people.mozilla.org/~respindola/gcc.bc.bz2 I did 10 runs with both the old and new versions. I timed "llc -O0 gcc.bc -o gcc.o -filetype=obj -mc-relax-all". The best result with the old version was 0m6.527s, with the new one it was 0m6.485s. > Thanks, > /jakob > Cheers, Rafael From benny.kra at googlemail.com Sun Jun 12 15:47:53 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Sun, 12 Jun 2011 22:47:53 -0000 Subject: [llvm-commits] [llvm] r132896 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineCompares.cpp test/Transforms/InstCombine/cast.ll Message-ID: <20110612224753.3713D2A6C12C@llvm.org> Author: d0k Date: Sun Jun 12 17:47:53 2011 New Revision: 132896 URL: http://llvm.org/viewvc/llvm-project?rev=132896&view=rev Log: Simplify code. No functionality changes, name changes aside. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp llvm/trunk/test/Transforms/InstCombine/cast.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp?rev=132896&r1=132895&r2=132896&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp Sun Jun 12 17:47:53 2011 @@ -1087,19 +1087,14 @@ // have its sign bit set or if it is an equality comparison. // Extending a relational comparison when we're checking the sign // bit would not work. - if (Cast->hasOneUse() && - (ICI.isEquality() || - (AndCST->getValue().isNonNegative() && RHSV.isNonNegative()))) { - uint32_t BitWidth = - cast(Cast->getOperand(0)->getType())->getBitWidth(); - APInt NewCST = AndCST->getValue().zext(BitWidth); - APInt NewCI = RHSV.zext(BitWidth); - Value *NewAnd = + if (ICI.isEquality() || + (AndCST->getValue().isNonNegative() && RHSV.isNonNegative())) { + Value *NewAnd = Builder->CreateAnd(Cast->getOperand(0), - ConstantInt::get(ICI.getContext(), NewCST), - LHSI->getName()); + ConstantExpr::getZExt(AndCST, Cast->getSrcTy())); + NewAnd->takeName(LHSI); return new ICmpInst(ICI.getPredicate(), NewAnd, - ConstantInt::get(ICI.getContext(), NewCI)); + ConstantExpr::getZExt(RHS, Cast->getSrcTy())); } } Modified: llvm/trunk/test/Transforms/InstCombine/cast.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/cast.ll?rev=132896&r1=132895&r2=132896&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/cast.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/cast.ll Sun Jun 12 17:47:53 2011 @@ -265,8 +265,8 @@ %C = and i32 %B, 42 ; [#uses=1] %D = icmp eq i32 %C, 10 ; [#uses=1] ret i1 %D -; CHECK: %C1 = and i64 %A, 42 -; CHECK: %D = icmp eq i64 %C1, 10 +; CHECK: %C = and i64 %A, 42 +; CHECK: %D = icmp eq i64 %C, 10 ; CHECK: ret i1 %D } From benny.kra at googlemail.com Sun Jun 12 15:48:00 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Sun, 12 Jun 2011 22:48:00 -0000 Subject: [llvm-commits] [llvm] r132897 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineCompares.cpp test/Transforms/InstCombine/icmp.ll Message-ID: <20110612224800.867FE2A6C12C@llvm.org> Author: d0k Date: Sun Jun 12 17:48:00 2011 New Revision: 132897 URL: http://llvm.org/viewvc/llvm-project?rev=132897&view=rev Log: InstCombine: Shrink ((zext X) & C1) == C2 to fold away the cast if the "zext" and the "and" have one use. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp llvm/trunk/test/Transforms/InstCombine/icmp.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp?rev=132897&r1=132896&r2=132897&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp Sun Jun 12 17:48:00 2011 @@ -1097,7 +1097,23 @@ ConstantExpr::getZExt(RHS, Cast->getSrcTy())); } } - + + // If the LHS is an AND of a zext, and we have an equality compare, we can + // shrink the and/compare to the smaller type, eliminating the cast. + if (ZExtInst *Cast = dyn_cast(LHSI->getOperand(0))) { + const IntegerType *Ty = cast(Cast->getSrcTy()); + // Make sure we don't compare the upper bits, SimplifyDemandedBits + // should fold the icmp to true/false in that case. + if (ICI.isEquality() && RHSV.getActiveBits() <= Ty->getBitWidth()) { + Value *NewAnd = + Builder->CreateAnd(Cast->getOperand(0), + ConstantExpr::getTrunc(AndCST, Ty)); + NewAnd->takeName(LHSI); + return new ICmpInst(ICI.getPredicate(), NewAnd, + ConstantExpr::getTrunc(RHS, Ty)); + } + } + // If this is: (X >> C1) & C2 != C3 (where any shift and any compare // could exist), turn it into (X & (C2 << C1)) != (C3 << C1). This // happens a LOT in code produced by the C front-end, for bitfield Modified: llvm/trunk/test/Transforms/InstCombine/icmp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/icmp.ll?rev=132897&r1=132896&r2=132897&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/icmp.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/icmp.ll Sun Jun 12 17:48:00 2011 @@ -521,3 +521,13 @@ %z = icmp eq i32 %x, %y ret i1 %z } + +; CHECK: @test54 +; CHECK-NEXT: %and = and i8 %a, -64 +; CHECK-NEXT icmp eq i8 %and, -128 +define i1 @test54(i8 %a) nounwind { + %ext = zext i8 %a to i32 + %and = and i32 %ext, 192 + %ret = icmp eq i32 %and, 128 + ret i1 %ret +} From geek4civic at gmail.com Sun Jun 12 17:51:36 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Mon, 13 Jun 2011 09:51:36 +0900 Subject: [llvm-commits] [MSVC] Possible miscompilation on TargetLoweringObjectFileELF::emitPersonalityValue() Message-ID: On Release and MinSizeRel, test/CodeGen/X86/no-cfi.ll barfs. not on Debug and RelWithDbginfo. I made a reduced patch, to suppress "g" on TargetLoweringObjectFileELF::emitPersonalityValue(). Any idea? ...Takumi --- lib/CodeGen/TargetLoweringObjectFileImpl.cpp | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-TargetLoweringObjectFileELF-emitPersonalityValue.patch.txt Type: text/x-patch Size: 962 bytes Desc: not available URL: From rafael.espindola at gmail.com Sun Jun 12 20:09:13 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Mon, 13 Jun 2011 03:09:13 -0000 Subject: [llvm-commits] [llvm] r132898 - /llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Message-ID: <20110613030913.C82342A6C12C@llvm.org> Author: rafael Date: Sun Jun 12 22:09:13 2011 New Revision: 132898 URL: http://llvm.org/viewvc/llvm-project?rev=132898&view=rev Log: Fix invalid uses of Twine. Hopefully this fixes the problem that Takumi is having. Modified: llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Modified: llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp?rev=132898&r1=132897&r2=132898&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp (original) +++ llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Sun Jun 12 22:09:13 2011 @@ -189,8 +189,8 @@ return Mang->getSymbol(GV); break; case dwarf::DW_EH_PE_pcrel: { - Twine FullName = StringRef("DW.ref.") + Mang->getSymbol(GV)->getName(); - return getContext().GetOrCreateSymbol(FullName); + return getContext().GetOrCreateSymbol(StringRef("DW.ref.") + + Mang->getSymbol(GV)->getName()); break; } } @@ -199,13 +199,13 @@ void TargetLoweringObjectFileELF::emitPersonalityValue(MCStreamer &Streamer, const TargetMachine &TM, const MCSymbol *Sym) const { - Twine FullName = StringRef("DW.ref.") + Sym->getName(); - MCSymbol *Label = getContext().GetOrCreateSymbol(FullName); + SmallString<64> NameData("DW.ref."); + NameData += Sym->getName(); + MCSymbol *Label = getContext().GetOrCreateSymbol(NameData); Streamer.EmitSymbolAttribute(Label, MCSA_Hidden); Streamer.EmitSymbolAttribute(Label, MCSA_Weak); - Twine SectionName = StringRef(".data.") + Label->getName(); - SmallString<64> NameData; - SectionName.toVector(NameData); + StringRef Prefix = ".data."; + NameData.insert(NameData.begin(), Prefix.begin(), Prefix.end()); unsigned Flags = ELF::SHF_ALLOC | ELF::SHF_WRITE | ELF::SHF_GROUP; const MCSection *Sec = getContext().getELFSection(NameData, ELF::SHT_PROGBITS, From rafael.espindola at gmail.com Sun Jun 12 20:15:34 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Sun, 12 Jun 2011 23:15:34 -0400 Subject: [llvm-commits] [MSVC] Possible miscompilation on TargetLoweringObjectFileELF::emitPersonalityValue() In-Reply-To: References: Message-ID: <4DF580D6.6070904@gmail.com> On 11-06-12 8:51 PM, NAKAMURA Takumi wrote: > On Release and MinSizeRel, test/CodeGen/X86/no-cfi.ll barfs. not on > Debug and RelWithDbginfo. > > I made a reduced patch, to suppress "g" on > TargetLoweringObjectFileELF::emitPersonalityValue(). > > Any idea? ...Takumi Can you try 132898? Sorry for the bug. Thanks! Rafael From stoklund at 2pi.dk Sun Jun 12 20:26:42 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 13 Jun 2011 03:26:42 -0000 Subject: [llvm-commits] [llvm] r132899 - /llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp Message-ID: <20110613032642.DF3682A6C12C@llvm.org> Author: stoklund Date: Sun Jun 12 22:26:42 2011 New Revision: 132899 URL: http://llvm.org/viewvc/llvm-project?rev=132899&view=rev Log: Include callee-saved registers in debug output. Modified: llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp Modified: llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp?rev=132899&r1=132898&r2=132899&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp Sun Jun 12 22:26:42 2011 @@ -103,7 +103,7 @@ DEBUG({ dbgs() << "AllocationOrder(" << RC->getName() << ") = ["; - for (unsigned I = 0; I != N; ++I) + for (unsigned I = 0; I != RCI.NumRegs; ++I) dbgs() << ' ' << PrintReg(RCI.Order[I], TRI); dbgs() << " ]\n"; }); From stoklund at 2pi.dk Sun Jun 12 20:26:46 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 13 Jun 2011 03:26:46 -0000 Subject: [llvm-commits] [llvm] r132900 - in /llvm/trunk: lib/CodeGen/RegAllocFast.cpp test/CodeGen/ARM/fast-isel-static.ll test/CodeGen/X86/2011-06-12-FastAllocSpill.ll test/CodeGen/X86/fast-isel-gep.ll Message-ID: <20110613032646.C847F2A6C12D@llvm.org> Author: stoklund Date: Sun Jun 12 22:26:46 2011 New Revision: 132900 URL: http://llvm.org/viewvc/llvm-project?rev=132900&view=rev Log: Be less aggressive about hinting in RAFast. In particular, don't spill dirty registers only to satisfy a hint. It is not worth it. The attached test case provides an example where the fast allocator would spill a register when other registers are available. Added: llvm/trunk/test/CodeGen/X86/2011-06-12-FastAllocSpill.ll Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp llvm/trunk/test/CodeGen/ARM/fast-isel-static.ll llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=132900&r1=132899&r2=132900&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Sun Jun 12 22:26:46 2011 @@ -487,14 +487,12 @@ // Take hint when possible. if (Hint) { - switch(calcSpillCost(Hint)) { - default: - definePhysReg(MI, Hint, regFree); - // Fall through. - case 0: + // Ignore the hint if we would have to spill a dirty register. + unsigned Cost = calcSpillCost(Hint); + if (Cost < spillDirty) { + if (Cost) + definePhysReg(MI, Hint, regFree); return assignVirtToPhysReg(LRE, Hint); - case spillImpossible: - break; } } Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-static.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-static.ll?rev=132900&r1=132899&r2=132900&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-static.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-static.ll Sun Jun 12 22:26:46 2011 @@ -23,7 +23,7 @@ %z = alloca float, align 4 store float 0.000000e+00, float* %ztot, align 4 store float 1.000000e+00, float* %z, align 4 -; CHECK-LONG: blx r2 +; CHECK-LONG: blx r ; CHECK-NORM: bl _myadd call void @myadd(float* %ztot, float* %z) ret i32 0 Added: llvm/trunk/test/CodeGen/X86/2011-06-12-FastAllocSpill.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-06-12-FastAllocSpill.ll?rev=132900&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2011-06-12-FastAllocSpill.ll (added) +++ llvm/trunk/test/CodeGen/X86/2011-06-12-FastAllocSpill.ll Sun Jun 12 22:26:46 2011 @@ -0,0 +1,52 @@ +; RUN: llc < %s -O0 -disable-fp-elim -relocation-model=pic -stats |& FileCheck %s +; +; This test should not cause any spilling with RAFast. +; +; CHECK: Number of copies coalesced +; CHECK-NOT: Number of stores added +; +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" + +%0 = type { i64, i64, i8*, i8* } +%1 = type opaque +%2 = type opaque +%3 = type <{ i8*, i32, i32, void (%4*)*, i8*, i64 }> +%4 = type { i8**, i32, i32, i8**, %5*, i64 } +%5 = type { i64, i64 } +%6 = type { i8*, i32, i32, i8*, %5* } + + at 0 = external hidden constant %0 + +define hidden void @f() ssp { +bb: + %tmp5 = alloca i64, align 8 + %tmp6 = alloca void ()*, align 8 + %tmp7 = alloca %3, align 8 + store i64 0, i64* %tmp5, align 8 + br label %bb8 + +bb8: ; preds = %bb23, %bb + %tmp15 = getelementptr inbounds %3* %tmp7, i32 0, i32 4 + store i8* bitcast (%0* @0 to i8*), i8** %tmp15 + %tmp16 = bitcast %3* %tmp7 to void ()* + store void ()* %tmp16, void ()** %tmp6, align 8 + %tmp17 = load void ()** %tmp6, align 8 + %tmp18 = bitcast void ()* %tmp17 to %6* + %tmp19 = getelementptr inbounds %6* %tmp18, i32 0, i32 3 + %tmp20 = bitcast %6* %tmp18 to i8* + %tmp21 = load i8** %tmp19 + %tmp22 = bitcast i8* %tmp21 to void (i8*)* + call void %tmp22(i8* %tmp20) + br label %bb23 + +bb23: ; preds = %bb8 + %tmp24 = load i64* %tmp5, align 8 + %tmp25 = add i64 %tmp24, 1 + store i64 %tmp25, i64* %tmp5, align 8 + %tmp26 = icmp ult i64 %tmp25, 10 + br i1 %tmp26, label %bb8, label %bb27 + +bb27: ; preds = %bb23 + ret void +} Modified: llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll?rev=132900&r1=132899&r2=132900&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll (original) +++ llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll Sun Jun 12 22:26:46 2011 @@ -24,7 +24,7 @@ %t15 = load i32* %t9 ; [#uses=1] ret i32 %t15 ; X32: test2: -; X32: movl (%edx,%ecx,4), %eax +; X32: movl (%edx,%ecx,4), %e ; X32: ret ; X64: test2: From isanbard at gmail.com Sun Jun 12 23:23:02 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 13 Jun 2011 06:23:02 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r132904 - /llvm-gcc-4.2/trunk/gcc/testsuite/gcc.misc-tests/bprob.exp Message-ID: <20110613062302.8C4292A6C12C@llvm.org> Author: void Date: Mon Jun 13 01:23:02 2011 New Revision: 132904 URL: http://llvm.org/viewvc/llvm-project?rev=132904&view=rev Log: An attempt to make the buildbot happy. Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.misc-tests/bprob.exp Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.misc-tests/bprob.exp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.misc-tests/bprob.exp?rev=132904&r1=132903&r2=132904&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.misc-tests/bprob.exp (original) +++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.misc-tests/bprob.exp Mon Jun 13 01:23:02 2011 @@ -47,10 +47,12 @@ # Load support procs. load_lib profopt.exp -set profile_options "-fprofile-arcs -ftest-coverage" -set feedback_options "-fbranch-probabilities" +#set profile_options "-fprofile-arcs -ftest-coverage" +#set feedback_options "-fbranch-probabilities" +set profile_option "-fprofile-arcs -ftest-coverage" +set feedback_option "-fbranch-probabilities" -foreach profile_option $profile_options feedback_option $feedback_options { +#foreach profile_option $profile_options feedback_option $feedback_options { foreach src [lsort [glob -nocomplain $srcdir/$subdir/bprob-*.c]] { # If we're only testing specific files and this isn't one of them, skip it. if ![runtest_file_p $runtests $src] then { @@ -58,4 +60,4 @@ } profopt-execute $src } -} +#}