[llvm-commits] [llvm] r132411 - /llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp

[Evan Cheng]

On Jun 1, 2011, at 12:01 PM, Stuart Hastings wrote:

> 
> On Jun 1, 2011, at 11:56 AM, Evan Cheng wrote:
> 
>> Stuart, why is this hard coded to i32? Is fgetsign double -> i64 legal?
> 
> Yes, fgetsign of a double is not legal on x86_32 (because i64 isn't  legal on x86_32).

But your code first check
isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32)

So it's assuming if i64 fgetsign is legal then i32 fgetsign must be legal. This works for x86, but it may not work for some 64-bit arch which has no native support for i32.

> 
> Is there a better way to do this?

Your code should be restructured to check isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType())) first. If not, then it checks isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32) and generates a fgetsign + zero_extend if that's the case.

Evan

> 
> stuart
> 
>> 
>> Evan
>> 
>> On Jun 1, 2011, at 11:32 AM, Stuart Hastings wrote:
>> 
>>> Author: stuart
>>> Date: Wed Jun  1 13:32:25 2011
>>> New Revision: 132411
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=132411&view=rev
>>> Log:
>>> Fix double FGETSIGN to work on x86_32; followup to 132396.
>>> rdar://problem/5660695
>>> 
>>> Modified:
>>>  llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
>>> 
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=132411&r1=132410&r2=132411&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Wed Jun  1 13:32:25 2011
>>> @@ -1759,11 +1759,14 @@
>>>   if (NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
>>>       Op.getOperand(0).getValueType().isFloatingPoint() &&
>>>       !Op.getOperand(0).getValueType().isVector()) {
>>> -      if (isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType())) {
>>> +      if (isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32)) {
>>> +        EVT Ty = (isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType())) ?
>>> +          Op.getValueType() : MVT::i32;
>>>       // Make a FGETSIGN + SHL to move the sign bit into the appropriate
>>>       // place.  We expect the SHL to be eliminated by other optimizations.
>>> -        SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Op.getValueType(),
>>> -                                         Op.getOperand(0));
>>> +        SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
>>> +        if (Ty != Op.getValueType())
>>> +          Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
>>>       unsigned ShVal = Op.getValueType().getSizeInBits()-1;
>>>       SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
>>>       return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
>>> 
>>> 
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>> 
>